1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2019 Western Digital Corporation or its affiliates.
5 * Copyright (C) 2018 SiFive, Inc.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * The FU540 PRCI implements clock and reset control for the SiFive
19 * FU540-C000 chip. This driver assumes that it has sole control
20 * over all PRCI resources.
22 * This driver is based on the PRCI driver written by Wesley Terpstra.
24 * Refer, commit 999529edf517ed75b56659d456d221b2ee56bb60 of:
25 * https://github.com/riscv/riscv-linux
28 * - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset"
33 #include <clk-uclass.h>
39 #include <linux/math64.h>
40 #include <linux/clk/analogbits-wrpll-cln28hpc.h>
41 #include <dt-bindings/clk/sifive-fu540-prci.h>
44 * EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects:
47 #define EXPECTED_CLK_PARENT_COUNT 2
50 * Register offsets and bitmasks
54 #define PRCI_COREPLLCFG0_OFFSET 0x4
55 #define PRCI_COREPLLCFG0_DIVR_SHIFT 0
56 #define PRCI_COREPLLCFG0_DIVR_MASK (0x3f << PRCI_COREPLLCFG0_DIVR_SHIFT)
57 #define PRCI_COREPLLCFG0_DIVF_SHIFT 6
58 #define PRCI_COREPLLCFG0_DIVF_MASK (0x1ff << PRCI_COREPLLCFG0_DIVF_SHIFT)
59 #define PRCI_COREPLLCFG0_DIVQ_SHIFT 15
60 #define PRCI_COREPLLCFG0_DIVQ_MASK (0x7 << PRCI_COREPLLCFG0_DIVQ_SHIFT)
61 #define PRCI_COREPLLCFG0_RANGE_SHIFT 18
62 #define PRCI_COREPLLCFG0_RANGE_MASK (0x7 << PRCI_COREPLLCFG0_RANGE_SHIFT)
63 #define PRCI_COREPLLCFG0_BYPASS_SHIFT 24
64 #define PRCI_COREPLLCFG0_BYPASS_MASK (0x1 << PRCI_COREPLLCFG0_BYPASS_SHIFT)
65 #define PRCI_COREPLLCFG0_FSE_SHIFT 25
66 #define PRCI_COREPLLCFG0_FSE_MASK (0x1 << PRCI_COREPLLCFG0_FSE_SHIFT)
67 #define PRCI_COREPLLCFG0_LOCK_SHIFT 31
68 #define PRCI_COREPLLCFG0_LOCK_MASK (0x1 << PRCI_COREPLLCFG0_LOCK_SHIFT)
71 #define PRCI_DDRPLLCFG0_OFFSET 0xc
72 #define PRCI_DDRPLLCFG0_DIVR_SHIFT 0
73 #define PRCI_DDRPLLCFG0_DIVR_MASK (0x3f << PRCI_DDRPLLCFG0_DIVR_SHIFT)
74 #define PRCI_DDRPLLCFG0_DIVF_SHIFT 6
75 #define PRCI_DDRPLLCFG0_DIVF_MASK (0x1ff << PRCI_DDRPLLCFG0_DIVF_SHIFT)
76 #define PRCI_DDRPLLCFG0_DIVQ_SHIFT 15
77 #define PRCI_DDRPLLCFG0_DIVQ_MASK (0x7 << PRCI_DDRPLLCFG0_DIVQ_SHIFT)
78 #define PRCI_DDRPLLCFG0_RANGE_SHIFT 18
79 #define PRCI_DDRPLLCFG0_RANGE_MASK (0x7 << PRCI_DDRPLLCFG0_RANGE_SHIFT)
80 #define PRCI_DDRPLLCFG0_BYPASS_SHIFT 24
81 #define PRCI_DDRPLLCFG0_BYPASS_MASK (0x1 << PRCI_DDRPLLCFG0_BYPASS_SHIFT)
82 #define PRCI_DDRPLLCFG0_FSE_SHIFT 25
83 #define PRCI_DDRPLLCFG0_FSE_MASK (0x1 << PRCI_DDRPLLCFG0_FSE_SHIFT)
84 #define PRCI_DDRPLLCFG0_LOCK_SHIFT 31
85 #define PRCI_DDRPLLCFG0_LOCK_MASK (0x1 << PRCI_DDRPLLCFG0_LOCK_SHIFT)
88 #define PRCI_DDRPLLCFG1_OFFSET 0x10
89 #define PRCI_DDRPLLCFG1_CKE_SHIFT 24
90 #define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT)
93 #define PRCI_GEMGXLPLLCFG0_OFFSET 0x1c
94 #define PRCI_GEMGXLPLLCFG0_DIVR_SHIFT 0
95 #define PRCI_GEMGXLPLLCFG0_DIVR_MASK \
96 (0x3f << PRCI_GEMGXLPLLCFG0_DIVR_SHIFT)
97 #define PRCI_GEMGXLPLLCFG0_DIVF_SHIFT 6
98 #define PRCI_GEMGXLPLLCFG0_DIVF_MASK \
99 (0x1ff << PRCI_GEMGXLPLLCFG0_DIVF_SHIFT)
100 #define PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT 15
101 #define PRCI_GEMGXLPLLCFG0_DIVQ_MASK (0x7 << PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT)
102 #define PRCI_GEMGXLPLLCFG0_RANGE_SHIFT 18
103 #define PRCI_GEMGXLPLLCFG0_RANGE_MASK \
104 (0x7 << PRCI_GEMGXLPLLCFG0_RANGE_SHIFT)
105 #define PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT 24
106 #define PRCI_GEMGXLPLLCFG0_BYPASS_MASK \
107 (0x1 << PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT)
108 #define PRCI_GEMGXLPLLCFG0_FSE_SHIFT 25
109 #define PRCI_GEMGXLPLLCFG0_FSE_MASK \
110 (0x1 << PRCI_GEMGXLPLLCFG0_FSE_SHIFT)
111 #define PRCI_GEMGXLPLLCFG0_LOCK_SHIFT 31
112 #define PRCI_GEMGXLPLLCFG0_LOCK_MASK (0x1 << PRCI_GEMGXLPLLCFG0_LOCK_SHIFT)
115 #define PRCI_GEMGXLPLLCFG1_OFFSET 0x20
116 #define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 24
117 #define PRCI_GEMGXLPLLCFG1_CKE_MASK (0x1 << PRCI_GEMGXLPLLCFG1_CKE_SHIFT)
120 #define PRCI_CORECLKSEL_OFFSET 0x24
121 #define PRCI_CORECLKSEL_CORECLKSEL_SHIFT 0
122 #define PRCI_CORECLKSEL_CORECLKSEL_MASK \
123 (0x1 << PRCI_CORECLKSEL_CORECLKSEL_SHIFT)
125 /* DEVICESRESETREG */
126 #define PRCI_DEVICESRESETREG_OFFSET 0x28
127 #define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_SHIFT 0
128 #define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_MASK \
129 (0x1 << PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_SHIFT)
130 #define PRCI_DEVICESRESETREG_DDR_AXI_RST_N_SHIFT 1
131 #define PRCI_DEVICESRESETREG_DDR_AXI_RST_N_MASK \
132 (0x1 << PRCI_DEVICESRESETREG_DDR_AXI_RST_N_SHIFT)
133 #define PRCI_DEVICESRESETREG_DDR_AHB_RST_N_SHIFT 2
134 #define PRCI_DEVICESRESETREG_DDR_AHB_RST_N_MASK \
135 (0x1 << PRCI_DEVICESRESETREG_DDR_AHB_RST_N_SHIFT)
136 #define PRCI_DEVICESRESETREG_DDR_PHY_RST_N_SHIFT 3
137 #define PRCI_DEVICESRESETREG_DDR_PHY_RST_N_MASK \
138 (0x1 << PRCI_DEVICESRESETREG_DDR_PHY_RST_N_SHIFT)
139 #define PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT 5
140 #define PRCI_DEVICESRESETREG_GEMGXL_RST_N_MASK \
141 (0x1 << PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT)
143 /* CLKMUXSTATUSREG */
144 #define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c
145 #define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1
146 #define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK \
147 (0x1 << PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT)
154 * struct __prci_data - per-device-instance data
155 * @va: base virtual address of the PRCI IP block
156 * @parent: parent clk instance
158 * PRCI per-device instance data
166 * struct __prci_wrpll_data - WRPLL configuration and integration data
167 * @c: WRPLL current configuration record
168 * @bypass: fn ptr to code to bypass the WRPLL (if applicable; else NULL)
169 * @no_bypass: fn ptr to code to not bypass the WRPLL (if applicable; else NULL)
170 * @cfg0_offs: WRPLL CFG0 register offset (in bytes) from the PRCI base address
172 * @bypass and @no_bypass are used for WRPLL instances that contain a separate
173 * external glitchless clock mux downstream from the PLL. The WRPLL internal
174 * bypass mux is not glitchless.
176 struct __prci_wrpll_data {
177 struct analogbits_wrpll_cfg c;
178 void (*bypass)(struct __prci_data *pd);
179 void (*no_bypass)(struct __prci_data *pd);
185 struct __prci_clock_ops {
186 int (*set_rate)(struct __prci_clock *pc,
188 unsigned long parent_rate);
189 unsigned long (*round_rate)(struct __prci_clock *pc,
191 unsigned long *parent_rate);
192 unsigned long (*recalc_rate)(struct __prci_clock *pc,
193 unsigned long parent_rate);
197 * struct __prci_clock - describes a clock device managed by PRCI
198 * @name: user-readable clock name string - should match the manual
199 * @parent_name: parent name for this clock
200 * @ops: struct clk_ops for the Linux clock framework to use for control
201 * @hw: Linux-private clock data
202 * @pwd: WRPLL-specific data, associated with this clock (if not NULL)
203 * @pd: PRCI-specific data associated with this clock (if not NULL)
205 * PRCI clock data. Used by the PRCI driver to register PRCI-provided
206 * clocks to the Linux clock infrastructure.
208 struct __prci_clock {
210 const char *parent_name;
211 const struct __prci_clock_ops *ops;
212 struct __prci_wrpll_data *pwd;
213 struct __prci_data *pd;
221 * __prci_readl() - read from a PRCI register
223 * @offs: register offset to read from (in bytes, from PRCI base address)
225 * Read the register located at offset @offs from the base virtual
226 * address of the PRCI register target described by @pd, and return
227 * the value to the caller.
229 * Context: Any context.
231 * Return: the contents of the register described by @pd and @offs.
233 static u32 __prci_readl(struct __prci_data *pd, u32 offs)
235 return readl(pd->base + offs);
238 static void __prci_writel(u32 v, u32 offs, struct __prci_data *pd)
240 return writel(v, pd->base + offs);
243 /* WRPLL-related private functions */
246 * __prci_wrpll_unpack() - unpack WRPLL configuration registers into parameters
247 * @c: ptr to a struct analogbits_wrpll_cfg record to write config into
248 * @r: value read from the PRCI PLL configuration register
250 * Given a value @r read from an FU540 PRCI PLL configuration register,
251 * split it into fields and populate it into the WRPLL configuration record
254 * The COREPLLCFG0 macros are used below, but the other *PLLCFG0 macros
255 * have the same register layout.
257 * Context: Any context.
259 static void __prci_wrpll_unpack(struct analogbits_wrpll_cfg *c, u32 r)
263 v = r & PRCI_COREPLLCFG0_DIVR_MASK;
264 v >>= PRCI_COREPLLCFG0_DIVR_SHIFT;
267 v = r & PRCI_COREPLLCFG0_DIVF_MASK;
268 v >>= PRCI_COREPLLCFG0_DIVF_SHIFT;
271 v = r & PRCI_COREPLLCFG0_DIVQ_MASK;
272 v >>= PRCI_COREPLLCFG0_DIVQ_SHIFT;
275 v = r & PRCI_COREPLLCFG0_RANGE_MASK;
276 v >>= PRCI_COREPLLCFG0_RANGE_SHIFT;
279 c->flags &= (WRPLL_FLAGS_INT_FEEDBACK_MASK |
280 WRPLL_FLAGS_EXT_FEEDBACK_MASK);
282 if (r & PRCI_COREPLLCFG0_FSE_MASK)
283 c->flags |= WRPLL_FLAGS_INT_FEEDBACK_MASK;
285 c->flags |= WRPLL_FLAGS_EXT_FEEDBACK_MASK;
289 * __prci_wrpll_pack() - pack PLL configuration parameters into a register value
290 * @c: pointer to a struct analogbits_wrpll_cfg record containing the PLL's cfg
292 * Using a set of WRPLL configuration values pointed to by @c,
293 * assemble a PRCI PLL configuration register value, and return it to
296 * Context: Any context. Caller must ensure that the contents of the
297 * record pointed to by @c do not change during the execution
300 * Returns: a value suitable for writing into a PRCI PLL configuration
303 static u32 __prci_wrpll_pack(struct analogbits_wrpll_cfg *c)
307 r |= c->divr << PRCI_COREPLLCFG0_DIVR_SHIFT;
308 r |= c->divf << PRCI_COREPLLCFG0_DIVF_SHIFT;
309 r |= c->divq << PRCI_COREPLLCFG0_DIVQ_SHIFT;
310 r |= c->range << PRCI_COREPLLCFG0_RANGE_SHIFT;
311 if (c->flags & WRPLL_FLAGS_INT_FEEDBACK_MASK)
312 r |= PRCI_COREPLLCFG0_FSE_MASK;
318 * __prci_wrpll_read_cfg() - read the WRPLL configuration from the PRCI
320 * @pwd: PRCI WRPLL metadata
322 * Read the current configuration of the PLL identified by @pwd from
323 * the PRCI identified by @pd, and store it into the local configuration
326 * Context: Any context. Caller must prevent the records pointed to by
327 * @pd and @pwd from changing during execution.
329 static void __prci_wrpll_read_cfg(struct __prci_data *pd,
330 struct __prci_wrpll_data *pwd)
332 __prci_wrpll_unpack(&pwd->c, __prci_readl(pd, pwd->cfg0_offs));
336 * __prci_wrpll_write_cfg() - write WRPLL configuration into the PRCI
338 * @pwd: PRCI WRPLL metadata
339 * @c: WRPLL configuration record to write
341 * Write the WRPLL configuration described by @c into the WRPLL
342 * configuration register identified by @pwd in the PRCI instance
343 * described by @c. Make a cached copy of the WRPLL's current
344 * configuration so it can be used by other code.
346 * Context: Any context. Caller must prevent the records pointed to by
347 * @pd and @pwd from changing during execution.
349 static void __prci_wrpll_write_cfg(struct __prci_data *pd,
350 struct __prci_wrpll_data *pwd,
351 struct analogbits_wrpll_cfg *c)
353 __prci_writel(__prci_wrpll_pack(c), pwd->cfg0_offs, pd);
355 memcpy(&pwd->c, c, sizeof(struct analogbits_wrpll_cfg));
358 /* Core clock mux control */
361 * __prci_coreclksel_use_hfclk() - switch the CORECLK mux to output HFCLK
362 * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
364 * Switch the CORECLK mux to the HFCLK input source; return once complete.
366 * Context: Any context. Caller must prevent concurrent changes to the
367 * PRCI_CORECLKSEL_OFFSET register.
369 static void __prci_coreclksel_use_hfclk(struct __prci_data *pd)
373 r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);
374 r |= PRCI_CORECLKSEL_CORECLKSEL_MASK;
375 __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);
377 r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */
381 * __prci_coreclksel_use_corepll() - switch the CORECLK mux to output COREPLL
382 * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
384 * Switch the CORECLK mux to the PLL output clock; return once complete.
386 * Context: Any context. Caller must prevent concurrent changes to the
387 * PRCI_CORECLKSEL_OFFSET register.
389 static void __prci_coreclksel_use_corepll(struct __prci_data *pd)
393 r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);
394 r &= ~PRCI_CORECLKSEL_CORECLKSEL_MASK;
395 __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);
397 r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */
400 static unsigned long sifive_fu540_prci_wrpll_recalc_rate(
401 struct __prci_clock *pc,
402 unsigned long parent_rate)
404 struct __prci_wrpll_data *pwd = pc->pwd;
406 return analogbits_wrpll_calc_output_rate(&pwd->c, parent_rate);
409 static unsigned long sifive_fu540_prci_wrpll_round_rate(
410 struct __prci_clock *pc,
412 unsigned long *parent_rate)
414 struct __prci_wrpll_data *pwd = pc->pwd;
415 struct analogbits_wrpll_cfg c;
417 memcpy(&c, &pwd->c, sizeof(c));
419 analogbits_wrpll_configure_for_rate(&c, rate, *parent_rate);
421 return analogbits_wrpll_calc_output_rate(&c, *parent_rate);
424 static int sifive_fu540_prci_wrpll_set_rate(struct __prci_clock *pc,
426 unsigned long parent_rate)
428 struct __prci_wrpll_data *pwd = pc->pwd;
429 struct __prci_data *pd = pc->pd;
432 r = analogbits_wrpll_configure_for_rate(&pwd->c, rate, parent_rate);
439 __prci_wrpll_write_cfg(pd, pwd, &pwd->c);
441 udelay(analogbits_wrpll_calc_max_lock_us(&pwd->c));
449 static const struct __prci_clock_ops sifive_fu540_prci_wrpll_clk_ops = {
450 .set_rate = sifive_fu540_prci_wrpll_set_rate,
451 .round_rate = sifive_fu540_prci_wrpll_round_rate,
452 .recalc_rate = sifive_fu540_prci_wrpll_recalc_rate,
455 static const struct __prci_clock_ops sifive_fu540_prci_wrpll_ro_clk_ops = {
456 .recalc_rate = sifive_fu540_prci_wrpll_recalc_rate,
459 /* TLCLKSEL clock integration */
461 static unsigned long sifive_fu540_prci_tlclksel_recalc_rate(
462 struct __prci_clock *pc,
463 unsigned long parent_rate)
465 struct __prci_data *pd = pc->pd;
469 v = __prci_readl(pd, PRCI_CLKMUXSTATUSREG_OFFSET);
470 v &= PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK;
473 return div_u64(parent_rate, div);
476 static const struct __prci_clock_ops sifive_fu540_prci_tlclksel_clk_ops = {
477 .recalc_rate = sifive_fu540_prci_tlclksel_recalc_rate,
481 * PRCI integration data for each WRPLL instance
484 static struct __prci_wrpll_data __prci_corepll_data = {
485 .cfg0_offs = PRCI_COREPLLCFG0_OFFSET,
486 .bypass = __prci_coreclksel_use_hfclk,
487 .no_bypass = __prci_coreclksel_use_corepll,
490 static struct __prci_wrpll_data __prci_ddrpll_data = {
491 .cfg0_offs = PRCI_DDRPLLCFG0_OFFSET,
494 static struct __prci_wrpll_data __prci_gemgxlpll_data = {
495 .cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
499 * List of clock controls provided by the PRCI
502 static struct __prci_clock __prci_init_clocks[] = {
503 [PRCI_CLK_COREPLL] = {
505 .parent_name = "hfclk",
506 .ops = &sifive_fu540_prci_wrpll_clk_ops,
507 .pwd = &__prci_corepll_data,
509 [PRCI_CLK_DDRPLL] = {
511 .parent_name = "hfclk",
512 .ops = &sifive_fu540_prci_wrpll_ro_clk_ops,
513 .pwd = &__prci_ddrpll_data,
515 [PRCI_CLK_GEMGXLPLL] = {
517 .parent_name = "hfclk",
518 .ops = &sifive_fu540_prci_wrpll_clk_ops,
519 .pwd = &__prci_gemgxlpll_data,
523 .parent_name = "corepll",
524 .ops = &sifive_fu540_prci_tlclksel_clk_ops,
528 static ulong sifive_fu540_prci_get_rate(struct clk *clk)
530 struct __prci_clock *pc;
532 if (ARRAY_SIZE(__prci_init_clocks) <= clk->id)
535 pc = &__prci_init_clocks[clk->id];
536 if (!pc->pd || !pc->ops->recalc_rate)
539 return pc->ops->recalc_rate(pc, clk_get_rate(&pc->pd->parent));
542 static ulong sifive_fu540_prci_set_rate(struct clk *clk, ulong rate)
545 struct __prci_clock *pc;
547 if (ARRAY_SIZE(__prci_init_clocks) <= clk->id)
550 pc = &__prci_init_clocks[clk->id];
551 if (!pc->pd || !pc->ops->set_rate)
554 err = pc->ops->set_rate(pc, rate, clk_get_rate(&pc->pd->parent));
561 static int sifive_fu540_prci_probe(struct udevice *dev)
564 struct __prci_clock *pc;
565 struct __prci_data *pd = dev_get_priv(dev);
567 pd->base = (void *)dev_read_addr(dev);
568 if (IS_ERR(pd->base))
569 return PTR_ERR(pd->base);
571 err = clk_get_by_index(dev, 0, &pd->parent);
575 for (i = 0; i < ARRAY_SIZE(__prci_init_clocks); ++i) {
576 pc = &__prci_init_clocks[i];
579 __prci_wrpll_read_cfg(pd, pc->pwd);
585 static struct clk_ops sifive_fu540_prci_ops = {
586 .set_rate = sifive_fu540_prci_set_rate,
587 .get_rate = sifive_fu540_prci_get_rate,
590 static const struct udevice_id sifive_fu540_prci_ids[] = {
591 { .compatible = "sifive,fu540-c000-prci0" },
592 { .compatible = "sifive,aloeprci0" },
596 U_BOOT_DRIVER(sifive_fu540_prci) = {
597 .name = "sifive-fu540-prci",
599 .of_match = sifive_fu540_prci_ids,
600 .probe = sifive_fu540_prci_probe,
601 .ops = &sifive_fu540_prci_ops,
602 .priv_auto_alloc_size = sizeof(struct __prci_data),