drivers/clk/rockchip/clk_rk3399.c

   1 /*
   2  * (C) Copyright 2015 Google, Inc
   3  * (C) 2017 Theobroma Systems Design und Consulting GmbH
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0
   6  */
   7
   8 #include <common.h>
   9 #include <clk-uclass.h>
  10 #include <dm.h>
  11 #include <dt-structs.h>
  12 #include <errno.h>
  13 #include <mapmem.h>
  14 #include <syscon.h>
  15 #include <asm/io.h>
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/cru_rk3399.h>
  18 #include <asm/arch/hardware.h>
  19 #include <dm/lists.h>
  20 #include <dt-bindings/clock/rk3399-cru.h>
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 #if CONFIG_IS_ENABLED(OF_PLATDATA)
  25 struct rk3399_clk_plat {
  26         struct dtd_rockchip_rk3399_cru dtd;
  27 };
  28
  29 struct rk3399_pmuclk_plat {
  30         struct dtd_rockchip_rk3399_pmucru dtd;
  31 };
  32 #endif
  33
  34 struct pll_div {
  35         u32 refdiv;
  36         u32 fbdiv;
  37         u32 postdiv1;
  38         u32 postdiv2;
  39         u32 frac;
  40 };
  41
  42 #define RATE_TO_DIV(input_rate, output_rate) \
  43         ((input_rate) / (output_rate) - 1);
  44 #define DIV_TO_RATE(input_rate, div)    ((input_rate) / ((div) + 1))
  45
  46 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
  47         .refdiv = _refdiv,\
  48         .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
  49         .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
  50
  51 #if defined(CONFIG_SPL_BUILD)
  52 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
  53 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
  54 #else
  55 static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
  56 #endif
  57
  58 static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1);
  59 static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1);
  60
  61 static const struct pll_div *apll_l_cfgs[] = {
  62         [APLL_L_1600_MHZ] = &apll_l_1600_cfg,
  63         [APLL_L_600_MHZ] = &apll_l_600_cfg,
  64 };
  65
  66 enum {
  67         /* PLL_CON0 */
  68         PLL_FBDIV_MASK                  = 0xfff,
  69         PLL_FBDIV_SHIFT                 = 0,
  70
  71         /* PLL_CON1 */
  72         PLL_POSTDIV2_SHIFT              = 12,
  73         PLL_POSTDIV2_MASK               = 0x7 << PLL_POSTDIV2_SHIFT,
  74         PLL_POSTDIV1_SHIFT              = 8,
  75         PLL_POSTDIV1_MASK               = 0x7 << PLL_POSTDIV1_SHIFT,
  76         PLL_REFDIV_MASK                 = 0x3f,
  77         PLL_REFDIV_SHIFT                = 0,
  78
  79         /* PLL_CON2 */
  80         PLL_LOCK_STATUS_SHIFT           = 31,
  81         PLL_LOCK_STATUS_MASK            = 1 << PLL_LOCK_STATUS_SHIFT,
  82         PLL_FRACDIV_MASK                = 0xffffff,
  83         PLL_FRACDIV_SHIFT               = 0,
  84
  85         /* PLL_CON3 */
  86         PLL_MODE_SHIFT                  = 8,
  87         PLL_MODE_MASK                   = 3 << PLL_MODE_SHIFT,
  88         PLL_MODE_SLOW                   = 0,
  89         PLL_MODE_NORM,
  90         PLL_MODE_DEEP,
  91         PLL_DSMPD_SHIFT                 = 3,
  92         PLL_DSMPD_MASK                  = 1 << PLL_DSMPD_SHIFT,
  93         PLL_INTEGER_MODE                = 1,
  94
  95         /* PMUCRU_CLKSEL_CON0 */
  96         PMU_PCLK_DIV_CON_MASK           = 0x1f,
  97         PMU_PCLK_DIV_CON_SHIFT          = 0,
  98
  99         /* PMUCRU_CLKSEL_CON1 */
 100         SPI3_PLL_SEL_SHIFT              = 7,
 101         SPI3_PLL_SEL_MASK               = 1 << SPI3_PLL_SEL_SHIFT,
 102         SPI3_PLL_SEL_24M                = 0,
 103         SPI3_PLL_SEL_PPLL               = 1,
 104         SPI3_DIV_CON_SHIFT              = 0x0,
 105         SPI3_DIV_CON_MASK               = 0x7f,
 106
 107         /* PMUCRU_CLKSEL_CON2 */
 108         I2C_DIV_CON_MASK                = 0x7f,
 109         CLK_I2C8_DIV_CON_SHIFT          = 8,
 110         CLK_I2C0_DIV_CON_SHIFT          = 0,
 111
 112         /* PMUCRU_CLKSEL_CON3 */
 113         CLK_I2C4_DIV_CON_SHIFT          = 0,
 114
 115         /* CLKSEL_CON0 */
 116         ACLKM_CORE_L_DIV_CON_SHIFT      = 8,
 117         ACLKM_CORE_L_DIV_CON_MASK       = 0x1f << ACLKM_CORE_L_DIV_CON_SHIFT,
 118         CLK_CORE_L_PLL_SEL_SHIFT        = 6,
 119         CLK_CORE_L_PLL_SEL_MASK         = 3 << CLK_CORE_L_PLL_SEL_SHIFT,
 120         CLK_CORE_L_PLL_SEL_ALPLL        = 0x0,
 121         CLK_CORE_L_PLL_SEL_ABPLL        = 0x1,
 122         CLK_CORE_L_PLL_SEL_DPLL         = 0x10,
 123         CLK_CORE_L_PLL_SEL_GPLL         = 0x11,
 124         CLK_CORE_L_DIV_MASK             = 0x1f,
 125         CLK_CORE_L_DIV_SHIFT            = 0,
 126
 127         /* CLKSEL_CON1 */
 128         PCLK_DBG_L_DIV_SHIFT            = 0x8,
 129         PCLK_DBG_L_DIV_MASK             = 0x1f << PCLK_DBG_L_DIV_SHIFT,
 130         ATCLK_CORE_L_DIV_SHIFT          = 0,
 131         ATCLK_CORE_L_DIV_MASK           = 0x1f << ATCLK_CORE_L_DIV_SHIFT,
 132
 133         /* CLKSEL_CON14 */
 134         PCLK_PERIHP_DIV_CON_SHIFT       = 12,
 135         PCLK_PERIHP_DIV_CON_MASK        = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT,
 136         HCLK_PERIHP_DIV_CON_SHIFT       = 8,
 137         HCLK_PERIHP_DIV_CON_MASK        = 3 << HCLK_PERIHP_DIV_CON_SHIFT,
 138         ACLK_PERIHP_PLL_SEL_SHIFT       = 7,
 139         ACLK_PERIHP_PLL_SEL_MASK        = 1 << ACLK_PERIHP_PLL_SEL_SHIFT,
 140         ACLK_PERIHP_PLL_SEL_CPLL        = 0,
 141         ACLK_PERIHP_PLL_SEL_GPLL        = 1,
 142         ACLK_PERIHP_DIV_CON_SHIFT       = 0,
 143         ACLK_PERIHP_DIV_CON_MASK        = 0x1f,
 144
 145         /* CLKSEL_CON21 */
 146         ACLK_EMMC_PLL_SEL_SHIFT         = 7,
 147         ACLK_EMMC_PLL_SEL_MASK          = 0x1 << ACLK_EMMC_PLL_SEL_SHIFT,
 148         ACLK_EMMC_PLL_SEL_GPLL          = 0x1,
 149         ACLK_EMMC_DIV_CON_SHIFT         = 0,
 150         ACLK_EMMC_DIV_CON_MASK          = 0x1f,
 151
 152         /* CLKSEL_CON22 */
 153         CLK_EMMC_PLL_SHIFT              = 8,
 154         CLK_EMMC_PLL_MASK               = 0x7 << CLK_EMMC_PLL_SHIFT,
 155         CLK_EMMC_PLL_SEL_GPLL           = 0x1,
 156         CLK_EMMC_PLL_SEL_24M            = 0x5,
 157         CLK_EMMC_DIV_CON_SHIFT          = 0,
 158         CLK_EMMC_DIV_CON_MASK           = 0x7f << CLK_EMMC_DIV_CON_SHIFT,
 159
 160         /* CLKSEL_CON23 */
 161         PCLK_PERILP0_DIV_CON_SHIFT      = 12,
 162         PCLK_PERILP0_DIV_CON_MASK       = 0x7 << PCLK_PERILP0_DIV_CON_SHIFT,
 163         HCLK_PERILP0_DIV_CON_SHIFT      = 8,
 164         HCLK_PERILP0_DIV_CON_MASK       = 3 << HCLK_PERILP0_DIV_CON_SHIFT,
 165         ACLK_PERILP0_PLL_SEL_SHIFT      = 7,
 166         ACLK_PERILP0_PLL_SEL_MASK       = 1 << ACLK_PERILP0_PLL_SEL_SHIFT,
 167         ACLK_PERILP0_PLL_SEL_CPLL       = 0,
 168         ACLK_PERILP0_PLL_SEL_GPLL       = 1,
 169         ACLK_PERILP0_DIV_CON_SHIFT      = 0,
 170         ACLK_PERILP0_DIV_CON_MASK       = 0x1f,
 171
 172         /* CLKSEL_CON25 */
 173         PCLK_PERILP1_DIV_CON_SHIFT      = 8,
 174         PCLK_PERILP1_DIV_CON_MASK       = 0x7 << PCLK_PERILP1_DIV_CON_SHIFT,
 175         HCLK_PERILP1_PLL_SEL_SHIFT      = 7,
 176         HCLK_PERILP1_PLL_SEL_MASK       = 1 << HCLK_PERILP1_PLL_SEL_SHIFT,
 177         HCLK_PERILP1_PLL_SEL_CPLL       = 0,
 178         HCLK_PERILP1_PLL_SEL_GPLL       = 1,
 179         HCLK_PERILP1_DIV_CON_SHIFT      = 0,
 180         HCLK_PERILP1_DIV_CON_MASK       = 0x1f,
 181
 182         /* CLKSEL_CON26 */
 183         CLK_SARADC_DIV_CON_SHIFT        = 8,
 184         CLK_SARADC_DIV_CON_MASK         = 0xff << CLK_SARADC_DIV_CON_SHIFT,
 185
 186         /* CLKSEL_CON27 */
 187         CLK_TSADC_SEL_X24M              = 0x0,
 188         CLK_TSADC_SEL_SHIFT             = 15,
 189         CLK_TSADC_SEL_MASK              = 1 << CLK_TSADC_SEL_SHIFT,
 190         CLK_TSADC_DIV_CON_SHIFT         = 0,
 191         CLK_TSADC_DIV_CON_MASK          = 0x3ff,
 192
 193         /* CLKSEL_CON47 & CLKSEL_CON48 */
 194         ACLK_VOP_PLL_SEL_SHIFT          = 6,
 195         ACLK_VOP_PLL_SEL_MASK           = 0x3 << ACLK_VOP_PLL_SEL_SHIFT,
 196         ACLK_VOP_PLL_SEL_CPLL           = 0x1,
 197         ACLK_VOP_DIV_CON_SHIFT          = 0,
 198         ACLK_VOP_DIV_CON_MASK           = 0x1f << ACLK_VOP_DIV_CON_SHIFT,
 199
 200         /* CLKSEL_CON49 & CLKSEL_CON50 */
 201         DCLK_VOP_DCLK_SEL_SHIFT         = 11,
 202         DCLK_VOP_DCLK_SEL_MASK          = 1 << DCLK_VOP_DCLK_SEL_SHIFT,
 203         DCLK_VOP_DCLK_SEL_DIVOUT        = 0,
 204         DCLK_VOP_PLL_SEL_SHIFT          = 8,
 205         DCLK_VOP_PLL_SEL_MASK           = 3 << DCLK_VOP_PLL_SEL_SHIFT,
 206         DCLK_VOP_PLL_SEL_VPLL           = 0,
 207         DCLK_VOP_DIV_CON_MASK           = 0xff,
 208         DCLK_VOP_DIV_CON_SHIFT          = 0,
 209
 210         /* CLKSEL_CON58 */
 211         CLK_SPI_PLL_SEL_WIDTH = 1,
 212         CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1),
 213         CLK_SPI_PLL_SEL_CPLL = 0,
 214         CLK_SPI_PLL_SEL_GPLL = 1,
 215         CLK_SPI_PLL_DIV_CON_WIDTH = 7,
 216         CLK_SPI_PLL_DIV_CON_MASK = ((1 << CLK_SPI_PLL_DIV_CON_WIDTH) - 1),
 217
 218         CLK_SPI5_PLL_DIV_CON_SHIFT      = 8,
 219         CLK_SPI5_PLL_SEL_SHIFT          = 15,
 220
 221         /* CLKSEL_CON59 */
 222         CLK_SPI1_PLL_SEL_SHIFT          = 15,
 223         CLK_SPI1_PLL_DIV_CON_SHIFT      = 8,
 224         CLK_SPI0_PLL_SEL_SHIFT          = 7,
 225         CLK_SPI0_PLL_DIV_CON_SHIFT      = 0,
 226
 227         /* CLKSEL_CON60 */
 228         CLK_SPI4_PLL_SEL_SHIFT          = 15,
 229         CLK_SPI4_PLL_DIV_CON_SHIFT      = 8,
 230         CLK_SPI2_PLL_SEL_SHIFT          = 7,
 231         CLK_SPI2_PLL_DIV_CON_SHIFT      = 0,
 232
 233         /* CLKSEL_CON61 */
 234         CLK_I2C_PLL_SEL_MASK            = 1,
 235         CLK_I2C_PLL_SEL_CPLL            = 0,
 236         CLK_I2C_PLL_SEL_GPLL            = 1,
 237         CLK_I2C5_PLL_SEL_SHIFT          = 15,
 238         CLK_I2C5_DIV_CON_SHIFT          = 8,
 239         CLK_I2C1_PLL_SEL_SHIFT          = 7,
 240         CLK_I2C1_DIV_CON_SHIFT          = 0,
 241
 242         /* CLKSEL_CON62 */
 243         CLK_I2C6_PLL_SEL_SHIFT          = 15,
 244         CLK_I2C6_DIV_CON_SHIFT          = 8,
 245         CLK_I2C2_PLL_SEL_SHIFT          = 7,
 246         CLK_I2C2_DIV_CON_SHIFT          = 0,
 247
 248         /* CLKSEL_CON63 */
 249         CLK_I2C7_PLL_SEL_SHIFT          = 15,
 250         CLK_I2C7_DIV_CON_SHIFT          = 8,
 251         CLK_I2C3_PLL_SEL_SHIFT          = 7,
 252         CLK_I2C3_DIV_CON_SHIFT          = 0,
 253
 254         /* CRU_SOFTRST_CON4 */
 255         RESETN_DDR0_REQ_SHIFT           = 8,
 256         RESETN_DDR0_REQ_MASK            = 1 << RESETN_DDR0_REQ_SHIFT,
 257         RESETN_DDRPHY0_REQ_SHIFT        = 9,
 258         RESETN_DDRPHY0_REQ_MASK         = 1 << RESETN_DDRPHY0_REQ_SHIFT,
 259         RESETN_DDR1_REQ_SHIFT           = 12,
 260         RESETN_DDR1_REQ_MASK            = 1 << RESETN_DDR1_REQ_SHIFT,
 261         RESETN_DDRPHY1_REQ_SHIFT        = 13,
 262         RESETN_DDRPHY1_REQ_MASK         = 1 << RESETN_DDRPHY1_REQ_SHIFT,
 263 };
 264
 265 #define VCO_MAX_KHZ     (3200 * (MHz / KHz))
 266 #define VCO_MIN_KHZ     (800 * (MHz / KHz))
 267 #define OUTPUT_MAX_KHZ  (3200 * (MHz / KHz))
 268 #define OUTPUT_MIN_KHZ  (16 * (MHz / KHz))
 269
 270 /*
 271  *  the div restructions of pll in integer mode, these are defined in
 272  *  * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0
 273  */
 274 #define PLL_DIV_MIN     16
 275 #define PLL_DIV_MAX     3200
 276
 277 /*
 278  * How to calculate the PLL(from TRM V0.3 Part 1 Page 63):
 279  * Formulas also embedded within the Fractional PLL Verilog model:
 280  * If DSMPD = 1 (DSM is disabled, "integer mode")
 281  * FOUTVCO = FREF / REFDIV * FBDIV
 282  * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
 283  * Where:
 284  * FOUTVCO = Fractional PLL non-divided output frequency
 285  * FOUTPOSTDIV = Fractional PLL divided output frequency
 286  *               (output of second post divider)
 287  * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
 288  * REFDIV = Fractional PLL input reference clock divider
 289  * FBDIV = Integer value programmed into feedback divide
 290  *
 291  */
 292 static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div)
 293 {
 294         /* All 8 PLLs have same VCO and output frequency range restrictions. */
 295         u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv;
 296         u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2;
 297
 298         debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, "
 299                            "postdiv2=%d, vco=%u khz, output=%u khz\n",
 300                            pll_con, div->fbdiv, div->refdiv, div->postdiv1,
 301                            div->postdiv2, vco_khz, output_khz);
 302         assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ &&
 303                output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ &&
 304                div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX);
 305
 306         /*
 307          * When power on or changing PLL setting,
 308          * we must force PLL into slow mode to ensure output stable clock.
 309          */
 310         rk_clrsetreg(&pll_con[3], PLL_MODE_MASK,
 311                      PLL_MODE_SLOW << PLL_MODE_SHIFT);
 312
 313         /* use integer mode */
 314         rk_clrsetreg(&pll_con[3], PLL_DSMPD_MASK,
 315                      PLL_INTEGER_MODE << PLL_DSMPD_SHIFT);
 316
 317         rk_clrsetreg(&pll_con[0], PLL_FBDIV_MASK,
 318                      div->fbdiv << PLL_FBDIV_SHIFT);
 319         rk_clrsetreg(&pll_con[1],
 320                      PLL_POSTDIV2_MASK | PLL_POSTDIV1_MASK |
 321                      PLL_REFDIV_MASK | PLL_REFDIV_SHIFT,
 322                      (div->postdiv2 << PLL_POSTDIV2_SHIFT) |
 323                      (div->postdiv1 << PLL_POSTDIV1_SHIFT) |
 324                      (div->refdiv << PLL_REFDIV_SHIFT));
 325
 326         /* waiting for pll lock */
 327         while (!(readl(&pll_con[2]) & (1 << PLL_LOCK_STATUS_SHIFT)))
 328                 udelay(1);
 329
 330         /* pll enter normal mode */
 331         rk_clrsetreg(&pll_con[3], PLL_MODE_MASK,
 332                      PLL_MODE_NORM << PLL_MODE_SHIFT);
 333 }
 334
 335 static int pll_para_config(u32 freq_hz, struct pll_div *div)
 336 {
 337         u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0;
 338         u32 postdiv1, postdiv2 = 1;
 339         u32 fref_khz;
 340         u32 diff_khz, best_diff_khz;
 341         const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16;
 342         const u32 max_postdiv1 = 7, max_postdiv2 = 7;
 343         u32 vco_khz;
 344         u32 freq_khz = freq_hz / KHz;
 345
 346         if (!freq_hz) {
 347                 printf("%s: the frequency can't be 0 Hz\n", __func__);
 348                 return -1;
 349         }
 350
 351         postdiv1 = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
 352         if (postdiv1 > max_postdiv1) {
 353                 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1);
 354                 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2);
 355         }
 356
 357         vco_khz = freq_khz * postdiv1 * postdiv2;
 358
 359         if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ ||
 360             postdiv2 > max_postdiv2) {
 361                 printf("%s: Cannot find out a supported VCO"
 362                        " for Frequency (%uHz).\n", __func__, freq_hz);
 363                 return -1;
 364         }
 365
 366         div->postdiv1 = postdiv1;
 367         div->postdiv2 = postdiv2;
 368
 369         best_diff_khz = vco_khz;
 370         for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) {
 371                 fref_khz = ref_khz / refdiv;
 372
 373                 fbdiv = vco_khz / fref_khz;
 374                 if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv))
 375                         continue;
 376                 diff_khz = vco_khz - fbdiv * fref_khz;
 377                 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) {
 378                         fbdiv++;
 379                         diff_khz = fref_khz - diff_khz;
 380                 }
 381
 382                 if (diff_khz >= best_diff_khz)
 383                         continue;
 384
 385                 best_diff_khz = diff_khz;
 386                 div->refdiv = refdiv;
 387                 div->fbdiv = fbdiv;
 388         }
 389
 390         if (best_diff_khz > 4 * (MHz/KHz)) {
 391                 printf("%s: Failed to match output frequency %u, "
 392                        "difference is %u Hz,exceed 4MHZ\n", __func__, freq_hz,
 393                        best_diff_khz * KHz);
 394                 return -1;
 395         }
 396         return 0;
 397 }
 398
 399 #ifdef CONFIG_SPL_BUILD
 400 static void rkclk_init(struct rk3399_cru *cru)
 401 {
 402         u32 aclk_div;
 403         u32 hclk_div;
 404         u32 pclk_div;
 405
 406         /*
 407          * some cru registers changed by bootrom, we'd better reset them to
 408          * reset/default values described in TRM to avoid confusion in kernel.
 409          * Please consider these three lines as a fix of bootrom bug.
 410          */
 411         rk_clrsetreg(&cru->clksel_con[12], 0xffff, 0x4101);
 412         rk_clrsetreg(&cru->clksel_con[19], 0xffff, 0x033f);
 413         rk_clrsetreg(&cru->clksel_con[56], 0x0003, 0x0003);
 414
 415         /* configure gpll cpll */
 416         rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg);
 417         rkclk_set_pll(&cru->cpll_con[0], &cpll_init_cfg);
 418
 419         /* configure perihp aclk, hclk, pclk */
 420         aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1;
 421         assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
 422
 423         hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1;
 424         assert((hclk_div + 1) * PERIHP_HCLK_HZ ==
 425                PERIHP_ACLK_HZ && (hclk_div < 0x4));
 426
 427         pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1;
 428         assert((pclk_div + 1) * PERIHP_PCLK_HZ ==
 429                PERIHP_ACLK_HZ && (pclk_div < 0x7));
 430
 431         rk_clrsetreg(&cru->clksel_con[14],
 432                      PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK |
 433                      ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK,
 434                      pclk_div << PCLK_PERIHP_DIV_CON_SHIFT |
 435                      hclk_div << HCLK_PERIHP_DIV_CON_SHIFT |
 436                      ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT |
 437                      aclk_div << ACLK_PERIHP_DIV_CON_SHIFT);
 438
 439         /* configure perilp0 aclk, hclk, pclk */
 440         aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1;
 441         assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
 442
 443         hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1;
 444         assert((hclk_div + 1) * PERILP0_HCLK_HZ ==
 445                PERILP0_ACLK_HZ && (hclk_div < 0x4));
 446
 447         pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1;
 448         assert((pclk_div + 1) * PERILP0_PCLK_HZ ==
 449                PERILP0_ACLK_HZ && (pclk_div < 0x7));
 450
 451         rk_clrsetreg(&cru->clksel_con[23],
 452                      PCLK_PERILP0_DIV_CON_MASK | HCLK_PERILP0_DIV_CON_MASK |
 453                      ACLK_PERILP0_PLL_SEL_MASK | ACLK_PERILP0_DIV_CON_MASK,
 454                      pclk_div << PCLK_PERILP0_DIV_CON_SHIFT |
 455                      hclk_div << HCLK_PERILP0_DIV_CON_SHIFT |
 456                      ACLK_PERILP0_PLL_SEL_GPLL << ACLK_PERILP0_PLL_SEL_SHIFT |
 457                      aclk_div << ACLK_PERILP0_DIV_CON_SHIFT);
 458
 459         /* perilp1 hclk select gpll as source */
 460         hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1;
 461         assert((hclk_div + 1) * PERILP1_HCLK_HZ ==
 462                GPLL_HZ && (hclk_div < 0x1f));
 463
 464         pclk_div = PERILP1_HCLK_HZ / PERILP1_HCLK_HZ - 1;
 465         assert((pclk_div + 1) * PERILP1_HCLK_HZ ==
 466                PERILP1_HCLK_HZ && (hclk_div < 0x7));
 467
 468         rk_clrsetreg(&cru->clksel_con[25],
 469                      PCLK_PERILP1_DIV_CON_MASK | HCLK_PERILP1_DIV_CON_MASK |
 470                      HCLK_PERILP1_PLL_SEL_MASK,
 471                      pclk_div << PCLK_PERILP1_DIV_CON_SHIFT |
 472                      hclk_div << HCLK_PERILP1_DIV_CON_SHIFT |
 473                      HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT);
 474 }
 475 #endif
 476
 477 void rk3399_configure_cpu(struct rk3399_cru *cru,
 478                           enum apll_l_frequencies apll_l_freq)
 479 {
 480         u32 aclkm_div;
 481         u32 pclk_dbg_div;
 482         u32 atclk_div;
 483
 484         rkclk_set_pll(&cru->apll_l_con[0], apll_l_cfgs[apll_l_freq]);
 485
 486         aclkm_div = APLL_HZ / ACLKM_CORE_HZ - 1;
 487         assert((aclkm_div + 1) * ACLKM_CORE_HZ == APLL_HZ &&
 488                aclkm_div < 0x1f);
 489
 490         pclk_dbg_div = APLL_HZ / PCLK_DBG_HZ - 1;
 491         assert((pclk_dbg_div + 1) * PCLK_DBG_HZ == APLL_HZ &&
 492                pclk_dbg_div < 0x1f);
 493
 494         atclk_div = APLL_HZ / ATCLK_CORE_HZ - 1;
 495         assert((atclk_div + 1) * ATCLK_CORE_HZ == APLL_HZ &&
 496                atclk_div < 0x1f);
 497
 498         rk_clrsetreg(&cru->clksel_con[0],
 499                      ACLKM_CORE_L_DIV_CON_MASK | CLK_CORE_L_PLL_SEL_MASK |
 500                      CLK_CORE_L_DIV_MASK,
 501                      aclkm_div << ACLKM_CORE_L_DIV_CON_SHIFT |
 502                      CLK_CORE_L_PLL_SEL_ALPLL << CLK_CORE_L_PLL_SEL_SHIFT |
 503                      0 << CLK_CORE_L_DIV_SHIFT);
 504
 505         rk_clrsetreg(&cru->clksel_con[1],
 506                      PCLK_DBG_L_DIV_MASK | ATCLK_CORE_L_DIV_MASK,
 507                      pclk_dbg_div << PCLK_DBG_L_DIV_SHIFT |
 508                      atclk_div << ATCLK_CORE_L_DIV_SHIFT);
 509 }
 510 #define I2C_CLK_REG_MASK(bus) \
 511                         (I2C_DIV_CON_MASK << \
 512                         CLK_I2C ##bus## _DIV_CON_SHIFT | \
 513                         CLK_I2C_PLL_SEL_MASK << \
 514                         CLK_I2C ##bus## _PLL_SEL_SHIFT)
 515
 516 #define I2C_CLK_REG_VALUE(bus, clk_div) \
 517                               ((clk_div - 1) << \
 518                                         CLK_I2C ##bus## _DIV_CON_SHIFT | \
 519                               CLK_I2C_PLL_SEL_GPLL << \
 520                                         CLK_I2C ##bus## _PLL_SEL_SHIFT)
 521
 522 #define I2C_CLK_DIV_VALUE(con, bus) \
 523                         (con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & \
 524                                 I2C_DIV_CON_MASK;
 525
 526 #define I2C_PMUCLK_REG_MASK(bus) \
 527                         (I2C_DIV_CON_MASK << \
 528                          CLK_I2C ##bus## _DIV_CON_SHIFT)
 529
 530 #define I2C_PMUCLK_REG_VALUE(bus, clk_div) \
 531                                 ((clk_div - 1) << \
 532                                 CLK_I2C ##bus## _DIV_CON_SHIFT)
 533
 534 static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id)
 535 {
 536         u32 div, con;
 537
 538         switch (clk_id) {
 539         case SCLK_I2C1:
 540                 con = readl(&cru->clksel_con[61]);
 541                 div = I2C_CLK_DIV_VALUE(con, 1);
 542                 break;
 543         case SCLK_I2C2:
 544                 con = readl(&cru->clksel_con[62]);
 545                 div = I2C_CLK_DIV_VALUE(con, 2);
 546                 break;
 547         case SCLK_I2C3:
 548                 con = readl(&cru->clksel_con[63]);
 549                 div = I2C_CLK_DIV_VALUE(con, 3);
 550                 break;
 551         case SCLK_I2C5:
 552                 con = readl(&cru->clksel_con[61]);
 553                 div = I2C_CLK_DIV_VALUE(con, 5);
 554                 break;
 555         case SCLK_I2C6:
 556                 con = readl(&cru->clksel_con[62]);
 557                 div = I2C_CLK_DIV_VALUE(con, 6);
 558                 break;
 559         case SCLK_I2C7:
 560                 con = readl(&cru->clksel_con[63]);
 561                 div = I2C_CLK_DIV_VALUE(con, 7);
 562                 break;
 563         default:
 564                 printf("do not support this i2c bus\n");
 565                 return -EINVAL;
 566         }
 567
 568         return DIV_TO_RATE(GPLL_HZ, div);
 569 }
 570
 571 static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
 572 {
 573         int src_clk_div;
 574
 575         /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/
 576         src_clk_div = GPLL_HZ / hz;
 577         assert(src_clk_div - 1 < 127);
 578
 579         switch (clk_id) {
 580         case SCLK_I2C1:
 581                 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(1),
 582                              I2C_CLK_REG_VALUE(1, src_clk_div));
 583                 break;
 584         case SCLK_I2C2:
 585                 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(2),
 586                              I2C_CLK_REG_VALUE(2, src_clk_div));
 587                 break;
 588         case SCLK_I2C3:
 589                 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(3),
 590                              I2C_CLK_REG_VALUE(3, src_clk_div));
 591                 break;
 592         case SCLK_I2C5:
 593                 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(5),
 594                              I2C_CLK_REG_VALUE(5, src_clk_div));
 595                 break;
 596         case SCLK_I2C6:
 597                 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(6),
 598                              I2C_CLK_REG_VALUE(6, src_clk_div));
 599                 break;
 600         case SCLK_I2C7:
 601                 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(7),
 602                              I2C_CLK_REG_VALUE(7, src_clk_div));
 603                 break;
 604         default:
 605                 printf("do not support this i2c bus\n");
 606                 return -EINVAL;
 607         }
 608
 609         return rk3399_i2c_get_clk(cru, clk_id);
 610 }
 611
 612 /*
 613  * RK3399 SPI clocks have a common divider-width (7 bits) and a single bit
 614  * to select either CPLL or GPLL as the clock-parent. The location within
 615  * the enclosing CLKSEL_CON (i.e. div_shift and sel_shift) are variable.
 616  */
 617
 618 struct spi_clkreg {
 619         uint8_t reg;  /* CLKSEL_CON[reg] register in CRU */
 620         uint8_t div_shift;
 621         uint8_t sel_shift;
 622 };
 623
 624 /*
 625  * The entries are numbered relative to their offset from SCLK_SPI0.
 626  *
 627  * Note that SCLK_SPI3 (which is configured via PMUCRU and requires different
 628  * logic is not supported).
 629  */
 630 static const struct spi_clkreg spi_clkregs[] = {
 631         [0] = { .reg = 59,
 632                 .div_shift = CLK_SPI0_PLL_DIV_CON_SHIFT,
 633                 .sel_shift = CLK_SPI0_PLL_SEL_SHIFT, },
 634         [1] = { .reg = 59,
 635                 .div_shift = CLK_SPI1_PLL_DIV_CON_SHIFT,
 636                 .sel_shift = CLK_SPI1_PLL_SEL_SHIFT, },
 637         [2] = { .reg = 60,
 638                 .div_shift = CLK_SPI2_PLL_DIV_CON_SHIFT,
 639                 .sel_shift = CLK_SPI2_PLL_SEL_SHIFT, },
 640         [3] = { .reg = 60,
 641                 .div_shift = CLK_SPI4_PLL_DIV_CON_SHIFT,
 642                 .sel_shift = CLK_SPI4_PLL_SEL_SHIFT, },
 643         [4] = { .reg = 58,
 644                 .div_shift = CLK_SPI5_PLL_DIV_CON_SHIFT,
 645                 .sel_shift = CLK_SPI5_PLL_SEL_SHIFT, },
 646 };
 647
 648 static inline u32 extract_bits(u32 val, unsigned width, unsigned shift)
 649 {
 650         return (val >> shift) & ((1 << width) - 1);
 651 }
 652
 653 static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id)
 654 {
 655         const struct spi_clkreg *spiclk = NULL;
 656         u32 div, val;
 657
 658         switch (clk_id) {
 659         case SCLK_SPI0 ... SCLK_SPI5:
 660                 spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
 661                 break;
 662
 663         default:
 664                 error("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
 665                 return -EINVAL;
 666         }
 667
 668         val = readl(&cru->clksel_con[spiclk->reg]);
 669         div = extract_bits(val, CLK_SPI_PLL_DIV_CON_WIDTH, spiclk->div_shift);
 670
 671         return DIV_TO_RATE(GPLL_HZ, div);
 672 }
 673
 674 static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
 675 {
 676         const struct spi_clkreg *spiclk = NULL;
 677         int src_clk_div;
 678
 679         src_clk_div = RATE_TO_DIV(GPLL_HZ, hz);
 680         assert(src_clk_div < 127);
 681
 682         switch (clk_id) {
 683         case SCLK_SPI1 ... SCLK_SPI5:
 684                 spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
 685                 break;
 686
 687         default:
 688                 error("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
 689                 return -EINVAL;
 690         }
 691
 692         rk_clrsetreg(&cru->clksel_con[spiclk->reg],
 693                      ((CLK_SPI_PLL_DIV_CON_MASK << spiclk->div_shift) |
 694                        (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)),
 695                      ((src_clk_div << spiclk->div_shift) |
 696                       (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)));
 697
 698         return rk3399_spi_get_clk(cru, clk_id);
 699 }
 700
 701 static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz)
 702 {
 703         struct pll_div vpll_config = {0};
 704         int aclk_vop = 198*MHz;
 705         void *aclkreg_addr, *dclkreg_addr;
 706         u32 div;
 707
 708         switch (clk_id) {
 709         case DCLK_VOP0:
 710                 aclkreg_addr = &cru->clksel_con[47];
 711                 dclkreg_addr = &cru->clksel_con[49];
 712                 break;
 713         case DCLK_VOP1:
 714                 aclkreg_addr = &cru->clksel_con[48];
 715                 dclkreg_addr = &cru->clksel_con[50];
 716                 break;
 717         default:
 718                 return -EINVAL;
 719         }
 720         /* vop aclk source clk: cpll */
 721         div = CPLL_HZ / aclk_vop;
 722         assert(div - 1 < 32);
 723
 724         rk_clrsetreg(aclkreg_addr,
 725                      ACLK_VOP_PLL_SEL_MASK | ACLK_VOP_DIV_CON_MASK,
 726                      ACLK_VOP_PLL_SEL_CPLL << ACLK_VOP_PLL_SEL_SHIFT |
 727                      (div - 1) << ACLK_VOP_DIV_CON_SHIFT);
 728
 729         /* vop dclk source from vpll, and equals to vpll(means div == 1) */
 730         if (pll_para_config(hz, &vpll_config))
 731                 return -1;
 732
 733         rkclk_set_pll(&cru->vpll_con[0], &vpll_config);
 734
 735         rk_clrsetreg(dclkreg_addr,
 736                      DCLK_VOP_DCLK_SEL_MASK | DCLK_VOP_PLL_SEL_MASK|
 737                      DCLK_VOP_DIV_CON_MASK,
 738                      DCLK_VOP_DCLK_SEL_DIVOUT << DCLK_VOP_DCLK_SEL_SHIFT |
 739                      DCLK_VOP_PLL_SEL_VPLL << DCLK_VOP_PLL_SEL_SHIFT |
 740                      (1 - 1) << DCLK_VOP_DIV_CON_SHIFT);
 741
 742         return hz;
 743 }
 744
 745 static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id)
 746 {
 747         u32 div, con;
 748
 749         switch (clk_id) {
 750         case SCLK_SDMMC:
 751                 con = readl(&cru->clksel_con[16]);
 752                 break;
 753         case SCLK_EMMC:
 754                 con = readl(&cru->clksel_con[21]);
 755                 break;
 756         default:
 757                 return -EINVAL;
 758         }
 759         div = (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT;
 760
 761         if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT
 762                         == CLK_EMMC_PLL_SEL_24M)
 763                 return DIV_TO_RATE(24*1000*1000, div);
 764         else
 765                 return DIV_TO_RATE(GPLL_HZ, div);
 766 }
 767
 768 static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
 769                                 ulong clk_id, ulong set_rate)
 770 {
 771         int src_clk_div;
 772         int aclk_emmc = 198*MHz;
 773
 774         switch (clk_id) {
 775         case SCLK_SDMMC:
 776                 /* Select clk_sdmmc source from GPLL by default */
 777                 src_clk_div = GPLL_HZ / set_rate;
 778
 779                 if (src_clk_div > 127) {
 780                         /* use 24MHz source for 400KHz clock */
 781                         src_clk_div = 24*1000*1000 / set_rate;
 782                         rk_clrsetreg(&cru->clksel_con[16],
 783                                      CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
 784                                      CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |
 785                                      (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
 786                 } else {
 787                         rk_clrsetreg(&cru->clksel_con[16],
 788                                      CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
 789                                      CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
 790                                      (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
 791                 }
 792                 break;
 793         case SCLK_EMMC:
 794                 /* Select aclk_emmc source from GPLL */
 795                 src_clk_div = GPLL_HZ / aclk_emmc;
 796                 assert(src_clk_div - 1 < 31);
 797
 798                 rk_clrsetreg(&cru->clksel_con[21],
 799                              ACLK_EMMC_PLL_SEL_MASK | ACLK_EMMC_DIV_CON_MASK,
 800                              ACLK_EMMC_PLL_SEL_GPLL << ACLK_EMMC_PLL_SEL_SHIFT |
 801                              (src_clk_div - 1) << ACLK_EMMC_DIV_CON_SHIFT);
 802
 803                 /* Select clk_emmc source from GPLL too */
 804                 src_clk_div = GPLL_HZ / set_rate;
 805                 assert(src_clk_div - 1 < 127);
 806
 807                 rk_clrsetreg(&cru->clksel_con[22],
 808                              CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
 809                              CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
 810                              (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
 811                 break;
 812         default:
 813                 return -EINVAL;
 814         }
 815         return rk3399_mmc_get_clk(cru, clk_id);
 816 }
 817
 818 #define PMUSGRF_DDR_RGN_CON16 0xff330040
 819 static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
 820                                 ulong set_rate)
 821 {
 822         struct pll_div dpll_cfg;
 823
 824         /*  IC ECO bug, need to set this register */
 825         writel(0xc000c000, PMUSGRF_DDR_RGN_CON16);
 826
 827         /*  clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
 828         switch (set_rate) {
 829         case 200*MHz:
 830                 dpll_cfg = (struct pll_div)
 831                 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1};
 832                 break;
 833         case 300*MHz:
 834                 dpll_cfg = (struct pll_div)
 835                 {.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1};
 836                 break;
 837         case 666*MHz:
 838                 dpll_cfg = (struct pll_div)
 839                 {.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1};
 840                 break;
 841         case 800*MHz:
 842                 dpll_cfg = (struct pll_div)
 843                 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};
 844                 break;
 845         case 933*MHz:
 846                 dpll_cfg = (struct pll_div)
 847                 {.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1};
 848                 break;
 849         default:
 850                 error("Unsupported SDRAM frequency!,%ld\n", set_rate);
 851         }
 852         rkclk_set_pll(&cru->dpll_con[0], &dpll_cfg);
 853
 854         return set_rate;
 855 }
 856 static ulong rk3399_clk_get_rate(struct clk *clk)
 857 {
 858         struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
 859         ulong rate = 0;
 860
 861         switch (clk->id) {
 862         case 0 ... 63:
 863                 return 0;
 864         case SCLK_SDMMC:
 865         case SCLK_EMMC:
 866                 rate = rk3399_mmc_get_clk(priv->cru, clk->id);
 867                 break;
 868         case SCLK_I2C1:
 869         case SCLK_I2C2:
 870         case SCLK_I2C3:
 871         case SCLK_I2C5:
 872         case SCLK_I2C6:
 873         case SCLK_I2C7:
 874                 rate = rk3399_i2c_get_clk(priv->cru, clk->id);
 875                 break;
 876         case SCLK_SPI0...SCLK_SPI5:
 877                 rate = rk3399_spi_get_clk(priv->cru, clk->id);
 878                 break;
 879         case SCLK_UART0:
 880         case SCLK_UART2:
 881                 return 24000000;
 882         case DCLK_VOP0:
 883         case DCLK_VOP1:
 884                 break;
 885         default:
 886                 return -ENOENT;
 887         }
 888
 889         return rate;
 890 }
 891
 892 static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
 893 {
 894         struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
 895         ulong ret = 0;
 896
 897         switch (clk->id) {
 898         case 0 ... 63:
 899                 return 0;
 900         case SCLK_SDMMC:
 901         case SCLK_EMMC:
 902                 ret = rk3399_mmc_set_clk(priv->cru, clk->id, rate);
 903                 break;
 904         case SCLK_MAC:
 905                 /* nothing to do, as this is an external clock */
 906                 ret = rate;
 907                 break;
 908         case SCLK_I2C1:
 909         case SCLK_I2C2:
 910         case SCLK_I2C3:
 911         case SCLK_I2C5:
 912         case SCLK_I2C6:
 913         case SCLK_I2C7:
 914                 ret = rk3399_i2c_set_clk(priv->cru, clk->id, rate);
 915                 break;
 916         case SCLK_SPI0...SCLK_SPI5:
 917                 ret = rk3399_spi_set_clk(priv->cru, clk->id, rate);
 918                 break;
 919         case DCLK_VOP0:
 920         case DCLK_VOP1:
 921                 ret = rk3399_vop_set_clk(priv->cru, clk->id, rate);
 922                 break;
 923         case SCLK_DDRCLK:
 924                 ret = rk3399_ddr_set_clk(priv->cru, rate);
 925                 break;
 926         default:
 927                 return -ENOENT;
 928         }
 929
 930         return ret;
 931 }
 932
 933 static struct clk_ops rk3399_clk_ops = {
 934         .get_rate = rk3399_clk_get_rate,
 935         .set_rate = rk3399_clk_set_rate,
 936 };
 937
 938 static int rk3399_clk_probe(struct udevice *dev)
 939 {
 940 #ifdef CONFIG_SPL_BUILD
 941         struct rk3399_clk_priv *priv = dev_get_priv(dev);
 942
 943 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 944         struct rk3399_clk_plat *plat = dev_get_platdata(dev);
 945
 946         priv->cru = map_sysmem(plat->dtd.reg[1], plat->dtd.reg[3]);
 947 #endif
 948         rkclk_init(priv->cru);
 949 #endif
 950         return 0;
 951 }
 952
 953 static int rk3399_clk_ofdata_to_platdata(struct udevice *dev)
 954 {
 955 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 956         struct rk3399_clk_priv *priv = dev_get_priv(dev);
 957
 958         priv->cru = (struct rk3399_cru *)dev_get_addr(dev);
 959 #endif
 960         return 0;
 961 }
 962
 963 static int rk3399_clk_bind(struct udevice *dev)
 964 {
 965         int ret;
 966
 967         /* The reset driver does not have a device node, so bind it here */
 968         ret = device_bind_driver(gd->dm_root, "rk3399_sysreset", "reset", &dev);
 969         if (ret)
 970                 printf("Warning: No RK3399 reset driver: ret=%d\n", ret);
 971
 972         return 0;
 973 }
 974
 975 static const struct udevice_id rk3399_clk_ids[] = {
 976         { .compatible = "rockchip,rk3399-cru" },
 977         { }
 978 };
 979
 980 U_BOOT_DRIVER(clk_rk3399) = {
 981         .name           = "rockchip_rk3399_cru",
 982         .id             = UCLASS_CLK,
 983         .of_match       = rk3399_clk_ids,
 984         .priv_auto_alloc_size = sizeof(struct rk3399_clk_priv),
 985         .ofdata_to_platdata = rk3399_clk_ofdata_to_platdata,
 986         .ops            = &rk3399_clk_ops,
 987         .bind           = rk3399_clk_bind,
 988         .probe          = rk3399_clk_probe,
 989 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 990         .platdata_auto_alloc_size = sizeof(struct rk3399_clk_plat),
 991 #endif
 992 };
 993
 994 static ulong rk3399_i2c_get_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id)
 995 {
 996         u32 div, con;
 997
 998         switch (clk_id) {
 999         case SCLK_I2C0_PMU:
1000                 con = readl(&pmucru->pmucru_clksel[2]);
1001                 div = I2C_CLK_DIV_VALUE(con, 0);
1002                 break;
1003         case SCLK_I2C4_PMU:
1004                 con = readl(&pmucru->pmucru_clksel[3]);
1005                 div = I2C_CLK_DIV_VALUE(con, 4);
1006                 break;
1007         case SCLK_I2C8_PMU:
1008                 con = readl(&pmucru->pmucru_clksel[2]);
1009                 div = I2C_CLK_DIV_VALUE(con, 8);
1010                 break;
1011         default:
1012                 printf("do not support this i2c bus\n");
1013                 return -EINVAL;
1014         }
1015
1016         return DIV_TO_RATE(PPLL_HZ, div);
1017 }
1018
1019 static ulong rk3399_i2c_set_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id,
1020                                    uint hz)
1021 {
1022         int src_clk_div;
1023
1024         src_clk_div = PPLL_HZ / hz;
1025         assert(src_clk_div - 1 < 127);
1026
1027         switch (clk_id) {
1028         case SCLK_I2C0_PMU:
1029                 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(0),
1030                              I2C_PMUCLK_REG_VALUE(0, src_clk_div));
1031                 break;
1032         case SCLK_I2C4_PMU:
1033                 rk_clrsetreg(&pmucru->pmucru_clksel[3], I2C_PMUCLK_REG_MASK(4),
1034                              I2C_PMUCLK_REG_VALUE(4, src_clk_div));
1035                 break;
1036         case SCLK_I2C8_PMU:
1037                 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(8),
1038                              I2C_PMUCLK_REG_VALUE(8, src_clk_div));
1039                 break;
1040         default:
1041                 printf("do not support this i2c bus\n");
1042                 return -EINVAL;
1043         }
1044
1045         return DIV_TO_RATE(PPLL_HZ, src_clk_div);
1046 }
1047
1048 static ulong rk3399_pwm_get_clk(struct rk3399_pmucru *pmucru)
1049 {
1050         u32 div, con;
1051
1052         /* PWM closk rate is same as pclk_pmu */
1053         con = readl(&pmucru->pmucru_clksel[0]);
1054         div = con & PMU_PCLK_DIV_CON_MASK;
1055
1056         return DIV_TO_RATE(PPLL_HZ, div);
1057 }
1058
1059 static ulong rk3399_pmuclk_get_rate(struct clk *clk)
1060 {
1061         struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev);
1062         ulong rate = 0;
1063
1064         switch (clk->id) {
1065         case PCLK_RKPWM_PMU:
1066                 rate = rk3399_pwm_get_clk(priv->pmucru);
1067                 break;
1068         case SCLK_I2C0_PMU:
1069         case SCLK_I2C4_PMU:
1070         case SCLK_I2C8_PMU:
1071                 rate = rk3399_i2c_get_pmuclk(priv->pmucru, clk->id);
1072                 break;
1073         default:
1074                 return -ENOENT;
1075         }
1076
1077         return rate;
1078 }
1079
1080 static ulong rk3399_pmuclk_set_rate(struct clk *clk, ulong rate)
1081 {
1082         struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev);
1083         ulong ret = 0;
1084
1085         switch (clk->id) {
1086         case SCLK_I2C0_PMU:
1087         case SCLK_I2C4_PMU:
1088         case SCLK_I2C8_PMU:
1089                 ret = rk3399_i2c_set_pmuclk(priv->pmucru, clk->id, rate);
1090                 break;
1091         default:
1092                 return -ENOENT;
1093         }
1094
1095         return ret;
1096 }
1097
1098 static struct clk_ops rk3399_pmuclk_ops = {
1099         .get_rate = rk3399_pmuclk_get_rate,
1100         .set_rate = rk3399_pmuclk_set_rate,
1101 };
1102
1103 #ifndef CONFIG_SPL_BUILD
1104 static void pmuclk_init(struct rk3399_pmucru *pmucru)
1105 {
1106         u32 pclk_div;
1107
1108         /*  configure pmu pll(ppll) */
1109         rkclk_set_pll(&pmucru->ppll_con[0], &ppll_init_cfg);
1110
1111         /*  configure pmu pclk */
1112         pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1;
1113         rk_clrsetreg(&pmucru->pmucru_clksel[0],
1114                      PMU_PCLK_DIV_CON_MASK,
1115                      pclk_div << PMU_PCLK_DIV_CON_SHIFT);
1116 }
1117 #endif
1118
1119 static int rk3399_pmuclk_probe(struct udevice *dev)
1120 {
1121 #if CONFIG_IS_ENABLED(OF_PLATDATA) || !defined(CONFIG_SPL_BUILD)
1122         struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
1123 #endif
1124
1125 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1126         struct rk3399_pmuclk_plat *plat = dev_get_platdata(dev);
1127
1128         priv->pmucru = map_sysmem(plat->dtd.reg[1], plat->dtd.reg[3]);
1129 #endif
1130
1131 #ifndef CONFIG_SPL_BUILD
1132         pmuclk_init(priv->pmucru);
1133 #endif
1134         return 0;
1135 }
1136
1137 static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev)
1138 {
1139 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1140         struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
1141
1142         priv->pmucru = (struct rk3399_pmucru *)dev_get_addr(dev);
1143 #endif
1144         return 0;
1145 }
1146
1147 static const struct udevice_id rk3399_pmuclk_ids[] = {
1148         { .compatible = "rockchip,rk3399-pmucru" },
1149         { }
1150 };
1151
1152 U_BOOT_DRIVER(rockchip_rk3399_pmuclk) = {
1153         .name           = "rockchip_rk3399_pmucru",
1154         .id             = UCLASS_CLK,
1155         .of_match       = rk3399_pmuclk_ids,
1156         .priv_auto_alloc_size = sizeof(struct rk3399_pmuclk_priv),
1157         .ofdata_to_platdata = rk3399_pmuclk_ofdata_to_platdata,
1158         .ops            = &rk3399_pmuclk_ops,
1159         .probe          = rk3399_pmuclk_probe,
1160 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1161         .platdata_auto_alloc_size = sizeof(struct rk3399_pmuclk_plat),
1162 #endif
1163 };