drivers/clk/rockchip/clk_rk3328.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * (C) Copyright 2017 Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <common.h>
   7 #include <bitfield.h>
   8 #include <clk-uclass.h>
   9 #include <dm.h>
  10 #include <errno.h>
  11 #include <syscon.h>
  12 #include <asm/arch-rockchip/clock.h>
  13 #include <asm/arch-rockchip/cru_rk3328.h>
  14 #include <asm/arch-rockchip/hardware.h>
  15 #include <asm/arch-rockchip/grf_rk3328.h>
  16 #include <asm/io.h>
  17 #include <dm/lists.h>
  18 #include <dt-bindings/clock/rk3328-cru.h>
  19
  20 struct pll_div {
  21         u32 refdiv;
  22         u32 fbdiv;
  23         u32 postdiv1;
  24         u32 postdiv2;
  25         u32 frac;
  26 };
  27
  28 #define RATE_TO_DIV(input_rate, output_rate) \
  29         ((input_rate) / (output_rate) - 1);
  30 #define DIV_TO_RATE(input_rate, div)    ((input_rate) / ((div) + 1))
  31
  32 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
  33         .refdiv = _refdiv,\
  34         .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
  35         .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
  36
  37 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 4, 1);
  38 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 2, 2, 1);
  39
  40 static const struct pll_div apll_816_cfg = PLL_DIVISORS(816 * MHz, 1, 2, 1);
  41 static const struct pll_div apll_600_cfg = PLL_DIVISORS(600 * MHz, 1, 3, 1);
  42
  43 static const struct pll_div *apll_cfgs[] = {
  44         [APLL_816_MHZ] = &apll_816_cfg,
  45         [APLL_600_MHZ] = &apll_600_cfg,
  46 };
  47
  48 enum {
  49         /* PLL_CON0 */
  50         PLL_POSTDIV1_SHIFT              = 12,
  51         PLL_POSTDIV1_MASK               = 0x7 << PLL_POSTDIV1_SHIFT,
  52         PLL_FBDIV_SHIFT                 = 0,
  53         PLL_FBDIV_MASK                  = 0xfff,
  54
  55         /* PLL_CON1 */
  56         PLL_DSMPD_SHIFT                 = 12,
  57         PLL_DSMPD_MASK                  = 1 << PLL_DSMPD_SHIFT,
  58         PLL_INTEGER_MODE                = 1,
  59         PLL_LOCK_STATUS_SHIFT           = 10,
  60         PLL_LOCK_STATUS_MASK            = 1 << PLL_LOCK_STATUS_SHIFT,
  61         PLL_POSTDIV2_SHIFT              = 6,
  62         PLL_POSTDIV2_MASK               = 0x7 << PLL_POSTDIV2_SHIFT,
  63         PLL_REFDIV_SHIFT                = 0,
  64         PLL_REFDIV_MASK                 = 0x3f,
  65
  66         /* PLL_CON2 */
  67         PLL_FRACDIV_SHIFT               = 0,
  68         PLL_FRACDIV_MASK                = 0xffffff,
  69
  70         /* MODE_CON */
  71         APLL_MODE_SHIFT                 = 0,
  72         NPLL_MODE_SHIFT                 = 1,
  73         DPLL_MODE_SHIFT                 = 4,
  74         CPLL_MODE_SHIFT                 = 8,
  75         GPLL_MODE_SHIFT                 = 12,
  76         PLL_MODE_SLOW                   = 0,
  77         PLL_MODE_NORM,
  78
  79         /* CLKSEL_CON0 */
  80         CLK_CORE_PLL_SEL_APLL           = 0,
  81         CLK_CORE_PLL_SEL_GPLL,
  82         CLK_CORE_PLL_SEL_DPLL,
  83         CLK_CORE_PLL_SEL_NPLL,
  84         CLK_CORE_PLL_SEL_SHIFT          = 6,
  85         CLK_CORE_PLL_SEL_MASK           = 3 << CLK_CORE_PLL_SEL_SHIFT,
  86         CLK_CORE_DIV_SHIFT              = 0,
  87         CLK_CORE_DIV_MASK               = 0x1f,
  88
  89         /* CLKSEL_CON1 */
  90         ACLKM_CORE_DIV_SHIFT            = 4,
  91         ACLKM_CORE_DIV_MASK             = 0x7 << ACLKM_CORE_DIV_SHIFT,
  92         PCLK_DBG_DIV_SHIFT              = 0,
  93         PCLK_DBG_DIV_MASK               = 0xF << PCLK_DBG_DIV_SHIFT,
  94
  95         /* CLKSEL_CON27 */
  96         GMAC2IO_PLL_SEL_SHIFT           = 7,
  97         GMAC2IO_PLL_SEL_MASK            = 1 << GMAC2IO_PLL_SEL_SHIFT,
  98         GMAC2IO_PLL_SEL_CPLL            = 0,
  99         GMAC2IO_PLL_SEL_GPLL            = 1,
 100         GMAC2IO_CLK_DIV_MASK            = 0x1f,
 101         GMAC2IO_CLK_DIV_SHIFT           = 0,
 102
 103         /* CLKSEL_CON28 */
 104         ACLK_PERIHP_PLL_SEL_CPLL        = 0,
 105         ACLK_PERIHP_PLL_SEL_GPLL,
 106         ACLK_PERIHP_PLL_SEL_HDMIPHY,
 107         ACLK_PERIHP_PLL_SEL_SHIFT       = 6,
 108         ACLK_PERIHP_PLL_SEL_MASK        = 3 << ACLK_PERIHP_PLL_SEL_SHIFT,
 109         ACLK_PERIHP_DIV_CON_SHIFT       = 0,
 110         ACLK_PERIHP_DIV_CON_MASK        = 0x1f,
 111
 112         /* CLKSEL_CON29 */
 113         PCLK_PERIHP_DIV_CON_SHIFT       = 4,
 114         PCLK_PERIHP_DIV_CON_MASK        = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT,
 115         HCLK_PERIHP_DIV_CON_SHIFT       = 0,
 116         HCLK_PERIHP_DIV_CON_MASK        = 3 << HCLK_PERIHP_DIV_CON_SHIFT,
 117
 118         /* CLKSEL_CON22 */
 119         CLK_TSADC_DIV_CON_SHIFT         = 0,
 120         CLK_TSADC_DIV_CON_MASK          = 0x3ff,
 121
 122         /* CLKSEL_CON23 */
 123         CLK_SARADC_DIV_CON_SHIFT        = 0,
 124         CLK_SARADC_DIV_CON_MASK         = GENMASK(9, 0),
 125         CLK_SARADC_DIV_CON_WIDTH        = 10,
 126
 127         /* CLKSEL_CON24 */
 128         CLK_PWM_PLL_SEL_CPLL            = 0,
 129         CLK_PWM_PLL_SEL_GPLL,
 130         CLK_PWM_PLL_SEL_SHIFT           = 15,
 131         CLK_PWM_PLL_SEL_MASK            = 1 << CLK_PWM_PLL_SEL_SHIFT,
 132         CLK_PWM_DIV_CON_SHIFT           = 8,
 133         CLK_PWM_DIV_CON_MASK            = 0x7f << CLK_PWM_DIV_CON_SHIFT,
 134
 135         CLK_SPI_PLL_SEL_CPLL            = 0,
 136         CLK_SPI_PLL_SEL_GPLL,
 137         CLK_SPI_PLL_SEL_SHIFT           = 7,
 138         CLK_SPI_PLL_SEL_MASK            = 1 << CLK_SPI_PLL_SEL_SHIFT,
 139         CLK_SPI_DIV_CON_SHIFT           = 0,
 140         CLK_SPI_DIV_CON_MASK            = 0x7f << CLK_SPI_DIV_CON_SHIFT,
 141
 142         /* CLKSEL_CON30 */
 143         CLK_SDMMC_PLL_SEL_CPLL          = 0,
 144         CLK_SDMMC_PLL_SEL_GPLL,
 145         CLK_SDMMC_PLL_SEL_24M,
 146         CLK_SDMMC_PLL_SEL_USBPHY,
 147         CLK_SDMMC_PLL_SHIFT             = 8,
 148         CLK_SDMMC_PLL_MASK              = 0x3 << CLK_SDMMC_PLL_SHIFT,
 149         CLK_SDMMC_DIV_CON_SHIFT          = 0,
 150         CLK_SDMMC_DIV_CON_MASK           = 0xff << CLK_SDMMC_DIV_CON_SHIFT,
 151
 152         /* CLKSEL_CON32 */
 153         CLK_EMMC_PLL_SEL_CPLL           = 0,
 154         CLK_EMMC_PLL_SEL_GPLL,
 155         CLK_EMMC_PLL_SEL_24M,
 156         CLK_EMMC_PLL_SEL_USBPHY,
 157         CLK_EMMC_PLL_SHIFT              = 8,
 158         CLK_EMMC_PLL_MASK               = 0x3 << CLK_EMMC_PLL_SHIFT,
 159         CLK_EMMC_DIV_CON_SHIFT          = 0,
 160         CLK_EMMC_DIV_CON_MASK           = 0xff << CLK_EMMC_DIV_CON_SHIFT,
 161
 162         /* CLKSEL_CON34 */
 163         CLK_I2C_PLL_SEL_CPLL            = 0,
 164         CLK_I2C_PLL_SEL_GPLL,
 165         CLK_I2C_DIV_CON_MASK            = 0x7f,
 166         CLK_I2C_PLL_SEL_MASK            = 1,
 167         CLK_I2C1_PLL_SEL_SHIFT          = 15,
 168         CLK_I2C1_DIV_CON_SHIFT          = 8,
 169         CLK_I2C0_PLL_SEL_SHIFT          = 7,
 170         CLK_I2C0_DIV_CON_SHIFT          = 0,
 171
 172         /* CLKSEL_CON35 */
 173         CLK_I2C3_PLL_SEL_SHIFT          = 15,
 174         CLK_I2C3_DIV_CON_SHIFT          = 8,
 175         CLK_I2C2_PLL_SEL_SHIFT          = 7,
 176         CLK_I2C2_DIV_CON_SHIFT          = 0,
 177 };
 178
 179 #define VCO_MAX_KHZ     (3200 * (MHz / KHz))
 180 #define VCO_MIN_KHZ     (800 * (MHz / KHz))
 181 #define OUTPUT_MAX_KHZ  (3200 * (MHz / KHz))
 182 #define OUTPUT_MIN_KHZ  (16 * (MHz / KHz))
 183
 184 /*
 185  *  the div restructions of pll in integer mode, these are defined in
 186  *  * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0
 187  */
 188 #define PLL_DIV_MIN     16
 189 #define PLL_DIV_MAX     3200
 190
 191 /*
 192  * How to calculate the PLL(from TRM V0.3 Part 1 Page 63):
 193  * Formulas also embedded within the Fractional PLL Verilog model:
 194  * If DSMPD = 1 (DSM is disabled, "integer mode")
 195  * FOUTVCO = FREF / REFDIV * FBDIV
 196  * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
 197  * Where:
 198  * FOUTVCO = Fractional PLL non-divided output frequency
 199  * FOUTPOSTDIV = Fractional PLL divided output frequency
 200  *               (output of second post divider)
 201  * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
 202  * REFDIV = Fractional PLL input reference clock divider
 203  * FBDIV = Integer value programmed into feedback divide
 204  *
 205  */
 206 static void rkclk_set_pll(struct rk3328_cru *cru, enum rk_clk_id clk_id,
 207                         const struct pll_div *div)
 208 {
 209         u32 *pll_con;
 210         u32 mode_shift, mode_mask;
 211
 212         pll_con = NULL;
 213         mode_shift = 0;
 214         switch (clk_id) {
 215         case CLK_ARM:
 216                 pll_con = cru->apll_con;
 217                 mode_shift = APLL_MODE_SHIFT;
 218                 break;
 219         case CLK_DDR:
 220                 pll_con = cru->dpll_con;
 221                 mode_shift = DPLL_MODE_SHIFT;
 222                 break;
 223         case CLK_CODEC:
 224                 pll_con = cru->cpll_con;
 225                 mode_shift = CPLL_MODE_SHIFT;
 226                 break;
 227         case CLK_GENERAL:
 228                 pll_con = cru->gpll_con;
 229                 mode_shift = GPLL_MODE_SHIFT;
 230                 break;
 231         case CLK_NEW:
 232                 pll_con = cru->npll_con;
 233                 mode_shift = NPLL_MODE_SHIFT;
 234                 break;
 235         default:
 236                 break;
 237         }
 238         mode_mask = 1 << mode_shift;
 239
 240         /* All 8 PLLs have same VCO and output frequency range restrictions. */
 241         u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv;
 242         u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2;
 243
 244         debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, \
 245               postdiv2=%d, vco=%u khz, output=%u khz\n",
 246               pll_con, div->fbdiv, div->refdiv, div->postdiv1,
 247               div->postdiv2, vco_khz, output_khz);
 248         assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ &&
 249                output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ &&
 250                div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX);
 251
 252         /*
 253          * When power on or changing PLL setting,
 254          * we must force PLL into slow mode to ensure output stable clock.
 255          */
 256         rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_SLOW << mode_shift);
 257
 258         /* use integer mode */
 259         rk_clrsetreg(&pll_con[1], PLL_DSMPD_MASK,
 260                      PLL_INTEGER_MODE << PLL_DSMPD_SHIFT);
 261
 262         rk_clrsetreg(&pll_con[0],
 263                      PLL_FBDIV_MASK | PLL_POSTDIV1_MASK,
 264                      (div->fbdiv << PLL_FBDIV_SHIFT) |
 265                      (div->postdiv1 << PLL_POSTDIV1_SHIFT));
 266         rk_clrsetreg(&pll_con[1],
 267                      PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
 268                      (div->postdiv2 << PLL_POSTDIV2_SHIFT) |
 269                      (div->refdiv << PLL_REFDIV_SHIFT));
 270
 271         /* waiting for pll lock */
 272         while (!(readl(&pll_con[1]) & (1 << PLL_LOCK_STATUS_SHIFT)))
 273                 udelay(1);
 274
 275         /* pll enter normal mode */
 276         rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_NORM << mode_shift);
 277 }
 278
 279 static void rkclk_init(struct rk3328_cru *cru)
 280 {
 281         u32 aclk_div;
 282         u32 hclk_div;
 283         u32 pclk_div;
 284
 285         rk3328_configure_cpu(cru, APLL_600_MHZ);
 286
 287         /* configure gpll cpll */
 288         rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
 289         rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
 290
 291         /* configure perihp aclk, hclk, pclk */
 292         aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1;
 293         hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1;
 294         pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1;
 295
 296         rk_clrsetreg(&cru->clksel_con[28],
 297                      ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK,
 298                      ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT |
 299                      aclk_div << ACLK_PERIHP_DIV_CON_SHIFT);
 300         rk_clrsetreg(&cru->clksel_con[29],
 301                      PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK,
 302                      pclk_div << PCLK_PERIHP_DIV_CON_SHIFT |
 303                      hclk_div << HCLK_PERIHP_DIV_CON_SHIFT);
 304 }
 305
 306 void rk3328_configure_cpu(struct rk3328_cru *cru,
 307                           enum apll_frequencies apll_freq)
 308 {
 309         u32 clk_core_div;
 310         u32 aclkm_div;
 311         u32 pclk_dbg_div;
 312
 313         rkclk_set_pll(cru, CLK_ARM, apll_cfgs[apll_freq]);
 314
 315         clk_core_div = APLL_HZ / CLK_CORE_HZ - 1;
 316         aclkm_div = APLL_HZ / ACLKM_CORE_HZ / (clk_core_div + 1) - 1;
 317         pclk_dbg_div = APLL_HZ / PCLK_DBG_HZ / (clk_core_div + 1) - 1;
 318
 319         rk_clrsetreg(&cru->clksel_con[0],
 320                      CLK_CORE_PLL_SEL_MASK | CLK_CORE_DIV_MASK,
 321                      CLK_CORE_PLL_SEL_APLL << CLK_CORE_PLL_SEL_SHIFT |
 322                      clk_core_div << CLK_CORE_DIV_SHIFT);
 323
 324         rk_clrsetreg(&cru->clksel_con[1],
 325                      PCLK_DBG_DIV_MASK | ACLKM_CORE_DIV_MASK,
 326                      pclk_dbg_div << PCLK_DBG_DIV_SHIFT |
 327                      aclkm_div << ACLKM_CORE_DIV_SHIFT);
 328 }
 329
 330
 331 static ulong rk3328_i2c_get_clk(struct rk3328_cru *cru, ulong clk_id)
 332 {
 333         u32 div, con;
 334
 335         switch (clk_id) {
 336         case SCLK_I2C0:
 337                 con = readl(&cru->clksel_con[34]);
 338                 div = con >> CLK_I2C0_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
 339                 break;
 340         case SCLK_I2C1:
 341                 con = readl(&cru->clksel_con[34]);
 342                 div = con >> CLK_I2C1_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
 343                 break;
 344         case SCLK_I2C2:
 345                 con = readl(&cru->clksel_con[35]);
 346                 div = con >> CLK_I2C2_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
 347                 break;
 348         case SCLK_I2C3:
 349                 con = readl(&cru->clksel_con[35]);
 350                 div = con >> CLK_I2C3_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
 351                 break;
 352         default:
 353                 printf("do not support this i2c bus\n");
 354                 return -EINVAL;
 355         }
 356
 357         return DIV_TO_RATE(GPLL_HZ, div);
 358 }
 359
 360 static ulong rk3328_i2c_set_clk(struct rk3328_cru *cru, ulong clk_id, uint hz)
 361 {
 362         int src_clk_div;
 363
 364         src_clk_div = GPLL_HZ / hz;
 365         assert(src_clk_div - 1 < 127);
 366
 367         switch (clk_id) {
 368         case SCLK_I2C0:
 369                 rk_clrsetreg(&cru->clksel_con[34],
 370                              CLK_I2C_DIV_CON_MASK << CLK_I2C0_DIV_CON_SHIFT |
 371                              CLK_I2C_PLL_SEL_MASK << CLK_I2C0_PLL_SEL_SHIFT,
 372                              (src_clk_div - 1) << CLK_I2C0_DIV_CON_SHIFT |
 373                              CLK_I2C_PLL_SEL_GPLL << CLK_I2C0_PLL_SEL_SHIFT);
 374                 break;
 375         case SCLK_I2C1:
 376                 rk_clrsetreg(&cru->clksel_con[34],
 377                              CLK_I2C_DIV_CON_MASK << CLK_I2C1_DIV_CON_SHIFT |
 378                              CLK_I2C_PLL_SEL_MASK << CLK_I2C1_PLL_SEL_SHIFT,
 379                              (src_clk_div - 1) << CLK_I2C1_DIV_CON_SHIFT |
 380                              CLK_I2C_PLL_SEL_GPLL << CLK_I2C1_PLL_SEL_SHIFT);
 381                 break;
 382         case SCLK_I2C2:
 383                 rk_clrsetreg(&cru->clksel_con[35],
 384                              CLK_I2C_DIV_CON_MASK << CLK_I2C2_DIV_CON_SHIFT |
 385                              CLK_I2C_PLL_SEL_MASK << CLK_I2C2_PLL_SEL_SHIFT,
 386                              (src_clk_div - 1) << CLK_I2C2_DIV_CON_SHIFT |
 387                              CLK_I2C_PLL_SEL_GPLL << CLK_I2C2_PLL_SEL_SHIFT);
 388                 break;
 389         case SCLK_I2C3:
 390                 rk_clrsetreg(&cru->clksel_con[35],
 391                              CLK_I2C_DIV_CON_MASK << CLK_I2C3_DIV_CON_SHIFT |
 392                              CLK_I2C_PLL_SEL_MASK << CLK_I2C3_PLL_SEL_SHIFT,
 393                              (src_clk_div - 1) << CLK_I2C3_DIV_CON_SHIFT |
 394                              CLK_I2C_PLL_SEL_GPLL << CLK_I2C3_PLL_SEL_SHIFT);
 395                 break;
 396         default:
 397                 printf("do not support this i2c bus\n");
 398                 return -EINVAL;
 399         }
 400
 401         return DIV_TO_RATE(GPLL_HZ, src_clk_div);
 402 }
 403
 404 static ulong rk3328_gmac2io_set_clk(struct rk3328_cru *cru, ulong rate)
 405 {
 406         struct rk3328_grf_regs *grf;
 407         ulong ret;
 408
 409         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 410
 411         /*
 412          * The RGMII CLK can be derived either from an external "clkin"
 413          * or can be generated from internally by a divider from SCLK_MAC.
 414          */
 415         if (readl(&grf->mac_con[1]) & BIT(10) &&
 416             readl(&grf->soc_con[4]) & BIT(14)) {
 417                 /* An external clock will always generate the right rate... */
 418                 ret = rate;
 419         } else {
 420                 u32 con = readl(&cru->clksel_con[27]);
 421                 ulong pll_rate;
 422                 u8 div;
 423
 424                 if ((con >> GMAC2IO_PLL_SEL_SHIFT) & GMAC2IO_PLL_SEL_GPLL)
 425                         pll_rate = GPLL_HZ;
 426                 else
 427                         pll_rate = CPLL_HZ;
 428
 429                 div = DIV_ROUND_UP(pll_rate, rate) - 1;
 430                 if (div <= 0x1f)
 431                         rk_clrsetreg(&cru->clksel_con[27], GMAC2IO_CLK_DIV_MASK,
 432                                      div << GMAC2IO_CLK_DIV_SHIFT);
 433                 else
 434                         debug("Unsupported div for gmac:%d\n", div);
 435
 436                 return DIV_TO_RATE(pll_rate, div);
 437         }
 438
 439         return ret;
 440 }
 441
 442 static ulong rk3328_mmc_get_clk(struct rk3328_cru *cru, uint clk_id)
 443 {
 444         u32 div, con, con_id;
 445
 446         switch (clk_id) {
 447         case HCLK_SDMMC:
 448         case SCLK_SDMMC:
 449                 con_id = 30;
 450                 break;
 451         case HCLK_EMMC:
 452         case SCLK_EMMC:
 453                 con_id = 32;
 454                 break;
 455         default:
 456                 return -EINVAL;
 457         }
 458         con = readl(&cru->clksel_con[con_id]);
 459         div = (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT;
 460
 461         if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT
 462             == CLK_EMMC_PLL_SEL_24M)
 463                 return DIV_TO_RATE(OSC_HZ, div) / 2;
 464         else
 465                 return DIV_TO_RATE(GPLL_HZ, div) / 2;
 466 }
 467
 468 static ulong rk3328_mmc_set_clk(struct rk3328_cru *cru,
 469                                 ulong clk_id, ulong set_rate)
 470 {
 471         int src_clk_div;
 472         u32 con_id;
 473
 474         switch (clk_id) {
 475         case HCLK_SDMMC:
 476         case SCLK_SDMMC:
 477                 con_id = 30;
 478                 break;
 479         case HCLK_EMMC:
 480         case SCLK_EMMC:
 481                 con_id = 32;
 482                 break;
 483         default:
 484                 return -EINVAL;
 485         }
 486         /* Select clk_sdmmc/emmc source from GPLL by default */
 487         /* mmc clock defaulg div 2 internal, need provide double in cru */
 488         src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate);
 489
 490         if (src_clk_div > 127) {
 491                 /* use 24MHz source for 400KHz clock */
 492                 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate);
 493                 rk_clrsetreg(&cru->clksel_con[con_id],
 494                              CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
 495                              CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |
 496                              (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
 497         } else {
 498                 rk_clrsetreg(&cru->clksel_con[con_id],
 499                              CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
 500                              CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
 501                              (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
 502         }
 503
 504         return rk3328_mmc_get_clk(cru, clk_id);
 505 }
 506
 507 static ulong rk3328_pwm_get_clk(struct rk3328_cru *cru)
 508 {
 509         u32 div, con;
 510
 511         con = readl(&cru->clksel_con[24]);
 512         div = (con & CLK_PWM_DIV_CON_MASK) >> CLK_PWM_DIV_CON_SHIFT;
 513
 514         return DIV_TO_RATE(GPLL_HZ, div);
 515 }
 516
 517 static ulong rk3328_pwm_set_clk(struct rk3328_cru *cru, uint hz)
 518 {
 519         u32 div = GPLL_HZ / hz;
 520
 521         rk_clrsetreg(&cru->clksel_con[24],
 522                      CLK_PWM_PLL_SEL_MASK | CLK_PWM_DIV_CON_MASK,
 523                      CLK_PWM_PLL_SEL_GPLL << CLK_PWM_PLL_SEL_SHIFT |
 524                      (div - 1) << CLK_PWM_DIV_CON_SHIFT);
 525
 526         return DIV_TO_RATE(GPLL_HZ, div);
 527 }
 528
 529 static ulong rk3328_saradc_get_clk(struct rk3328_cru *cru)
 530 {
 531         u32 div, val;
 532
 533         val = readl(&cru->clksel_con[23]);
 534         div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
 535                                CLK_SARADC_DIV_CON_WIDTH);
 536
 537         return DIV_TO_RATE(OSC_HZ, div);
 538 }
 539
 540 static ulong rk3328_saradc_set_clk(struct rk3328_cru *cru, uint hz)
 541 {
 542         int src_clk_div;
 543
 544         src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
 545         assert(src_clk_div < 128);
 546
 547         rk_clrsetreg(&cru->clksel_con[23],
 548                      CLK_SARADC_DIV_CON_MASK,
 549                      src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
 550
 551         return rk3328_saradc_get_clk(cru);
 552 }
 553
 554 static ulong rk3328_clk_get_rate(struct clk *clk)
 555 {
 556         struct rk3328_clk_priv *priv = dev_get_priv(clk->dev);
 557         ulong rate = 0;
 558
 559         switch (clk->id) {
 560         case 0 ... 29:
 561                 return 0;
 562         case HCLK_SDMMC:
 563         case HCLK_EMMC:
 564         case SCLK_SDMMC:
 565         case SCLK_EMMC:
 566                 rate = rk3328_mmc_get_clk(priv->cru, clk->id);
 567                 break;
 568         case SCLK_I2C0:
 569         case SCLK_I2C1:
 570         case SCLK_I2C2:
 571         case SCLK_I2C3:
 572                 rate = rk3328_i2c_get_clk(priv->cru, clk->id);
 573                 break;
 574         case SCLK_PWM:
 575                 rate = rk3328_pwm_get_clk(priv->cru);
 576                 break;
 577         case SCLK_SARADC:
 578                 rate = rk3328_saradc_get_clk(priv->cru);
 579                 break;
 580         default:
 581                 return -ENOENT;
 582         }
 583
 584         return rate;
 585 }
 586
 587 static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate)
 588 {
 589         struct rk3328_clk_priv *priv = dev_get_priv(clk->dev);
 590         ulong ret = 0;
 591
 592         switch (clk->id) {
 593         case 0 ... 29:
 594                 return 0;
 595         case HCLK_SDMMC:
 596         case HCLK_EMMC:
 597         case SCLK_SDMMC:
 598         case SCLK_EMMC:
 599                 ret = rk3328_mmc_set_clk(priv->cru, clk->id, rate);
 600                 break;
 601         case SCLK_I2C0:
 602         case SCLK_I2C1:
 603         case SCLK_I2C2:
 604         case SCLK_I2C3:
 605                 ret = rk3328_i2c_set_clk(priv->cru, clk->id, rate);
 606                 break;
 607         case SCLK_MAC2IO:
 608                 ret = rk3328_gmac2io_set_clk(priv->cru, rate);
 609                 break;
 610         case SCLK_PWM:
 611                 ret = rk3328_pwm_set_clk(priv->cru, rate);
 612                 break;
 613         case SCLK_SARADC:
 614                 ret = rk3328_saradc_set_clk(priv->cru, rate);
 615                 break;
 616         case DCLK_LCDC:
 617         case SCLK_PDM:
 618         case SCLK_RTC32K:
 619         case SCLK_UART0:
 620         case SCLK_UART1:
 621         case SCLK_UART2:
 622         case SCLK_SDIO:
 623         case SCLK_TSP:
 624         case SCLK_WIFI:
 625         case ACLK_BUS_PRE:
 626         case HCLK_BUS_PRE:
 627         case PCLK_BUS_PRE:
 628         case ACLK_PERI_PRE:
 629         case HCLK_PERI:
 630         case PCLK_PERI:
 631         case ACLK_VIO_PRE:
 632         case HCLK_VIO_PRE:
 633         case ACLK_RGA_PRE:
 634         case SCLK_RGA:
 635         case ACLK_VOP_PRE:
 636         case ACLK_RKVDEC_PRE:
 637         case ACLK_RKVENC:
 638         case ACLK_VPU_PRE:
 639         case SCLK_VDEC_CABAC:
 640         case SCLK_VDEC_CORE:
 641         case SCLK_VENC_CORE:
 642         case SCLK_VENC_DSP:
 643         case SCLK_EFUSE:
 644         case PCLK_DDR:
 645         case ACLK_GMAC:
 646         case PCLK_GMAC:
 647         case SCLK_USB3OTG_SUSPEND:
 648                 return 0;
 649         default:
 650                 return -ENOENT;
 651         }
 652
 653         return ret;
 654 }
 655
 656 static int rk3328_gmac2io_set_parent(struct clk *clk, struct clk *parent)
 657 {
 658         struct rk3328_grf_regs *grf;
 659         const char *clock_output_name;
 660         int ret;
 661
 662         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 663
 664         /*
 665          * If the requested parent is in the same clock-controller and the id
 666          * is SCLK_MAC2IO_SRC ("clk_mac2io_src"), switch to the internal clock.
 667          */
 668         if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC2IO_SRC)) {
 669                 debug("%s: switching RGMII to SCLK_MAC2IO_SRC\n", __func__);
 670                 rk_clrreg(&grf->mac_con[1], BIT(10));
 671                 return 0;
 672         }
 673
 674         /*
 675          * Otherwise, we need to check the clock-output-names of the
 676          * requested parent to see if the requested id is "gmac_clkin".
 677          */
 678         ret = dev_read_string_index(parent->dev, "clock-output-names",
 679                                     parent->id, &clock_output_name);
 680         if (ret < 0)
 681                 return -ENODATA;
 682
 683         /* If this is "gmac_clkin", switch to the external clock input */
 684         if (!strcmp(clock_output_name, "gmac_clkin")) {
 685                 debug("%s: switching RGMII to CLKIN\n", __func__);
 686                 rk_setreg(&grf->mac_con[1], BIT(10));
 687                 return 0;
 688         }
 689
 690         return -EINVAL;
 691 }
 692
 693 static int rk3328_gmac2io_ext_set_parent(struct clk *clk, struct clk *parent)
 694 {
 695         struct rk3328_grf_regs *grf;
 696         const char *clock_output_name;
 697         int ret;
 698
 699         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 700
 701         /*
 702          * If the requested parent is in the same clock-controller and the id
 703          * is SCLK_MAC2IO ("clk_mac2io"), switch to the internal clock.
 704          */
 705         if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC2IO)) {
 706                 debug("%s: switching RGMII to SCLK_MAC2IO\n", __func__);
 707                 rk_clrreg(&grf->soc_con[4], BIT(14));
 708                 return 0;
 709         }
 710
 711         /*
 712          * Otherwise, we need to check the clock-output-names of the
 713          * requested parent to see if the requested id is "gmac_clkin".
 714          */
 715         ret = dev_read_string_index(parent->dev, "clock-output-names",
 716                                     parent->id, &clock_output_name);
 717         if (ret < 0)
 718                 return -ENODATA;
 719
 720         /* If this is "gmac_clkin", switch to the external clock input */
 721         if (!strcmp(clock_output_name, "gmac_clkin")) {
 722                 debug("%s: switching RGMII to CLKIN\n", __func__);
 723                 rk_setreg(&grf->soc_con[4], BIT(14));
 724                 return 0;
 725         }
 726
 727         return -EINVAL;
 728 }
 729
 730 static int rk3328_clk_set_parent(struct clk *clk, struct clk *parent)
 731 {
 732         switch (clk->id) {
 733         case SCLK_MAC2IO:
 734                 return rk3328_gmac2io_set_parent(clk, parent);
 735         case SCLK_MAC2IO_EXT:
 736                 return rk3328_gmac2io_ext_set_parent(clk, parent);
 737         case DCLK_LCDC:
 738         case SCLK_PDM:
 739         case SCLK_RTC32K:
 740         case SCLK_UART0:
 741         case SCLK_UART1:
 742         case SCLK_UART2:
 743                 return 0;
 744         }
 745
 746         debug("%s: unsupported clk %ld\n", __func__, clk->id);
 747         return -ENOENT;
 748 }
 749
 750 static struct clk_ops rk3328_clk_ops = {
 751         .get_rate = rk3328_clk_get_rate,
 752         .set_rate = rk3328_clk_set_rate,
 753         .set_parent = rk3328_clk_set_parent,
 754 };
 755
 756 static int rk3328_clk_probe(struct udevice *dev)
 757 {
 758         struct rk3328_clk_priv *priv = dev_get_priv(dev);
 759
 760         rkclk_init(priv->cru);
 761
 762         return 0;
 763 }
 764
 765 static int rk3328_clk_ofdata_to_platdata(struct udevice *dev)
 766 {
 767         struct rk3328_clk_priv *priv = dev_get_priv(dev);
 768
 769         priv->cru = dev_read_addr_ptr(dev);
 770
 771         return 0;
 772 }
 773
 774 static int rk3328_clk_bind(struct udevice *dev)
 775 {
 776         int ret;
 777         struct udevice *sys_child;
 778         struct sysreset_reg *priv;
 779
 780         /* The reset driver does not have a device node, so bind it here */
 781         ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
 782                                  &sys_child);
 783         if (ret) {
 784                 debug("Warning: No sysreset driver: ret=%d\n", ret);
 785         } else {
 786                 priv = malloc(sizeof(struct sysreset_reg));
 787                 priv->glb_srst_fst_value = offsetof(struct rk3328_cru,
 788                                                     glb_srst_fst_value);
 789                 priv->glb_srst_snd_value = offsetof(struct rk3328_cru,
 790                                                     glb_srst_snd_value);
 791                 sys_child->priv = priv;
 792         }
 793
 794 #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
 795         ret = offsetof(struct rk3328_cru, softrst_con[0]);
 796         ret = rockchip_reset_bind(dev, ret, 12);
 797         if (ret)
 798                 debug("Warning: software reset driver bind faile\n");
 799 #endif
 800
 801         return ret;
 802 }
 803
 804 static const struct udevice_id rk3328_clk_ids[] = {
 805         { .compatible = "rockchip,rk3328-cru" },
 806         { }
 807 };
 808
 809 U_BOOT_DRIVER(rockchip_rk3328_cru) = {
 810         .name           = "rockchip_rk3328_cru",
 811         .id             = UCLASS_CLK,
 812         .of_match       = rk3328_clk_ids,
 813         .priv_auto_alloc_size = sizeof(struct rk3328_clk_priv),
 814         .ofdata_to_platdata = rk3328_clk_ofdata_to_platdata,
 815         .ops            = &rk3328_clk_ops,
 816         .bind           = rk3328_clk_bind,
 817         .probe          = rk3328_clk_probe,
 818 };