drivers/clk/rockchip/clk_rk3308.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * (C) Copyright 2017-2019 Rockchip Electronics Co., Ltd
   4  */
   5 #include <common.h>
   6 #include <bitfield.h>
   7 #include <clk-uclass.h>
   8 #include <dm.h>
   9 #include <div64.h>
  10 #include <errno.h>
  11 #include <log.h>
  12 #include <malloc.h>
  13 #include <syscon.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/cru_rk3308.h>
  16 #include <asm/arch-rockchip/clock.h>
  17 #include <asm/arch-rockchip/hardware.h>
  18 #include <dm/lists.h>
  19 #include <dt-bindings/clock/rk3308-cru.h>
  20 #include <linux/bitops.h>
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 enum {
  25         VCO_MAX_HZ      = 3200U * 1000000,
  26         VCO_MIN_HZ      = 800 * 1000000,
  27         OUTPUT_MAX_HZ   = 3200U * 1000000,
  28         OUTPUT_MIN_HZ   = 24 * 1000000,
  29 };
  30
  31 #define DIV_TO_RATE(input_rate, div)    ((input_rate) / ((div) + 1))
  32
  33 #define RK3308_CPUCLK_RATE(_rate, _aclk_div, _pclk_div)         \
  34 {                                                               \
  35         .rate   = _rate##U,                                     \
  36         .aclk_div = _aclk_div,                                  \
  37         .pclk_div = _pclk_div,                                  \
  38 }
  39
  40 static struct rockchip_pll_rate_table rk3308_pll_rates[] = {
  41         /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
  42         RK3036_PLL_RATE(1300000000, 6, 325, 1, 1, 1, 0),
  43         RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
  44         RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
  45         RK3036_PLL_RATE(748000000, 2, 187, 3, 1, 1, 0),
  46 };
  47
  48 static struct rockchip_cpu_rate_table rk3308_cpu_rates[] = {
  49         RK3308_CPUCLK_RATE(1200000000, 1, 5),
  50         RK3308_CPUCLK_RATE(1008000000, 1, 5),
  51         RK3308_CPUCLK_RATE(816000000, 1, 3),
  52         RK3308_CPUCLK_RATE(600000000, 1, 3),
  53         RK3308_CPUCLK_RATE(408000000, 1, 1),
  54 };
  55
  56 static struct rockchip_pll_clock rk3308_pll_clks[] = {
  57         [APLL] = PLL(pll_rk3328, PLL_APLL, RK3308_PLL_CON(0),
  58                      RK3308_MODE_CON, 0, 10, 0, rk3308_pll_rates),
  59         [DPLL] = PLL(pll_rk3328, PLL_DPLL, RK3308_PLL_CON(8),
  60                      RK3308_MODE_CON, 2, 10, 0, NULL),
  61         [VPLL0] = PLL(pll_rk3328, PLL_VPLL0, RK3308_PLL_CON(16),
  62                       RK3308_MODE_CON, 4, 10, 0, NULL),
  63         [VPLL1] = PLL(pll_rk3328, PLL_VPLL1, RK3308_PLL_CON(24),
  64                       RK3308_MODE_CON, 6, 10, 0, NULL),
  65 };
  66
  67 static ulong rk3308_armclk_set_clk(struct rk3308_clk_priv *priv, ulong hz)
  68 {
  69         struct rk3308_cru *cru = priv->cru;
  70         const struct rockchip_cpu_rate_table *rate;
  71         ulong old_rate;
  72
  73         rate = rockchip_get_cpu_settings(rk3308_cpu_rates, hz);
  74         if (!rate) {
  75                 printf("%s unsupport rate\n", __func__);
  76                 return -EINVAL;
  77         }
  78
  79         /*
  80          * select apll as cpu/core clock pll source and
  81          * set up dependent divisors for PERI and ACLK clocks.
  82          * core hz : apll = 1:1
  83          */
  84         old_rate = rockchip_pll_get_rate(&rk3308_pll_clks[APLL],
  85                                          priv->cru, APLL);
  86         if (old_rate > hz) {
  87                 if (rockchip_pll_set_rate(&rk3308_pll_clks[APLL],
  88                                           priv->cru, APLL, hz))
  89                         return -EINVAL;
  90                 rk_clrsetreg(&cru->clksel_con[0],
  91                              CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK |
  92                              CORE_ACLK_DIV_MASK | CORE_DBG_DIV_MASK,
  93                              rate->aclk_div << CORE_ACLK_DIV_SHIFT |
  94                              rate->pclk_div << CORE_DBG_DIV_SHIFT |
  95                              CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
  96                              0 << CORE_DIV_CON_SHIFT);
  97         } else if (old_rate < hz) {
  98                 rk_clrsetreg(&cru->clksel_con[0],
  99                              CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK |
 100                              CORE_ACLK_DIV_MASK | CORE_DBG_DIV_MASK,
 101                              rate->aclk_div << CORE_ACLK_DIV_SHIFT |
 102                              rate->pclk_div << CORE_DBG_DIV_SHIFT |
 103                              CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
 104                              0 << CORE_DIV_CON_SHIFT);
 105                 if (rockchip_pll_set_rate(&rk3308_pll_clks[APLL],
 106                                           priv->cru, APLL, hz))
 107                         return -EINVAL;
 108         }
 109
 110         return rockchip_pll_get_rate(&rk3308_pll_clks[APLL], priv->cru, APLL);
 111 }
 112
 113 static void rk3308_clk_get_pll_rate(struct rk3308_clk_priv *priv)
 114 {
 115         if (!priv->dpll_hz)
 116                 priv->dpll_hz = rockchip_pll_get_rate(&rk3308_pll_clks[DPLL],
 117                                                       priv->cru, DPLL);
 118         if (!priv->vpll0_hz)
 119                 priv->vpll0_hz = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0],
 120                                                        priv->cru, VPLL0);
 121         if (!priv->vpll1_hz)
 122                 priv->vpll1_hz = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL1],
 123                                                        priv->cru, VPLL1);
 124 }
 125
 126 static ulong rk3308_i2c_get_clk(struct clk *clk)
 127 {
 128         struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
 129         struct rk3308_cru *cru = priv->cru;
 130         u32 div, con, con_id;
 131
 132         switch (clk->id) {
 133         case SCLK_I2C0:
 134                 con_id = 25;
 135                 break;
 136         case SCLK_I2C1:
 137                 con_id = 26;
 138                 break;
 139         case SCLK_I2C2:
 140                 con_id = 27;
 141                 break;
 142         case SCLK_I2C3:
 143                 con_id = 28;
 144                 break;
 145         default:
 146                 printf("do not support this i2c bus\n");
 147                 return -EINVAL;
 148         }
 149
 150         con = readl(&cru->clksel_con[con_id]);
 151         div = con >> CLK_I2C_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
 152
 153         return DIV_TO_RATE(priv->dpll_hz, div);
 154 }
 155
 156 static ulong rk3308_i2c_set_clk(struct clk *clk, uint hz)
 157 {
 158         struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
 159         struct rk3308_cru *cru = priv->cru;
 160         u32 src_clk_div, con_id;
 161
 162         src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz);
 163         assert(src_clk_div - 1 <= 127);
 164
 165         switch (clk->id) {
 166         case SCLK_I2C0:
 167                 con_id = 25;
 168                 break;
 169         case SCLK_I2C1:
 170                 con_id = 26;
 171                 break;
 172         case SCLK_I2C2:
 173                 con_id = 27;
 174                 break;
 175         case SCLK_I2C3:
 176                 con_id = 28;
 177                 break;
 178         default:
 179                 printf("do not support this i2c bus\n");
 180                 return -EINVAL;
 181         }
 182         rk_clrsetreg(&cru->clksel_con[con_id],
 183                      CLK_I2C_PLL_SEL_MASK | CLK_I2C_DIV_CON_MASK,
 184                      CLK_I2C_PLL_SEL_DPLL << CLK_I2C_PLL_SEL_SHIFT |
 185                      (src_clk_div - 1) << CLK_I2C_DIV_CON_SHIFT);
 186
 187         return rk3308_i2c_get_clk(clk);
 188 }
 189
 190 static ulong rk3308_mac_set_clk(struct clk *clk, uint hz)
 191 {
 192         struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
 193         struct rk3308_cru *cru = priv->cru;
 194         u32 con = readl(&cru->clksel_con[43]);
 195         ulong pll_rate;
 196         u8 div;
 197
 198         if ((con >> MAC_PLL_SHIFT) & MAC_SEL_VPLL0)
 199                 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0],
 200                                                  priv->cru, VPLL0);
 201         else if ((con >> MAC_PLL_SHIFT) & MAC_SEL_VPLL1)
 202                 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL1],
 203                                                  priv->cru, VPLL1);
 204         else
 205                 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[DPLL],
 206                                                  priv->cru, DPLL);
 207
 208         /*default set 50MHZ for gmac*/
 209         if (!hz)
 210                 hz = 50000000;
 211
 212         div = DIV_ROUND_UP(pll_rate, hz) - 1;
 213         assert(div < 32);
 214         rk_clrsetreg(&cru->clksel_con[43], MAC_DIV_MASK,
 215                      div << MAC_DIV_SHIFT);
 216
 217         return DIV_TO_RATE(pll_rate, div);
 218 }
 219
 220 static int rk3308_mac_set_speed_clk(struct clk *clk, uint hz)
 221 {
 222         struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
 223         struct rk3308_cru *cru = priv->cru;
 224
 225         if (hz != 2500000 && hz != 25000000) {
 226                 debug("Unsupported mac speed:%d\n", hz);
 227                 return -EINVAL;
 228         }
 229
 230         rk_clrsetreg(&cru->clksel_con[43], MAC_CLK_SPEED_SEL_MASK,
 231                      ((hz == 2500000) ? 0 : 1) << MAC_CLK_SPEED_SEL_SHIFT);
 232
 233         return 0;
 234 }
 235
 236 static ulong rk3308_mmc_get_clk(struct clk *clk)
 237 {
 238         struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
 239         struct rk3308_cru *cru = priv->cru;
 240         u32 div, con, con_id;
 241
 242         switch (clk->id) {
 243         case HCLK_SDMMC:
 244         case SCLK_SDMMC:
 245                 con_id = 39;
 246                 break;
 247         case HCLK_EMMC:
 248         case SCLK_EMMC:
 249         case SCLK_EMMC_SAMPLE:
 250                 con_id = 41;
 251                 break;
 252         default:
 253                 return -EINVAL;
 254         }
 255
 256         con = readl(&cru->clksel_con[con_id]);
 257         div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
 258
 259         if ((con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT
 260             == EMMC_SEL_24M)
 261                 return DIV_TO_RATE(OSC_HZ, div) / 2;
 262         else
 263                 return DIV_TO_RATE(priv->vpll0_hz, div) / 2;
 264 }
 265
 266 static ulong rk3308_mmc_set_clk(struct clk *clk, ulong set_rate)
 267 {
 268         struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
 269         struct rk3308_cru *cru = priv->cru;
 270         int src_clk_div;
 271         u32 con_id;
 272
 273         switch (clk->id) {
 274         case HCLK_SDMMC:
 275         case SCLK_SDMMC:
 276                 con_id = 39;
 277                 break;
 278         case HCLK_EMMC:
 279         case SCLK_EMMC:
 280                 con_id = 41;
 281                 break;
 282         default:
 283                 return -EINVAL;
 284         }
 285         /* Select clk_sdmmc/emmc source from VPLL0 by default */
 286         /* mmc clock defaulg div 2 internal, need provide double in cru */
 287         src_clk_div = DIV_ROUND_UP(priv->vpll0_hz / 2, set_rate);
 288
 289         if (src_clk_div > 127) {
 290                 /* use 24MHz source for 400KHz clock */
 291                 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate);
 292                 rk_clrsetreg(&cru->clksel_con[con_id],
 293                              EMMC_PLL_MASK | EMMC_DIV_MASK | EMMC_CLK_SEL_MASK,
 294                              EMMC_CLK_SEL_EMMC << EMMC_CLK_SEL_SHIFT |
 295                              EMMC_SEL_24M << EMMC_PLL_SHIFT |
 296                              (src_clk_div - 1) << EMMC_DIV_SHIFT);
 297         } else {
 298                 rk_clrsetreg(&cru->clksel_con[con_id],
 299                              EMMC_PLL_MASK | EMMC_DIV_MASK | EMMC_CLK_SEL_MASK,
 300                              EMMC_CLK_SEL_EMMC << EMMC_CLK_SEL_SHIFT |
 301                              EMMC_SEL_VPLL0 << EMMC_PLL_SHIFT |
 302                              (src_clk_div - 1) << EMMC_DIV_SHIFT);
 303         }
 304
 305         return rk3308_mmc_get_clk(clk);
 306 }
 307
 308 static ulong rk3308_saradc_get_clk(struct clk *clk)
 309 {
 310         struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
 311         struct rk3308_cru *cru = priv->cru;
 312         u32 div, con;
 313
 314         con = readl(&cru->clksel_con[34]);
 315         div = con >> CLK_SARADC_DIV_CON_SHIFT & CLK_SARADC_DIV_CON_MASK;
 316
 317         return DIV_TO_RATE(OSC_HZ, div);
 318 }
 319
 320 static ulong rk3308_saradc_set_clk(struct clk *clk, uint hz)
 321 {
 322         struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
 323         struct rk3308_cru *cru = priv->cru;
 324         int src_clk_div;
 325
 326         src_clk_div = DIV_ROUND_UP(OSC_HZ, hz);
 327         assert(src_clk_div - 1 <= 2047);
 328
 329         rk_clrsetreg(&cru->clksel_con[34],
 330                      CLK_SARADC_DIV_CON_MASK,
 331                      (src_clk_div - 1) << CLK_SARADC_DIV_CON_SHIFT);
 332
 333         return rk3308_saradc_get_clk(clk);
 334 }
 335
 336 static ulong rk3308_tsadc_get_clk(struct clk *clk)
 337 {
 338         struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
 339         struct rk3308_cru *cru = priv->cru;
 340         u32 div, con;
 341
 342         con = readl(&cru->clksel_con[33]);
 343         div = con >> CLK_SARADC_DIV_CON_SHIFT & CLK_SARADC_DIV_CON_MASK;
 344
 345         return DIV_TO_RATE(OSC_HZ, div);
 346 }
 347
 348 static ulong rk3308_tsadc_set_clk(struct clk *clk, uint hz)
 349 {
 350         struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
 351         struct rk3308_cru *cru = priv->cru;
 352         int src_clk_div;
 353
 354         src_clk_div = DIV_ROUND_UP(OSC_HZ, hz);
 355         assert(src_clk_div - 1 <= 2047);
 356
 357         rk_clrsetreg(&cru->clksel_con[33],
 358                      CLK_SARADC_DIV_CON_MASK,
 359                      (src_clk_div - 1) << CLK_SARADC_DIV_CON_SHIFT);
 360
 361         return rk3308_tsadc_get_clk(clk);
 362 }
 363
 364 static ulong rk3308_spi_get_clk(struct clk *clk)
 365 {
 366         struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
 367         struct rk3308_cru *cru = priv->cru;
 368         u32 div, con, con_id;
 369
 370         switch (clk->id) {
 371         case SCLK_SPI0:
 372                 con_id = 30;
 373                 break;
 374         case SCLK_SPI1:
 375                 con_id = 31;
 376                 break;
 377         case SCLK_SPI2:
 378                 con_id = 32;
 379                 break;
 380         default:
 381                 printf("do not support this spi bus\n");
 382                 return -EINVAL;
 383         }
 384
 385         con = readl(&cru->clksel_con[con_id]);
 386         div = con >> CLK_SPI_DIV_CON_SHIFT & CLK_SPI_DIV_CON_MASK;
 387
 388         return DIV_TO_RATE(priv->dpll_hz, div);
 389 }
 390
 391 static ulong rk3308_spi_set_clk(struct clk *clk, uint hz)
 392 {
 393         struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
 394         struct rk3308_cru *cru = priv->cru;
 395         u32 src_clk_div, con_id;
 396
 397         src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz);
 398         assert(src_clk_div - 1 <= 127);
 399
 400         switch (clk->id) {
 401         case SCLK_SPI0:
 402                 con_id = 30;
 403                 break;
 404         case SCLK_SPI1:
 405                 con_id = 31;
 406                 break;
 407         case SCLK_SPI2:
 408                 con_id = 32;
 409                 break;
 410         default:
 411                 printf("do not support this spi bus\n");
 412                 return -EINVAL;
 413         }
 414
 415         rk_clrsetreg(&cru->clksel_con[con_id],
 416                      CLK_SPI_PLL_SEL_MASK | CLK_SPI_DIV_CON_MASK,
 417                      CLK_SPI_PLL_SEL_DPLL << CLK_SPI_PLL_SEL_SHIFT |
 418                      (src_clk_div - 1) << CLK_SPI_DIV_CON_SHIFT);
 419
 420         return rk3308_spi_get_clk(clk);
 421 }
 422
 423 static ulong rk3308_pwm_get_clk(struct clk *clk)
 424 {
 425         struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
 426         struct rk3308_cru *cru = priv->cru;
 427         u32 div, con;
 428
 429         con = readl(&cru->clksel_con[29]);
 430         div = con >> CLK_PWM_DIV_CON_SHIFT & CLK_PWM_DIV_CON_MASK;
 431
 432         return DIV_TO_RATE(priv->dpll_hz, div);
 433 }
 434
 435 static ulong rk3308_pwm_set_clk(struct clk *clk, uint hz)
 436 {
 437         struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
 438         struct rk3308_cru *cru = priv->cru;
 439         int src_clk_div;
 440
 441         src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz);
 442         assert(src_clk_div - 1 <= 127);
 443
 444         rk_clrsetreg(&cru->clksel_con[29],
 445                      CLK_PWM_PLL_SEL_MASK | CLK_PWM_DIV_CON_MASK,
 446                      CLK_PWM_PLL_SEL_DPLL << CLK_PWM_PLL_SEL_SHIFT |
 447                      (src_clk_div - 1) << CLK_PWM_DIV_CON_SHIFT);
 448
 449         return rk3308_pwm_get_clk(clk);
 450 }
 451
 452 static ulong rk3308_vop_get_clk(struct clk *clk)
 453 {
 454         struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
 455         struct rk3308_cru *cru = priv->cru;
 456         u32 div, pll_sel, vol_sel, con, parent;
 457
 458         con = readl(&cru->clksel_con[8]);
 459         vol_sel = (con & DCLK_VOP_SEL_MASK) >> DCLK_VOP_SEL_SHIFT;
 460         pll_sel = (con & DCLK_VOP_PLL_SEL_MASK) >> DCLK_VOP_PLL_SEL_SHIFT;
 461         div = con & DCLK_VOP_DIV_MASK;
 462
 463         if (vol_sel == DCLK_VOP_SEL_24M) {
 464                 parent = OSC_HZ;
 465         } else if (vol_sel == DCLK_VOP_SEL_DIVOUT) {
 466                 switch (pll_sel) {
 467                 case DCLK_VOP_PLL_SEL_DPLL:
 468                         parent = priv->dpll_hz;
 469                         break;
 470                 case DCLK_VOP_PLL_SEL_VPLL0:
 471                         parent = priv->vpll0_hz;
 472                         break;
 473                 case DCLK_VOP_PLL_SEL_VPLL1:
 474                         parent = priv->vpll0_hz;
 475                         break;
 476                 default:
 477                         printf("do not support this vop pll sel\n");
 478                         return -EINVAL;
 479                 }
 480         } else {
 481                 printf("do not support this vop sel\n");
 482                 return -EINVAL;
 483         }
 484
 485         return DIV_TO_RATE(parent, div);
 486 }
 487
 488 static ulong rk3308_vop_set_clk(struct clk *clk, ulong hz)
 489 {
 490         struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
 491         struct rk3308_cru *cru = priv->cru;
 492         ulong pll_rate, now, best_rate = 0;
 493         u32 i, div, best_div = 0, best_sel = 0;
 494
 495         for (i = 0; i <= DCLK_VOP_PLL_SEL_VPLL1; i++) {
 496                 switch (i) {
 497                 case DCLK_VOP_PLL_SEL_DPLL:
 498                         pll_rate = priv->dpll_hz;
 499                         break;
 500                 case DCLK_VOP_PLL_SEL_VPLL0:
 501                         pll_rate = priv->vpll0_hz;
 502                         break;
 503                 case DCLK_VOP_PLL_SEL_VPLL1:
 504                         pll_rate = priv->vpll1_hz;
 505                         break;
 506                 default:
 507                         printf("do not support this vop pll sel\n");
 508                         return -EINVAL;
 509                 }
 510
 511                 div = DIV_ROUND_UP(pll_rate, hz);
 512                 if (div > 255)
 513                         continue;
 514                 now = pll_rate / div;
 515                 if (abs(hz - now) < abs(hz - best_rate)) {
 516                         best_rate = now;
 517                         best_div = div;
 518                         best_sel = i;
 519                 }
 520                 debug("pll_rate=%lu, best_rate=%lu, best_div=%u, best_sel=%u\n",
 521                       pll_rate, best_rate, best_div, best_sel);
 522         }
 523
 524         if (best_rate != hz && hz == OSC_HZ) {
 525                 rk_clrsetreg(&cru->clksel_con[8],
 526                              DCLK_VOP_SEL_MASK,
 527                              DCLK_VOP_SEL_24M << DCLK_VOP_SEL_SHIFT);
 528         } else if (best_rate) {
 529                 rk_clrsetreg(&cru->clksel_con[8],
 530                              DCLK_VOP_SEL_MASK | DCLK_VOP_PLL_SEL_MASK |
 531                              DCLK_VOP_DIV_MASK,
 532                              DCLK_VOP_SEL_DIVOUT << DCLK_VOP_SEL_SHIFT |
 533                              best_sel << DCLK_VOP_PLL_SEL_SHIFT |
 534                              (best_div - 1) << DCLK_VOP_DIV_SHIFT);
 535         } else {
 536                 printf("do not support this vop freq\n");
 537                 return -EINVAL;
 538         }
 539
 540         return rk3308_vop_get_clk(clk);
 541 }
 542
 543 static ulong rk3308_bus_get_clk(struct rk3308_clk_priv *priv, ulong clk_id)
 544 {
 545         struct rk3308_cru *cru = priv->cru;
 546         u32 div, con, parent = priv->dpll_hz;
 547
 548         switch (clk_id) {
 549         case ACLK_BUS:
 550                 con = readl(&cru->clksel_con[5]);
 551                 div = (con & BUS_ACLK_DIV_MASK) >> BUS_ACLK_DIV_SHIFT;
 552                 break;
 553         case HCLK_BUS:
 554                 con = readl(&cru->clksel_con[6]);
 555                 div = (con & BUS_HCLK_DIV_MASK) >> BUS_HCLK_DIV_SHIFT;
 556                 break;
 557         case PCLK_BUS:
 558         case PCLK_WDT:
 559                 con = readl(&cru->clksel_con[6]);
 560                 div = (con & BUS_PCLK_DIV_MASK) >> BUS_PCLK_DIV_SHIFT;
 561                 break;
 562         default:
 563                 return -ENOENT;
 564         }
 565
 566         return DIV_TO_RATE(parent, div);
 567 }
 568
 569 static ulong rk3308_bus_set_clk(struct rk3308_clk_priv *priv, ulong clk_id,
 570                                 ulong hz)
 571 {
 572         struct rk3308_cru *cru = priv->cru;
 573         int src_clk_div;
 574
 575         src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz);
 576         assert(src_clk_div - 1 <= 31);
 577
 578         /*
 579          * select dpll as pd_bus bus clock source and
 580          * set up dependent divisors for PCLK/HCLK and ACLK clocks.
 581          */
 582         switch (clk_id) {
 583         case ACLK_BUS:
 584                 rk_clrsetreg(&cru->clksel_con[5],
 585                              BUS_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,
 586                              BUS_PLL_SEL_DPLL << BUS_PLL_SEL_SHIFT |
 587                              (src_clk_div - 1) << BUS_ACLK_DIV_SHIFT);
 588                 break;
 589         case HCLK_BUS:
 590                 rk_clrsetreg(&cru->clksel_con[6],
 591                              BUS_HCLK_DIV_MASK,
 592                              (src_clk_div - 1) << BUS_HCLK_DIV_SHIFT);
 593                 break;
 594         case PCLK_BUS:
 595                 rk_clrsetreg(&cru->clksel_con[6],
 596                              BUS_PCLK_DIV_MASK,
 597                              (src_clk_div - 1) << BUS_PCLK_DIV_SHIFT);
 598                 break;
 599         default:
 600                 printf("do not support this bus freq\n");
 601                 return -EINVAL;
 602         }
 603
 604         return rk3308_bus_get_clk(priv, clk_id);
 605 }
 606
 607 static ulong rk3308_peri_get_clk(struct rk3308_clk_priv *priv, ulong clk_id)
 608 {
 609         struct rk3308_cru *cru = priv->cru;
 610         u32 div, con, parent = priv->dpll_hz;
 611
 612         switch (clk_id) {
 613         case ACLK_PERI:
 614                 con = readl(&cru->clksel_con[36]);
 615                 div = (con & PERI_ACLK_DIV_MASK) >> PERI_ACLK_DIV_SHIFT;
 616                 break;
 617         case HCLK_PERI:
 618                 con = readl(&cru->clksel_con[37]);
 619                 div = (con & PERI_HCLK_DIV_MASK) >> PERI_HCLK_DIV_SHIFT;
 620                 break;
 621         case PCLK_PERI:
 622                 con = readl(&cru->clksel_con[37]);
 623                 div = (con & PERI_PCLK_DIV_MASK) >> PERI_PCLK_DIV_SHIFT;
 624                 break;
 625         default:
 626                 return -ENOENT;
 627         }
 628
 629         return DIV_TO_RATE(parent, div);
 630 }
 631
 632 static ulong rk3308_peri_set_clk(struct rk3308_clk_priv *priv, ulong clk_id,
 633                                  ulong hz)
 634 {
 635         struct rk3308_cru *cru = priv->cru;
 636         int src_clk_div;
 637
 638         src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz);
 639         assert(src_clk_div - 1 <= 31);
 640
 641         /*
 642          * select dpll as pd_peri bus clock source and
 643          * set up dependent divisors for PCLK/HCLK and ACLK clocks.
 644          */
 645         switch (clk_id) {
 646         case ACLK_PERI:
 647                 rk_clrsetreg(&cru->clksel_con[36],
 648                              PERI_PLL_SEL_MASK | PERI_ACLK_DIV_MASK,
 649                              PERI_PLL_DPLL << PERI_PLL_SEL_SHIFT |
 650                              (src_clk_div - 1) << PERI_ACLK_DIV_SHIFT);
 651                 break;
 652         case HCLK_PERI:
 653                 rk_clrsetreg(&cru->clksel_con[37],
 654                              PERI_HCLK_DIV_MASK,
 655                              (src_clk_div - 1) << PERI_HCLK_DIV_SHIFT);
 656                 break;
 657         case PCLK_PERI:
 658                 rk_clrsetreg(&cru->clksel_con[37],
 659                              PERI_PCLK_DIV_MASK,
 660                              (src_clk_div - 1) << PERI_PCLK_DIV_SHIFT);
 661                 break;
 662         default:
 663                 printf("do not support this peri freq\n");
 664                 return -EINVAL;
 665         }
 666
 667         return rk3308_peri_get_clk(priv, clk_id);
 668 }
 669
 670 static ulong rk3308_audio_get_clk(struct rk3308_clk_priv *priv, ulong clk_id)
 671 {
 672         struct rk3308_cru *cru = priv->cru;
 673         u32 div, con, parent = priv->vpll0_hz;
 674
 675         switch (clk_id) {
 676         case HCLK_AUDIO:
 677                 con = readl(&cru->clksel_con[45]);
 678                 div = (con & AUDIO_HCLK_DIV_MASK) >> AUDIO_HCLK_DIV_SHIFT;
 679                 break;
 680         case PCLK_AUDIO:
 681                 con = readl(&cru->clksel_con[45]);
 682                 div = (con & AUDIO_PCLK_DIV_MASK) >> AUDIO_PCLK_DIV_SHIFT;
 683                 break;
 684         default:
 685                 return -ENOENT;
 686         }
 687
 688         return DIV_TO_RATE(parent, div);
 689 }
 690
 691 static ulong rk3308_audio_set_clk(struct rk3308_clk_priv *priv, ulong clk_id,
 692                                   ulong hz)
 693 {
 694         struct rk3308_cru *cru = priv->cru;
 695         int src_clk_div;
 696
 697         src_clk_div = DIV_ROUND_UP(priv->vpll0_hz, hz);
 698         assert(src_clk_div - 1 <= 31);
 699
 700         /*
 701          * select vpll0 as audio bus clock source and
 702          * set up dependent divisors for HCLK and PCLK clocks.
 703          */
 704         switch (clk_id) {
 705         case HCLK_AUDIO:
 706                 rk_clrsetreg(&cru->clksel_con[45],
 707                              AUDIO_PLL_SEL_MASK | AUDIO_HCLK_DIV_MASK,
 708                              AUDIO_PLL_VPLL0 << AUDIO_PLL_SEL_SHIFT |
 709                              (src_clk_div - 1) << AUDIO_HCLK_DIV_SHIFT);
 710                 break;
 711         case PCLK_AUDIO:
 712                 rk_clrsetreg(&cru->clksel_con[45],
 713                              AUDIO_PLL_SEL_MASK | AUDIO_PCLK_DIV_MASK,
 714                              AUDIO_PLL_VPLL0 << AUDIO_PLL_SEL_SHIFT |
 715                              (src_clk_div - 1) << AUDIO_PCLK_DIV_SHIFT);
 716                 break;
 717         default:
 718                 printf("do not support this audio freq\n");
 719                 return -EINVAL;
 720         }
 721
 722         return rk3308_peri_get_clk(priv, clk_id);
 723 }
 724
 725 static ulong rk3308_crypto_get_clk(struct rk3308_clk_priv *priv, ulong clk_id)
 726 {
 727         struct rk3308_cru *cru = priv->cru;
 728         u32 div, con, parent;
 729
 730         switch (clk_id) {
 731         case SCLK_CRYPTO:
 732                 con = readl(&cru->clksel_con[7]);
 733                 div = (con & CRYPTO_DIV_MASK) >> CRYPTO_DIV_SHIFT;
 734                 parent = priv->vpll0_hz;
 735                 break;
 736         case SCLK_CRYPTO_APK:
 737                 con = readl(&cru->clksel_con[7]);
 738                 div = (con & CRYPTO_APK_DIV_MASK) >> CRYPTO_APK_DIV_SHIFT;
 739                 parent = priv->vpll0_hz;
 740                 break;
 741         default:
 742                 return -ENOENT;
 743         }
 744
 745         return DIV_TO_RATE(parent, div);
 746 }
 747
 748 static ulong rk3308_crypto_set_clk(struct rk3308_clk_priv *priv, ulong clk_id,
 749                                    ulong hz)
 750 {
 751         struct rk3308_cru *cru = priv->cru;
 752         int src_clk_div;
 753
 754         src_clk_div = DIV_ROUND_UP(priv->vpll0_hz, hz);
 755         assert(src_clk_div - 1 <= 31);
 756
 757         /*
 758          * select gpll as crypto clock source and
 759          * set up dependent divisors for crypto clocks.
 760          */
 761         switch (clk_id) {
 762         case SCLK_CRYPTO:
 763                 rk_clrsetreg(&cru->clksel_con[7],
 764                              CRYPTO_PLL_SEL_MASK | CRYPTO_DIV_MASK,
 765                              CRYPTO_PLL_SEL_VPLL0 << CRYPTO_PLL_SEL_SHIFT |
 766                              (src_clk_div - 1) << CRYPTO_DIV_SHIFT);
 767                 break;
 768         case SCLK_CRYPTO_APK:
 769                 rk_clrsetreg(&cru->clksel_con[7],
 770                              CRYPTO_APK_PLL_SEL_MASK | CRYPTO_APK_DIV_MASK,
 771                              CRYPTO_PLL_SEL_VPLL0 << CRYPTO_APK_SEL_SHIFT |
 772                              (src_clk_div - 1) << CRYPTO_APK_DIV_SHIFT);
 773                 break;
 774         default:
 775                 printf("do not support this peri freq\n");
 776                 return -EINVAL;
 777         }
 778
 779         return rk3308_crypto_get_clk(priv, clk_id);
 780 }
 781
 782 static ulong rk3308_clk_get_rate(struct clk *clk)
 783 {
 784         struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
 785         ulong rate = 0;
 786
 787         debug("%s id:%ld\n", __func__, clk->id);
 788
 789         switch (clk->id) {
 790         case PLL_APLL:
 791         case ARMCLK:
 792                 rate = rockchip_pll_get_rate(&rk3308_pll_clks[APLL],
 793                                              priv->cru, APLL);
 794                 break;
 795         case PLL_DPLL:
 796                 rate = rockchip_pll_get_rate(&rk3308_pll_clks[DPLL],
 797                                              priv->cru, DPLL);
 798                 break;
 799         case PLL_VPLL0:
 800                 rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0],
 801                                              priv->cru, VPLL0);
 802                 break;
 803         case PLL_VPLL1:
 804                 rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL1],
 805                                              priv->cru, VPLL1);
 806                 break;
 807         case HCLK_SDMMC:
 808         case HCLK_EMMC:
 809         case SCLK_SDMMC:
 810         case SCLK_EMMC:
 811         case SCLK_EMMC_SAMPLE:
 812                 rate = rk3308_mmc_get_clk(clk);
 813                 break;
 814         case SCLK_I2C0:
 815         case SCLK_I2C1:
 816         case SCLK_I2C2:
 817         case SCLK_I2C3:
 818                 rate = rk3308_i2c_get_clk(clk);
 819                 break;
 820         case SCLK_SARADC:
 821                 rate = rk3308_saradc_get_clk(clk);
 822                 break;
 823         case SCLK_TSADC:
 824                 rate = rk3308_tsadc_get_clk(clk);
 825                 break;
 826         case SCLK_SPI0:
 827         case SCLK_SPI1:
 828                 rate = rk3308_spi_get_clk(clk);
 829                 break;
 830         case SCLK_PWM0:
 831                 rate = rk3308_pwm_get_clk(clk);
 832                 break;
 833         case DCLK_VOP:
 834                 rate = rk3308_vop_get_clk(clk);
 835                 break;
 836         case ACLK_BUS:
 837         case HCLK_BUS:
 838         case PCLK_BUS:
 839         case PCLK_WDT:
 840                 rate = rk3308_bus_get_clk(priv, clk->id);
 841                 break;
 842         case ACLK_PERI:
 843         case HCLK_PERI:
 844         case PCLK_PERI:
 845                 rate = rk3308_peri_get_clk(priv, clk->id);
 846                 break;
 847         case HCLK_AUDIO:
 848         case PCLK_AUDIO:
 849                 rate = rk3308_audio_get_clk(priv, clk->id);
 850                 break;
 851         case SCLK_CRYPTO:
 852         case SCLK_CRYPTO_APK:
 853                 rate = rk3308_crypto_get_clk(priv, clk->id);
 854                 break;
 855         default:
 856                 return -ENOENT;
 857         }
 858
 859         return rate;
 860 }
 861
 862 static ulong rk3308_clk_set_rate(struct clk *clk, ulong rate)
 863 {
 864         struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
 865         ulong ret = 0;
 866
 867         debug("%s %ld %ld\n", __func__, clk->id, rate);
 868
 869         switch (clk->id) {
 870         case PLL_DPLL:
 871                 ret = rockchip_pll_set_rate(&rk3308_pll_clks[DPLL], priv->cru,
 872                                             DPLL, rate);
 873                 priv->dpll_hz = rockchip_pll_get_rate(&rk3308_pll_clks[DPLL],
 874                                                       priv->cru, DPLL);
 875                 break;
 876         case ARMCLK:
 877                 if (priv->armclk_hz)
 878                         rk3308_armclk_set_clk(priv, rate);
 879                 priv->armclk_hz = rate;
 880                 break;
 881         case HCLK_SDMMC:
 882         case HCLK_EMMC:
 883         case SCLK_SDMMC:
 884         case SCLK_EMMC:
 885                 ret = rk3308_mmc_set_clk(clk, rate);
 886                 break;
 887         case SCLK_I2C0:
 888         case SCLK_I2C1:
 889         case SCLK_I2C2:
 890         case SCLK_I2C3:
 891                 ret = rk3308_i2c_set_clk(clk, rate);
 892                 break;
 893         case SCLK_MAC:
 894                 ret = rk3308_mac_set_clk(clk, rate);
 895                 break;
 896         case SCLK_MAC_RMII:
 897                 ret = rk3308_mac_set_speed_clk(clk, rate);
 898                 break;
 899         case SCLK_SARADC:
 900                 ret = rk3308_saradc_set_clk(clk, rate);
 901                 break;
 902         case SCLK_TSADC:
 903                 ret = rk3308_tsadc_set_clk(clk, rate);
 904                 break;
 905         case SCLK_SPI0:
 906         case SCLK_SPI1:
 907                 ret = rk3308_spi_set_clk(clk, rate);
 908                 break;
 909         case SCLK_PWM0:
 910                 ret = rk3308_pwm_set_clk(clk, rate);
 911                 break;
 912         case DCLK_VOP:
 913                 ret = rk3308_vop_set_clk(clk, rate);
 914                 break;
 915         case ACLK_BUS:
 916         case HCLK_BUS:
 917         case PCLK_BUS:
 918                 rate = rk3308_bus_set_clk(priv, clk->id, rate);
 919                 break;
 920         case ACLK_PERI:
 921         case HCLK_PERI:
 922         case PCLK_PERI:
 923                 rate = rk3308_peri_set_clk(priv, clk->id, rate);
 924                 break;
 925         case HCLK_AUDIO:
 926         case PCLK_AUDIO:
 927                 rate = rk3308_audio_set_clk(priv, clk->id, rate);
 928                 break;
 929         case SCLK_CRYPTO:
 930         case SCLK_CRYPTO_APK:
 931                 ret = rk3308_crypto_set_clk(priv, clk->id, rate);
 932                 break;
 933         default:
 934                 return -ENOENT;
 935         }
 936
 937         return ret;
 938 }
 939
 940 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
 941 static int __maybe_unused rk3308_mac_set_parent(struct clk *clk, struct clk *parent)
 942 {
 943         struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
 944
 945         /*
 946          * If the requested parent is in the same clock-controller and
 947          * the id is SCLK_MAC_SRC, switch to the internal clock.
 948          */
 949         if (parent->id == SCLK_MAC_SRC) {
 950                 debug("%s: switching RMII to SCLK_MAC\n", __func__);
 951                 rk_clrreg(&priv->cru->clksel_con[43], BIT(14));
 952         } else {
 953                 debug("%s: switching RMII to CLKIN\n", __func__);
 954                 rk_setreg(&priv->cru->clksel_con[43], BIT(14));
 955         }
 956
 957         return 0;
 958 }
 959
 960 static int __maybe_unused rk3308_clk_set_parent(struct clk *clk, struct clk *parent)
 961 {
 962         switch (clk->id) {
 963         case SCLK_MAC:
 964                 return rk3308_mac_set_parent(clk, parent);
 965         default:
 966                 break;
 967         }
 968
 969         debug("%s: unsupported clk %ld\n", __func__, clk->id);
 970         return -ENOENT;
 971 }
 972 #endif
 973
 974 static struct clk_ops rk3308_clk_ops = {
 975         .get_rate = rk3308_clk_get_rate,
 976         .set_rate = rk3308_clk_set_rate,
 977 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
 978         .set_parent = rk3308_clk_set_parent,
 979 #endif
 980 };
 981
 982 static void rk3308_clk_init(struct udevice *dev)
 983 {
 984         struct rk3308_clk_priv *priv = dev_get_priv(dev);
 985         int ret;
 986
 987         if (rockchip_pll_get_rate(&rk3308_pll_clks[APLL],
 988                                   priv->cru, APLL) != APLL_HZ) {
 989                 ret = rk3308_armclk_set_clk(priv, APLL_HZ);
 990                 if (ret < 0)
 991                         printf("%s failed to set armclk rate\n", __func__);
 992         }
 993
 994         rk3308_clk_get_pll_rate(priv);
 995
 996         rk3308_bus_set_clk(priv, ACLK_BUS, BUS_ACLK_HZ);
 997         rk3308_bus_set_clk(priv, HCLK_BUS, BUS_HCLK_HZ);
 998         rk3308_bus_set_clk(priv, PCLK_BUS, BUS_PCLK_HZ);
 999
1000         rk3308_peri_set_clk(priv, ACLK_PERI, PERI_ACLK_HZ);
1001         rk3308_peri_set_clk(priv, HCLK_PERI, PERI_HCLK_HZ);
1002         rk3308_peri_set_clk(priv, PCLK_PERI, PERI_PCLK_HZ);
1003
1004         rk3308_audio_set_clk(priv, HCLK_AUDIO, AUDIO_HCLK_HZ);
1005         rk3308_audio_set_clk(priv, PCLK_AUDIO, AUDIO_PCLK_HZ);
1006 }
1007
1008 static int rk3308_clk_probe(struct udevice *dev)
1009 {
1010         int ret;
1011
1012         rk3308_clk_init(dev);
1013
1014         /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
1015         ret = clk_set_defaults(dev, 1);
1016         if (ret)
1017                 debug("%s clk_set_defaults failed %d\n", __func__, ret);
1018
1019         return ret;
1020 }
1021
1022 static int rk3308_clk_ofdata_to_platdata(struct udevice *dev)
1023 {
1024         struct rk3308_clk_priv *priv = dev_get_priv(dev);
1025
1026         priv->cru = dev_read_addr_ptr(dev);
1027
1028         return 0;
1029 }
1030
1031 static int rk3308_clk_bind(struct udevice *dev)
1032 {
1033         int ret;
1034         struct udevice *sys_child;
1035         struct sysreset_reg *priv;
1036
1037         /* The reset driver does not have a device node, so bind it here */
1038         ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
1039                                  &sys_child);
1040         if (ret) {
1041                 debug("Warning: No sysreset driver: ret=%d\n", ret);
1042         } else {
1043                 priv = malloc(sizeof(struct sysreset_reg));
1044                 priv->glb_srst_fst_value = offsetof(struct rk3308_cru,
1045                                                     glb_srst_fst);
1046                 priv->glb_srst_snd_value = offsetof(struct rk3308_cru,
1047                                                     glb_srst_snd);
1048                 sys_child->priv = priv;
1049         }
1050
1051 #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
1052         ret = offsetof(struct rk3308_cru, softrst_con[0]);
1053         ret = rockchip_reset_bind(dev, ret, 12);
1054         if (ret)
1055                 debug("Warning: software reset driver bind faile\n");
1056 #endif
1057
1058         return 0;
1059 }
1060
1061 static const struct udevice_id rk3308_clk_ids[] = {
1062         { .compatible = "rockchip,rk3308-cru" },
1063         { }
1064 };
1065
1066 U_BOOT_DRIVER(rockchip_rk3308_cru) = {
1067         .name           = "rockchip_rk3308_cru",
1068         .id             = UCLASS_CLK,
1069         .of_match       = rk3308_clk_ids,
1070         .priv_auto_alloc_size = sizeof(struct rk3308_clk_priv),
1071         .ofdata_to_platdata = rk3308_clk_ofdata_to_platdata,
1072         .ops            = &rk3308_clk_ops,
1073         .bind           = rk3308_clk_bind,
1074         .probe          = rk3308_clk_probe,
1075 };