1 // SPDX-License-Identifier: GPL-2.0
3 * (C) Copyright 2015 Google, Inc
8 #include <clk-uclass.h>
11 #include <dt-structs.h>
16 #include <asm/arch-rockchip/clock.h>
17 #include <asm/arch-rockchip/cru_rk3288.h>
18 #include <asm/arch-rockchip/grf_rk3288.h>
19 #include <asm/arch-rockchip/hardware.h>
20 #include <dt-bindings/clock/rk3288-cru.h>
21 #include <dm/device-internal.h>
23 #include <dm/uclass-internal.h>
24 #include <linux/log2.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 struct rk3288_clk_plat {
29 #if CONFIG_IS_ENABLED(OF_PLATDATA)
30 struct dtd_rockchip_rk3288_cru dtd;
41 VCO_MAX_HZ = 2200U * 1000000,
42 VCO_MIN_HZ = 440 * 1000000,
43 OUTPUT_MAX_HZ = 2200U * 1000000,
44 OUTPUT_MIN_HZ = 27500000,
45 FREF_MAX_HZ = 2200U * 1000000,
46 FREF_MIN_HZ = 269 * 1000,
57 PLL_BWADJ_MASK = 0x0fff,
63 CORE_SEL_PLL_SHIFT = 15,
64 CORE_SEL_PLL_MASK = 1 << CORE_SEL_PLL_SHIFT,
66 A17_DIV_MASK = 0x1f << A17_DIV_SHIFT,
68 MP_DIV_MASK = 0xf << MP_DIV_SHIFT,
70 M0_DIV_MASK = 0xf << M0_DIV_SHIFT,
72 /* CLKSEL1: pd bus clk pll sel: codec or general */
73 PD_BUS_SEL_PLL_MASK = 15,
77 /* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */
78 PD_BUS_PCLK_DIV_SHIFT = 12,
79 PD_BUS_PCLK_DIV_MASK = 7 << PD_BUS_PCLK_DIV_SHIFT,
81 /* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
82 PD_BUS_HCLK_DIV_SHIFT = 8,
83 PD_BUS_HCLK_DIV_MASK = 3 << PD_BUS_HCLK_DIV_SHIFT,
85 /* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */
86 PD_BUS_ACLK_DIV0_SHIFT = 3,
87 PD_BUS_ACLK_DIV0_MASK = 0x1f << PD_BUS_ACLK_DIV0_SHIFT,
88 PD_BUS_ACLK_DIV1_SHIFT = 0,
89 PD_BUS_ACLK_DIV1_MASK = 0x7 << PD_BUS_ACLK_DIV1_SHIFT,
93 * peripheral bus pclk div:
94 * aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1
96 PERI_SEL_PLL_SHIFT = 15,
97 PERI_SEL_PLL_MASK = 1 << PERI_SEL_PLL_SHIFT,
101 PERI_PCLK_DIV_SHIFT = 12,
102 PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT,
104 /* peripheral bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
105 PERI_HCLK_DIV_SHIFT = 8,
106 PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT,
109 * peripheral bus aclk div:
110 * aclk_periph = periph_clk_src / (peri_aclk_div_con + 1)
112 PERI_ACLK_DIV_SHIFT = 0,
113 PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT,
118 * clk_saradc=24MHz/(saradc_div_con+1)
120 CLK_SARADC_DIV_CON_SHIFT = 8,
121 CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8),
122 CLK_SARADC_DIV_CON_WIDTH = 8,
124 SOCSTS_DPLL_LOCK = 1 << 5,
125 SOCSTS_APLL_LOCK = 1 << 6,
126 SOCSTS_CPLL_LOCK = 1 << 7,
127 SOCSTS_GPLL_LOCK = 1 << 8,
128 SOCSTS_NPLL_LOCK = 1 << 9,
131 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
133 #define PLL_DIVISORS(hz, _nr, _no) {\
134 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
135 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
136 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
137 "divisors on line " __stringify(__LINE__));
139 /* Keep divisors as low as possible to reduce jitter and power usage */
140 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
141 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
142 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
144 static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
145 const struct pll_div *div)
147 int pll_id = rk_pll_id(clk_id);
148 struct rk3288_pll *pll = &cru->pll[pll_id];
149 /* All PLLs have same VCO and output frequency range restrictions. */
150 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
151 uint output_hz = vco_hz / div->no;
153 debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
154 (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz);
155 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
156 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ &&
157 (div->no == 1 || !(div->no % 2)));
160 rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
162 rk_clrsetreg(&pll->con0, CLKR_MASK | PLL_OD_MASK,
163 ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));
164 rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);
165 rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
169 /* return from reset */
170 rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT);
175 static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf,
178 static const struct pll_div dpll_cfg[] = {
179 {.nf = 25, .nr = 2, .no = 1},
180 {.nf = 400, .nr = 9, .no = 2},
181 {.nf = 500, .nr = 9, .no = 2},
182 {.nf = 100, .nr = 3, .no = 1},
190 case 533000000: /* actually 533.3P MHz */
193 case 666000000: /* actually 666.6P MHz */
200 debug("Unsupported SDRAM frequency");
204 /* pll enter slow-mode */
205 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
206 DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
208 rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]);
210 /* wait for pll lock */
211 while (!(readl(&grf->soc_status[1]) & SOCSTS_DPLL_LOCK))
214 /* PLL enter normal-mode */
215 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
216 DPLL_MODE_NORMAL << DPLL_MODE_SHIFT);
221 #ifndef CONFIG_SPL_BUILD
222 #define VCO_MAX_KHZ 2200000
223 #define VCO_MIN_KHZ 440000
224 #define FREF_MAX_KHZ 2200000
225 #define FREF_MIN_KHZ 269
227 static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div)
229 uint ref_khz = OSC_HZ / 1000, nr, nf = 0;
231 uint diff_khz, best_diff_khz;
232 const uint max_nr = 1 << 6, max_nf = 1 << 12, max_no = 1 << 4;
235 uint freq_khz = freq_hz / 1000;
238 printf("%s: the frequency can not be 0 Hz\n", __func__);
242 no = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
244 *ext_div = DIV_ROUND_UP(no, max_no);
245 no = DIV_ROUND_UP(no, *ext_div);
248 /* only even divisors (and 1) are supported */
250 no = DIV_ROUND_UP(no, 2) * 2;
252 vco_khz = freq_khz * no;
256 if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || no > max_no) {
257 printf("%s: Cannot find out a supported VCO for Frequency (%luHz).\n",
264 best_diff_khz = vco_khz;
265 for (nr = 1; nr < max_nr && best_diff_khz; nr++) {
266 fref_khz = ref_khz / nr;
267 if (fref_khz < FREF_MIN_KHZ)
269 if (fref_khz > FREF_MAX_KHZ)
272 nf = vco_khz / fref_khz;
275 diff_khz = vco_khz - nf * fref_khz;
276 if (nf + 1 < max_nf && diff_khz > fref_khz / 2) {
278 diff_khz = fref_khz - diff_khz;
281 if (diff_khz >= best_diff_khz)
284 best_diff_khz = diff_khz;
289 if (best_diff_khz > 4 * 1000) {
290 printf("%s: Failed to match output frequency %lu, difference is %u Hz, exceed 4MHZ\n",
291 __func__, freq_hz, best_diff_khz * 1000);
298 static int rockchip_mac_set_clk(struct rk3288_cru *cru, uint freq)
303 * The gmac clock can be derived either from an external clock
304 * or can be generated from internally by a divider from SCLK_MAC.
306 if (readl(&cru->cru_clksel_con[21]) & RMII_EXTCLK_MASK) {
307 /* An external clock will always generate the right rate... */
310 u32 con = readl(&cru->cru_clksel_con[21]);
314 if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) ==
315 EMAC_PLL_SELECT_GENERAL)
317 else if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) ==
318 EMAC_PLL_SELECT_CODEC)
323 div = DIV_ROUND_UP(pll_rate, freq) - 1;
325 rk_clrsetreg(&cru->cru_clksel_con[21], MAC_DIV_CON_MASK,
326 div << MAC_DIV_CON_SHIFT);
328 debug("Unsupported div for gmac:%d\n", div);
330 return DIV_TO_RATE(pll_rate, div);
336 static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
337 int periph, unsigned int rate_hz)
339 struct pll_div npll_config = {0};
343 ret = pll_para_config(rate_hz, &npll_config, &lcdc_div);
347 rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK,
348 NPLL_MODE_SLOW << NPLL_MODE_SHIFT);
349 rkclk_set_pll(cru, CLK_NEW, &npll_config);
351 /* waiting for pll lock */
353 if (readl(&grf->soc_status[1]) & SOCSTS_NPLL_LOCK)
358 rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK,
359 NPLL_MODE_NORMAL << NPLL_MODE_SHIFT);
361 /* vop dclk source clk: npll,dclk_div: 1 */
364 rk_clrsetreg(&cru->cru_clksel_con[27], 0xff << 8 | 3 << 0,
365 (lcdc_div - 1) << 8 | 2 << 0);
368 rk_clrsetreg(&cru->cru_clksel_con[29], 0xff << 8 | 3 << 6,
369 (lcdc_div - 1) << 8 | 2 << 6);
376 static u32 rockchip_clk_gcd(u32 a, u32 b)
387 static ulong rockchip_i2s_get_clk(struct rk3288_cru *cru, uint gclk_rate)
389 unsigned long long rate;
393 val = readl(&cru->cru_clksel_con[8]);
394 n = (val & I2S0_FRAC_NUMER_MASK) >> I2S0_FRAC_NUMER_SHIFT;
395 d = (val & I2S0_FRAC_DENOM_MASK) >> I2S0_FRAC_DENOM_SHIFT;
397 rate = (unsigned long long)gclk_rate * n;
403 static ulong rockchip_i2s_set_clk(struct rk3288_cru *cru, uint gclk_rate,
409 /* set frac divider */
410 v = rockchip_clk_gcd(gclk_rate, freq);
413 assert(freq == gclk_rate / n * d);
414 writel(d << I2S0_FRAC_NUMER_SHIFT | n << I2S0_FRAC_DENOM_SHIFT,
415 &cru->cru_clksel_con[8]);
417 return rockchip_i2s_get_clk(cru, gclk_rate);
419 #endif /* CONFIG_SPL_BUILD */
421 static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
427 /* pll enter slow-mode */
428 rk_clrsetreg(&cru->cru_mode_con,
429 GPLL_MODE_MASK | CPLL_MODE_MASK,
430 GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
431 CPLL_MODE_SLOW << CPLL_MODE_SHIFT);
434 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
435 rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
437 /* waiting for pll lock */
438 while ((readl(&grf->soc_status[1]) &
439 (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) !=
440 (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
444 * pd_bus clock pll source selection and
445 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
447 aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1;
448 assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
449 hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1;
450 assert((hclk_div + 1) * PD_BUS_HCLK_HZ ==
451 PD_BUS_ACLK_HZ && (hclk_div < 0x4) && (hclk_div != 0x2));
453 pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1;
454 assert((pclk_div + 1) * PD_BUS_PCLK_HZ ==
455 PD_BUS_ACLK_HZ && pclk_div < 0x7);
457 rk_clrsetreg(&cru->cru_clksel_con[1],
458 PD_BUS_PCLK_DIV_MASK | PD_BUS_HCLK_DIV_MASK |
459 PD_BUS_ACLK_DIV0_MASK | PD_BUS_ACLK_DIV1_MASK,
460 pclk_div << PD_BUS_PCLK_DIV_SHIFT |
461 hclk_div << PD_BUS_HCLK_DIV_SHIFT |
462 aclk_div << PD_BUS_ACLK_DIV0_SHIFT |
466 * peri clock pll source selection and
467 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
469 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
470 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
472 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
473 assert((1 << hclk_div) * PERI_HCLK_HZ ==
474 PERI_ACLK_HZ && (hclk_div < 0x4));
476 pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
477 assert((1 << pclk_div) * PERI_PCLK_HZ ==
478 PERI_ACLK_HZ && (pclk_div < 0x4));
480 rk_clrsetreg(&cru->cru_clksel_con[10],
481 PERI_PCLK_DIV_MASK | PERI_HCLK_DIV_MASK |
483 PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT |
484 pclk_div << PERI_PCLK_DIV_SHIFT |
485 hclk_div << PERI_HCLK_DIV_SHIFT |
486 aclk_div << PERI_ACLK_DIV_SHIFT);
488 /* PLL enter normal-mode */
489 rk_clrsetreg(&cru->cru_mode_con,
490 GPLL_MODE_MASK | CPLL_MODE_MASK,
491 GPLL_MODE_NORMAL << GPLL_MODE_SHIFT |
492 CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
495 void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf)
497 /* pll enter slow-mode */
498 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK,
499 APLL_MODE_SLOW << APLL_MODE_SHIFT);
501 rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
503 /* waiting for pll lock */
504 while (!(readl(&grf->soc_status[1]) & SOCSTS_APLL_LOCK))
508 * core clock pll source selection and
509 * set up dependent divisors for MPAXI/M0AXI and ARM clocks.
510 * core clock select apll, apll clk = 1800MHz
511 * arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz
513 rk_clrsetreg(&cru->cru_clksel_con[0],
514 CORE_SEL_PLL_MASK | A17_DIV_MASK | MP_DIV_MASK |
521 * set up dependent divisors for L2RAM/ATCLK and PCLK clocks.
522 * l2ramclk = 900MHz, atclk = 450MHz, pclk_dbg = 450MHz
524 rk_clrsetreg(&cru->cru_clksel_con[37],
525 CLK_L2RAM_DIV_MASK | ATCLK_CORE_DIV_CON_MASK |
526 PCLK_CORE_DBG_DIV_MASK,
527 1 << CLK_L2RAM_DIV_SHIFT |
528 3 << ATCLK_CORE_DIV_CON_SHIFT |
529 3 << PCLK_CORE_DBG_DIV_SHIFT);
531 /* PLL enter normal-mode */
532 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK,
533 APLL_MODE_NORMAL << APLL_MODE_SHIFT);
536 /* Get pll rate by id */
537 static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru,
538 enum rk_clk_id clk_id)
542 int pll_id = rk_pll_id(clk_id);
543 struct rk3288_pll *pll = &cru->pll[pll_id];
544 static u8 clk_shift[CLK_COUNT] = {
545 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
546 GPLL_MODE_SHIFT, NPLL_MODE_SHIFT
550 con = readl(&cru->cru_mode_con);
551 shift = clk_shift[clk_id];
552 switch ((con >> shift) & CRU_MODE_MASK) {
555 case APLL_MODE_NORMAL:
557 con = readl(&pll->con0);
558 no = ((con & CLKOD_MASK) >> CLKOD_SHIFT) + 1;
559 nr = ((con & CLKR_MASK) >> CLKR_SHIFT) + 1;
560 con = readl(&pll->con1);
561 nf = ((con & CLKF_MASK) >> CLKF_SHIFT) + 1;
563 return (24 * nf / (nr * no)) * 1000000;
570 static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate,
580 con = readl(&cru->cru_clksel_con[12]);
581 mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
582 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
586 con = readl(&cru->cru_clksel_con[11]);
587 mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
588 div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
592 con = readl(&cru->cru_clksel_con[12]);
593 mux = (con & SDIO0_PLL_MASK) >> SDIO0_PLL_SHIFT;
594 div = (con & SDIO0_DIV_MASK) >> SDIO0_DIV_SHIFT;
600 src_rate = mux == EMMC_PLL_SELECT_24MHZ ? OSC_HZ : gclk_rate;
601 return DIV_TO_RATE(src_rate, div);
604 static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
605 int periph, uint freq)
610 debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
611 /* mmc clock default div 2 internal, need provide double in cru */
612 src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq);
614 if (src_clk_div > 0x3f) {
615 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
616 assert(src_clk_div < 0x40);
617 mux = EMMC_PLL_SELECT_24MHZ;
618 assert((int)EMMC_PLL_SELECT_24MHZ ==
619 (int)MMC0_PLL_SELECT_24MHZ);
621 mux = EMMC_PLL_SELECT_GENERAL;
622 assert((int)EMMC_PLL_SELECT_GENERAL ==
623 (int)MMC0_PLL_SELECT_GENERAL);
628 rk_clrsetreg(&cru->cru_clksel_con[12],
629 EMMC_PLL_MASK | EMMC_DIV_MASK,
630 mux << EMMC_PLL_SHIFT |
631 (src_clk_div - 1) << EMMC_DIV_SHIFT);
635 rk_clrsetreg(&cru->cru_clksel_con[11],
636 MMC0_PLL_MASK | MMC0_DIV_MASK,
637 mux << MMC0_PLL_SHIFT |
638 (src_clk_div - 1) << MMC0_DIV_SHIFT);
642 rk_clrsetreg(&cru->cru_clksel_con[12],
643 SDIO0_PLL_MASK | SDIO0_DIV_MASK,
644 mux << SDIO0_PLL_SHIFT |
645 (src_clk_div - 1) << SDIO0_DIV_SHIFT);
651 return rockchip_mmc_get_clk(cru, gclk_rate, periph);
654 static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate,
662 con = readl(&cru->cru_clksel_con[25]);
663 mux = (con & SPI0_PLL_MASK) >> SPI0_PLL_SHIFT;
664 div = (con & SPI0_DIV_MASK) >> SPI0_DIV_SHIFT;
667 con = readl(&cru->cru_clksel_con[25]);
668 mux = (con & SPI1_PLL_MASK) >> SPI1_PLL_SHIFT;
669 div = (con & SPI1_DIV_MASK) >> SPI1_DIV_SHIFT;
672 con = readl(&cru->cru_clksel_con[39]);
673 mux = (con & SPI2_PLL_MASK) >> SPI2_PLL_SHIFT;
674 div = (con & SPI2_DIV_MASK) >> SPI2_DIV_SHIFT;
679 assert(mux == SPI0_PLL_SELECT_GENERAL);
681 return DIV_TO_RATE(gclk_rate, div);
684 static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
685 int periph, uint freq)
689 debug("%s: clk_general_rate=%u\n", __func__, gclk_rate);
690 src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1;
691 assert(src_clk_div < 128);
694 rk_clrsetreg(&cru->cru_clksel_con[25],
695 SPI0_PLL_MASK | SPI0_DIV_MASK,
696 SPI0_PLL_SELECT_GENERAL << SPI0_PLL_SHIFT |
697 src_clk_div << SPI0_DIV_SHIFT);
700 rk_clrsetreg(&cru->cru_clksel_con[25],
701 SPI1_PLL_MASK | SPI1_DIV_MASK,
702 SPI1_PLL_SELECT_GENERAL << SPI1_PLL_SHIFT |
703 src_clk_div << SPI1_DIV_SHIFT);
706 rk_clrsetreg(&cru->cru_clksel_con[39],
707 SPI2_PLL_MASK | SPI2_DIV_MASK,
708 SPI2_PLL_SELECT_GENERAL << SPI2_PLL_SHIFT |
709 src_clk_div << SPI2_DIV_SHIFT);
715 return rockchip_spi_get_clk(cru, gclk_rate, periph);
718 static ulong rockchip_saradc_get_clk(struct rk3288_cru *cru)
722 val = readl(&cru->cru_clksel_con[24]);
723 div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
724 CLK_SARADC_DIV_CON_WIDTH);
726 return DIV_TO_RATE(OSC_HZ, div);
729 static ulong rockchip_saradc_set_clk(struct rk3288_cru *cru, uint hz)
733 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
734 assert(src_clk_div < 128);
736 rk_clrsetreg(&cru->cru_clksel_con[24],
737 CLK_SARADC_DIV_CON_MASK,
738 src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
740 return rockchip_saradc_get_clk(cru);
743 static ulong rk3288_clk_get_rate(struct clk *clk)
745 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
746 ulong new_rate, gclk_rate;
748 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
751 new_rate = rkclk_pll_get_rate(priv->cru, clk->id);
759 new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
764 new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, clk->id);
774 return PD_BUS_PCLK_HZ;
776 new_rate = rockchip_saradc_get_clk(priv->cru);
785 static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
787 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
788 struct rk3288_cru *cru = priv->cru;
789 ulong new_rate, gclk_rate;
791 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
794 /* We only support a fixed rate here */
795 if (rate != 1800000000)
797 rk3288_clk_configure_cpu(priv->cru, priv->grf);
801 new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate);
809 new_rate = rockchip_mmc_set_clk(cru, gclk_rate, clk->id, rate);
814 new_rate = rockchip_spi_set_clk(cru, gclk_rate, clk->id, rate);
816 #ifndef CONFIG_SPL_BUILD
818 new_rate = rockchip_i2s_set_clk(cru, gclk_rate, rate);
821 new_rate = rockchip_mac_set_clk(priv->cru, rate);
825 new_rate = rockchip_vop_set_clk(cru, priv->grf, clk->id, rate);
828 /* clk_edp_24M source: 24M */
829 rk_setreg(&cru->cru_clksel_con[28], 1 << 15);
832 rk_setreg(&cru->cru_clksel_con[6], 1 << 15);
834 rk_clrreg(&cru->cru_clksel_con[6], 1 << 15);
841 /* vop aclk source clk: cpll */
842 div = CPLL_HZ / rate;
843 assert((div - 1 < 64) && (div * rate == CPLL_HZ));
847 rk_clrsetreg(&cru->cru_clksel_con[31],
849 0 << 6 | (div - 1) << 0);
852 rk_clrsetreg(&cru->cru_clksel_con[31],
854 0 << 14 | (div - 1) << 8);
861 /* enable pclk hdmi ctrl */
862 rk_clrreg(&cru->cru_clkgate_con[16], 1 << 9);
864 /* software reset hdmi */
865 rk_setreg(&cru->cru_clkgate_con[7], 1 << 9);
867 rk_clrreg(&cru->cru_clkgate_con[7], 1 << 9);
872 new_rate = rockchip_saradc_set_clk(priv->cru, rate);
892 static int __maybe_unused rk3288_gmac_set_parent(struct clk *clk, struct clk *parent)
894 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
895 struct rk3288_cru *cru = priv->cru;
896 const char *clock_output_name;
900 * If the requested parent is in the same clock-controller and
901 * the id is SCLK_MAC_PLL ("mac_pll_src"), switch to the internal
904 if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_PLL)) {
905 debug("%s: switching GAMC to SCLK_MAC_PLL\n", __func__);
906 rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK, 0);
911 * Otherwise, we need to check the clock-output-names of the
912 * requested parent to see if the requested id is "ext_gmac".
914 ret = dev_read_string_index(parent->dev, "clock-output-names",
915 parent->id, &clock_output_name);
919 /* If this is "ext_gmac", switch to the external clock input */
920 if (!strcmp(clock_output_name, "ext_gmac")) {
921 debug("%s: switching GMAC to external clock\n", __func__);
922 rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK,
923 RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT);
930 static int __maybe_unused rk3288_clk_set_parent(struct clk *clk, struct clk *parent)
934 return rk3288_gmac_set_parent(clk, parent);
935 case SCLK_USBPHY480M_SRC:
939 debug("%s: unsupported clk %ld\n", __func__, clk->id);
943 static int rk3288_clk_enable(struct clk *clk)
954 case SCLK_MACREF_OUT:
957 /* Required to successfully probe the Designware GMAC driver */
961 debug("%s: unsupported clk %ld\n", __func__, clk->id);
965 static struct clk_ops rk3288_clk_ops = {
966 .get_rate = rk3288_clk_get_rate,
967 .set_rate = rk3288_clk_set_rate,
968 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
969 .set_parent = rk3288_clk_set_parent,
971 .enable = rk3288_clk_enable,
974 static int rk3288_clk_ofdata_to_platdata(struct udevice *dev)
976 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
977 struct rk3288_clk_priv *priv = dev_get_priv(dev);
979 priv->cru = dev_read_addr_ptr(dev);
985 static int rk3288_clk_probe(struct udevice *dev)
987 struct rk3288_clk_priv *priv = dev_get_priv(dev);
988 bool init_clocks = false;
990 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
991 if (IS_ERR(priv->grf))
992 return PTR_ERR(priv->grf);
993 #ifdef CONFIG_SPL_BUILD
994 #if CONFIG_IS_ENABLED(OF_PLATDATA)
995 struct rk3288_clk_plat *plat = dev_get_platdata(dev);
997 priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
1001 if (!(gd->flags & GD_FLG_RELOC)) {
1005 * Init clocks in U-Boot proper if the NPLL is runnning. This
1006 * indicates that a previous boot loader set up the clocks, so
1007 * we need to redo it. U-Boot's SPL does not set this clock.
1009 reg = readl(&priv->cru->cru_mode_con);
1010 if (((reg & NPLL_MODE_MASK) >> NPLL_MODE_SHIFT) ==
1016 rkclk_init(priv->cru, priv->grf);
1021 static int rk3288_clk_bind(struct udevice *dev)
1024 struct udevice *sys_child;
1025 struct sysreset_reg *priv;
1027 /* The reset driver does not have a device node, so bind it here */
1028 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
1031 debug("Warning: No sysreset driver: ret=%d\n", ret);
1033 priv = malloc(sizeof(struct sysreset_reg));
1034 priv->glb_srst_fst_value = offsetof(struct rk3288_cru,
1035 cru_glb_srst_fst_value);
1036 priv->glb_srst_snd_value = offsetof(struct rk3288_cru,
1037 cru_glb_srst_snd_value);
1038 sys_child->priv = priv;
1041 #if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
1042 ret = offsetof(struct rk3288_cru, cru_softrst_con[0]);
1043 ret = rockchip_reset_bind(dev, ret, 12);
1045 debug("Warning: software reset driver bind faile\n");
1051 static const struct udevice_id rk3288_clk_ids[] = {
1052 { .compatible = "rockchip,rk3288-cru" },
1056 U_BOOT_DRIVER(rockchip_rk3288_cru) = {
1057 .name = "rockchip_rk3288_cru",
1059 .of_match = rk3288_clk_ids,
1060 .priv_auto_alloc_size = sizeof(struct rk3288_clk_priv),
1061 .platdata_auto_alloc_size = sizeof(struct rk3288_clk_plat),
1062 .ops = &rk3288_clk_ops,
1063 .bind = rk3288_clk_bind,
1064 .ofdata_to_platdata = rk3288_clk_ofdata_to_platdata,
1065 .probe = rk3288_clk_probe,