drivers/clk/rockchip/clk_rk3288.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * (C) Copyright 2015 Google, Inc
   4  */
   5
   6 #include <common.h>
   7 #include <bitfield.h>
   8 #include <clk-uclass.h>
   9 #include <div64.h>
  10 #include <dm.h>
  11 #include <dt-structs.h>
  12 #include <errno.h>
  13 #include <log.h>
  14 #include <malloc.h>
  15 #include <mapmem.h>
  16 #include <syscon.h>
  17 #include <asm/io.h>
  18 #include <asm/arch-rockchip/clock.h>
  19 #include <asm/arch-rockchip/cru.h>
  20 #include <asm/arch-rockchip/grf_rk3288.h>
  21 #include <asm/arch-rockchip/hardware.h>
  22 #include <dt-bindings/clock/rk3288-cru.h>
  23 #include <dm/device-internal.h>
  24 #include <dm/lists.h>
  25 #include <dm/uclass-internal.h>
  26 #include <linux/bitops.h>
  27 #include <linux/delay.h>
  28 #include <linux/err.h>
  29 #include <linux/log2.h>
  30 #include <linux/stringify.h>
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 struct rk3288_clk_plat {
  35 #if CONFIG_IS_ENABLED(OF_PLATDATA)
  36         struct dtd_rockchip_rk3288_cru dtd;
  37 #endif
  38 };
  39
  40 struct pll_div {
  41         u32 nr;
  42         u32 nf;
  43         u32 no;
  44 };
  45
  46 enum {
  47         VCO_MAX_HZ      = 2200U * 1000000,
  48         VCO_MIN_HZ      = 440 * 1000000,
  49         OUTPUT_MAX_HZ   = 2200U * 1000000,
  50         OUTPUT_MIN_HZ   = 27500000,
  51         FREF_MAX_HZ     = 2200U * 1000000,
  52         FREF_MIN_HZ     = 269 * 1000,
  53 };
  54
  55 enum {
  56         /* PLL CON0 */
  57         PLL_OD_MASK             = 0x0f,
  58
  59         /* PLL CON1 */
  60         PLL_NF_MASK             = 0x1fff,
  61
  62         /* PLL CON2 */
  63         PLL_BWADJ_MASK          = 0x0fff,
  64
  65         /* PLL CON3 */
  66         PLL_RESET_SHIFT         = 5,
  67
  68         /* CLKSEL0 */
  69         CORE_SEL_PLL_SHIFT      = 15,
  70         CORE_SEL_PLL_MASK       = 1 << CORE_SEL_PLL_SHIFT,
  71         A17_DIV_SHIFT           = 8,
  72         A17_DIV_MASK            = 0x1f << A17_DIV_SHIFT,
  73         MP_DIV_SHIFT            = 4,
  74         MP_DIV_MASK             = 0xf << MP_DIV_SHIFT,
  75         M0_DIV_SHIFT            = 0,
  76         M0_DIV_MASK             = 0xf << M0_DIV_SHIFT,
  77
  78         /* CLKSEL1: pd bus clk pll sel: codec or general */
  79         PD_BUS_SEL_PLL_MASK     = 15,
  80         PD_BUS_SEL_CPLL         = 0,
  81         PD_BUS_SEL_GPLL,
  82
  83         /* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */
  84         PD_BUS_PCLK_DIV_SHIFT   = 12,
  85         PD_BUS_PCLK_DIV_MASK    = 7 << PD_BUS_PCLK_DIV_SHIFT,
  86
  87         /* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
  88         PD_BUS_HCLK_DIV_SHIFT   = 8,
  89         PD_BUS_HCLK_DIV_MASK    = 3 << PD_BUS_HCLK_DIV_SHIFT,
  90
  91         /* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */
  92         PD_BUS_ACLK_DIV0_SHIFT  = 3,
  93         PD_BUS_ACLK_DIV0_MASK   = 0x1f << PD_BUS_ACLK_DIV0_SHIFT,
  94         PD_BUS_ACLK_DIV1_SHIFT  = 0,
  95         PD_BUS_ACLK_DIV1_MASK   = 0x7 << PD_BUS_ACLK_DIV1_SHIFT,
  96
  97         /*
  98          * CLKSEL10
  99          * peripheral bus pclk div:
 100          * aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1
 101          */
 102         PERI_SEL_PLL_SHIFT       = 15,
 103         PERI_SEL_PLL_MASK        = 1 << PERI_SEL_PLL_SHIFT,
 104         PERI_SEL_CPLL           = 0,
 105         PERI_SEL_GPLL,
 106
 107         PERI_PCLK_DIV_SHIFT     = 12,
 108         PERI_PCLK_DIV_MASK      = 3 << PERI_PCLK_DIV_SHIFT,
 109
 110         /* peripheral bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
 111         PERI_HCLK_DIV_SHIFT     = 8,
 112         PERI_HCLK_DIV_MASK      = 3 << PERI_HCLK_DIV_SHIFT,
 113
 114         /*
 115          * peripheral bus aclk div:
 116          *    aclk_periph = periph_clk_src / (peri_aclk_div_con + 1)
 117          */
 118         PERI_ACLK_DIV_SHIFT     = 0,
 119         PERI_ACLK_DIV_MASK      = 0x1f << PERI_ACLK_DIV_SHIFT,
 120
 121         /*
 122          * CLKSEL24
 123          * saradc_div_con:
 124          * clk_saradc=24MHz/(saradc_div_con+1)
 125          */
 126         CLK_SARADC_DIV_CON_SHIFT        = 8,
 127         CLK_SARADC_DIV_CON_MASK         = GENMASK(15, 8),
 128         CLK_SARADC_DIV_CON_WIDTH        = 8,
 129
 130         SOCSTS_DPLL_LOCK        = 1 << 5,
 131         SOCSTS_APLL_LOCK        = 1 << 6,
 132         SOCSTS_CPLL_LOCK        = 1 << 7,
 133         SOCSTS_GPLL_LOCK        = 1 << 8,
 134         SOCSTS_NPLL_LOCK        = 1 << 9,
 135 };
 136
 137 #define DIV_TO_RATE(input_rate, div)    ((input_rate) / ((div) + 1))
 138
 139 #define PLL_DIVISORS(hz, _nr, _no) {\
 140         .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
 141         _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
 142                        (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
 143                        "divisors on line " __stringify(__LINE__));
 144
 145 /* Keep divisors as low as possible to reduce jitter and power usage */
 146 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
 147 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
 148 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
 149
 150 static int rkclk_set_pll(struct rockchip_cru *cru, enum rk_clk_id clk_id,
 151                          const struct pll_div *div)
 152 {
 153         int pll_id = rk_pll_id(clk_id);
 154         struct rk3288_pll *pll = &cru->pll[pll_id];
 155         /* All PLLs have same VCO and output frequency range restrictions. */
 156         uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
 157         uint output_hz = vco_hz / div->no;
 158
 159         debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
 160               (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz);
 161         assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
 162                output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ &&
 163                (div->no == 1 || !(div->no % 2)));
 164
 165         /* enter reset */
 166         rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
 167
 168         rk_clrsetreg(&pll->con0, CLKR_MASK | PLL_OD_MASK,
 169                      ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));
 170         rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);
 171         rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
 172
 173         udelay(10);
 174
 175         /* return from reset */
 176         rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT);
 177
 178         return 0;
 179 }
 180
 181 static int rkclk_configure_ddr(struct rockchip_cru *cru, struct rk3288_grf *grf,
 182                                unsigned int hz)
 183 {
 184         static const struct pll_div dpll_cfg[] = {
 185                 {.nf = 25, .nr = 2, .no = 1},
 186                 {.nf = 400, .nr = 9, .no = 2},
 187                 {.nf = 500, .nr = 9, .no = 2},
 188                 {.nf = 100, .nr = 3, .no = 1},
 189         };
 190         int cfg;
 191
 192         switch (hz) {
 193         case 300000000:
 194                 cfg = 0;
 195                 break;
 196         case 533000000: /* actually 533.3P MHz */
 197                 cfg = 1;
 198                 break;
 199         case 666000000: /* actually 666.6P MHz */
 200                 cfg = 2;
 201                 break;
 202         case 800000000:
 203                 cfg = 3;
 204                 break;
 205         default:
 206                 debug("Unsupported SDRAM frequency");
 207                 return -EINVAL;
 208         }
 209
 210         /* pll enter slow-mode */
 211         rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
 212                      DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
 213
 214         rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]);
 215
 216         /* wait for pll lock */
 217         while (!(readl(&grf->soc_status[1]) & SOCSTS_DPLL_LOCK))
 218                 udelay(1);
 219
 220         /* PLL enter normal-mode */
 221         rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
 222                      DPLL_MODE_NORMAL << DPLL_MODE_SHIFT);
 223
 224         return 0;
 225 }
 226
 227 #ifndef CONFIG_SPL_BUILD
 228 #define VCO_MAX_KHZ     2200000
 229 #define VCO_MIN_KHZ     440000
 230 #define FREF_MAX_KHZ    2200000
 231 #define FREF_MIN_KHZ    269
 232
 233 static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div)
 234 {
 235         uint ref_khz = OSC_HZ / 1000, nr, nf = 0;
 236         uint fref_khz;
 237         uint diff_khz, best_diff_khz;
 238         const uint max_nr = 1 << 6, max_nf = 1 << 12, max_no = 1 << 4;
 239         uint vco_khz;
 240         uint no = 1;
 241         uint freq_khz = freq_hz / 1000;
 242
 243         if (!freq_hz) {
 244                 printf("%s: the frequency can not be 0 Hz\n", __func__);
 245                 return -EINVAL;
 246         }
 247
 248         no = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
 249         if (ext_div) {
 250                 *ext_div = DIV_ROUND_UP(no, max_no);
 251                 no = DIV_ROUND_UP(no, *ext_div);
 252         }
 253
 254         /* only even divisors (and 1) are supported */
 255         if (no > 1)
 256                 no = DIV_ROUND_UP(no, 2) * 2;
 257
 258         vco_khz = freq_khz * no;
 259         if (ext_div)
 260                 vco_khz *= *ext_div;
 261
 262         if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || no > max_no) {
 263                 printf("%s: Cannot find out a supported VCO for Frequency (%luHz).\n",
 264                        __func__, freq_hz);
 265                 return -1;
 266         }
 267
 268         div->no = no;
 269
 270         best_diff_khz = vco_khz;
 271         for (nr = 1; nr < max_nr && best_diff_khz; nr++) {
 272                 fref_khz = ref_khz / nr;
 273                 if (fref_khz < FREF_MIN_KHZ)
 274                         break;
 275                 if (fref_khz > FREF_MAX_KHZ)
 276                         continue;
 277
 278                 nf = vco_khz / fref_khz;
 279                 if (nf >= max_nf)
 280                         continue;
 281                 diff_khz = vco_khz - nf * fref_khz;
 282                 if (nf + 1 < max_nf && diff_khz > fref_khz / 2) {
 283                         nf++;
 284                         diff_khz = fref_khz - diff_khz;
 285                 }
 286
 287                 if (diff_khz >= best_diff_khz)
 288                         continue;
 289
 290                 best_diff_khz = diff_khz;
 291                 div->nr = nr;
 292                 div->nf = nf;
 293         }
 294
 295         if (best_diff_khz > 4 * 1000) {
 296                 printf("%s: Failed to match output frequency %lu, difference is %u Hz, exceed 4MHZ\n",
 297                        __func__, freq_hz, best_diff_khz * 1000);
 298                 return -EINVAL;
 299         }
 300
 301         return 0;
 302 }
 303
 304 static int rockchip_mac_set_clk(struct rockchip_cru *cru, uint freq)
 305 {
 306         ulong ret;
 307
 308         /*
 309          * The gmac clock can be derived either from an external clock
 310          * or can be generated from internally by a divider from SCLK_MAC.
 311          */
 312         if (readl(&cru->cru_clksel_con[21]) & RMII_EXTCLK_MASK) {
 313                 /* An external clock will always generate the right rate... */
 314                 ret = freq;
 315         } else {
 316                 u32 con = readl(&cru->cru_clksel_con[21]);
 317                 ulong pll_rate;
 318                 u8 div;
 319
 320                 if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) ==
 321                     EMAC_PLL_SELECT_GENERAL)
 322                         pll_rate = GPLL_HZ;
 323                 else if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) ==
 324                          EMAC_PLL_SELECT_CODEC)
 325                         pll_rate = CPLL_HZ;
 326                 else
 327                         pll_rate = NPLL_HZ;
 328
 329                 div = DIV_ROUND_UP(pll_rate, freq) - 1;
 330                 if (div <= 0x1f)
 331                         rk_clrsetreg(&cru->cru_clksel_con[21], MAC_DIV_CON_MASK,
 332                                      div << MAC_DIV_CON_SHIFT);
 333                 else
 334                         debug("Unsupported div for gmac:%d\n", div);
 335
 336                 return DIV_TO_RATE(pll_rate, div);
 337         }
 338
 339         return ret;
 340 }
 341
 342 static int rockchip_vop_set_clk(struct rockchip_cru *cru, struct rk3288_grf *grf,
 343                                 int periph, unsigned int rate_hz)
 344 {
 345         struct pll_div npll_config = {0};
 346         u32 lcdc_div;
 347         int ret;
 348
 349         ret = pll_para_config(rate_hz, &npll_config, &lcdc_div);
 350         if (ret)
 351                 return ret;
 352
 353         rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK,
 354                      NPLL_MODE_SLOW << NPLL_MODE_SHIFT);
 355         rkclk_set_pll(cru, CLK_NEW, &npll_config);
 356
 357         /* waiting for pll lock */
 358         while (1) {
 359                 if (readl(&grf->soc_status[1]) & SOCSTS_NPLL_LOCK)
 360                         break;
 361                 udelay(1);
 362         }
 363
 364         rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK,
 365                      NPLL_MODE_NORMAL << NPLL_MODE_SHIFT);
 366
 367         /* vop dclk source clk: npll,dclk_div: 1 */
 368         switch (periph) {
 369         case DCLK_VOP0:
 370                 rk_clrsetreg(&cru->cru_clksel_con[27], 0xff << 8 | 3 << 0,
 371                              (lcdc_div - 1) << 8 | 2 << 0);
 372                 break;
 373         case DCLK_VOP1:
 374                 rk_clrsetreg(&cru->cru_clksel_con[29], 0xff << 8 | 3 << 6,
 375                              (lcdc_div - 1) << 8 | 2 << 6);
 376                 break;
 377         }
 378
 379         return 0;
 380 }
 381
 382 static u32 rockchip_clk_gcd(u32 a, u32 b)
 383 {
 384         while (b != 0) {
 385                 int r = b;
 386
 387                 b = a % b;
 388                 a = r;
 389         }
 390         return a;
 391 }
 392
 393 static ulong rockchip_i2s_get_clk(struct rockchip_cru *cru, uint gclk_rate)
 394 {
 395         unsigned long long rate;
 396         uint val;
 397         int n, d;
 398
 399         val = readl(&cru->cru_clksel_con[8]);
 400         n = (val & I2S0_FRAC_NUMER_MASK) >> I2S0_FRAC_NUMER_SHIFT;
 401         d = (val & I2S0_FRAC_DENOM_MASK) >> I2S0_FRAC_DENOM_SHIFT;
 402
 403         rate = (unsigned long long)gclk_rate * n;
 404         do_div(rate, d);
 405
 406         return (ulong)rate;
 407 }
 408
 409 static ulong rockchip_i2s_set_clk(struct rockchip_cru *cru, uint gclk_rate,
 410                                   uint freq)
 411 {
 412         int n, d;
 413         int v;
 414
 415         /* set frac divider */
 416         v = rockchip_clk_gcd(gclk_rate, freq);
 417         n = gclk_rate / v;
 418         d = freq / v;
 419         assert(freq == gclk_rate / n * d);
 420         writel(d << I2S0_FRAC_NUMER_SHIFT | n << I2S0_FRAC_DENOM_SHIFT,
 421                &cru->cru_clksel_con[8]);
 422
 423         return rockchip_i2s_get_clk(cru, gclk_rate);
 424 }
 425 #endif /* CONFIG_SPL_BUILD */
 426
 427 static void rkclk_init(struct rockchip_cru *cru, struct rk3288_grf *grf)
 428 {
 429         u32 aclk_div;
 430         u32 hclk_div;
 431         u32 pclk_div;
 432
 433         /* pll enter slow-mode */
 434         rk_clrsetreg(&cru->cru_mode_con,
 435                      GPLL_MODE_MASK | CPLL_MODE_MASK,
 436                      GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
 437                      CPLL_MODE_SLOW << CPLL_MODE_SHIFT);
 438
 439         /* init pll */
 440         rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
 441         rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
 442
 443         /* waiting for pll lock */
 444         while ((readl(&grf->soc_status[1]) &
 445                         (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) !=
 446                         (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
 447                 udelay(1);
 448
 449         /*
 450          * pd_bus clock pll source selection and
 451          * set up dependent divisors for PCLK/HCLK and ACLK clocks.
 452          */
 453         aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1;
 454         assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
 455         hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1;
 456         assert((hclk_div + 1) * PD_BUS_HCLK_HZ ==
 457                 PD_BUS_ACLK_HZ && (hclk_div < 0x4) && (hclk_div != 0x2));
 458
 459         pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1;
 460         assert((pclk_div + 1) * PD_BUS_PCLK_HZ ==
 461                 PD_BUS_ACLK_HZ && pclk_div < 0x7);
 462
 463         rk_clrsetreg(&cru->cru_clksel_con[1],
 464                      PD_BUS_PCLK_DIV_MASK | PD_BUS_HCLK_DIV_MASK |
 465                      PD_BUS_ACLK_DIV0_MASK | PD_BUS_ACLK_DIV1_MASK,
 466                      pclk_div << PD_BUS_PCLK_DIV_SHIFT |
 467                      hclk_div << PD_BUS_HCLK_DIV_SHIFT |
 468                      aclk_div << PD_BUS_ACLK_DIV0_SHIFT |
 469                      0 << 0);
 470
 471         /*
 472          * peri clock pll source selection and
 473          * set up dependent divisors for PCLK/HCLK and ACLK clocks.
 474          */
 475         aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
 476         assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
 477
 478         hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
 479         assert((1 << hclk_div) * PERI_HCLK_HZ ==
 480                 PERI_ACLK_HZ && (hclk_div < 0x4));
 481
 482         pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
 483         assert((1 << pclk_div) * PERI_PCLK_HZ ==
 484                 PERI_ACLK_HZ && (pclk_div < 0x4));
 485
 486         rk_clrsetreg(&cru->cru_clksel_con[10],
 487                      PERI_PCLK_DIV_MASK | PERI_HCLK_DIV_MASK |
 488                      PERI_ACLK_DIV_MASK,
 489                      PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT |
 490                      pclk_div << PERI_PCLK_DIV_SHIFT |
 491                      hclk_div << PERI_HCLK_DIV_SHIFT |
 492                      aclk_div << PERI_ACLK_DIV_SHIFT);
 493
 494         /* PLL enter normal-mode */
 495         rk_clrsetreg(&cru->cru_mode_con,
 496                      GPLL_MODE_MASK | CPLL_MODE_MASK,
 497                      GPLL_MODE_NORMAL << GPLL_MODE_SHIFT |
 498                      CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
 499 }
 500
 501 void rk3288_clk_configure_cpu(struct rockchip_cru *cru, struct rk3288_grf *grf)
 502 {
 503         /* pll enter slow-mode */
 504         rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK,
 505                      APLL_MODE_SLOW << APLL_MODE_SHIFT);
 506
 507         rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
 508
 509         /* waiting for pll lock */
 510         while (!(readl(&grf->soc_status[1]) & SOCSTS_APLL_LOCK))
 511                 udelay(1);
 512
 513         /*
 514          * core clock pll source selection and
 515          * set up dependent divisors for MPAXI/M0AXI and ARM clocks.
 516          * core clock select apll, apll clk = 1800MHz
 517          * arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz
 518          */
 519         rk_clrsetreg(&cru->cru_clksel_con[0],
 520                      CORE_SEL_PLL_MASK | A17_DIV_MASK | MP_DIV_MASK |
 521                      M0_DIV_MASK,
 522                      0 << A17_DIV_SHIFT |
 523                      3 << MP_DIV_SHIFT |
 524                      1 << M0_DIV_SHIFT);
 525
 526         /*
 527          * set up dependent divisors for L2RAM/ATCLK and PCLK clocks.
 528          * l2ramclk = 900MHz, atclk = 450MHz, pclk_dbg = 450MHz
 529          */
 530         rk_clrsetreg(&cru->cru_clksel_con[37],
 531                      CLK_L2RAM_DIV_MASK | ATCLK_CORE_DIV_CON_MASK |
 532                      PCLK_CORE_DBG_DIV_MASK,
 533                      1 << CLK_L2RAM_DIV_SHIFT |
 534                      3 << ATCLK_CORE_DIV_CON_SHIFT |
 535                      3 << PCLK_CORE_DBG_DIV_SHIFT);
 536
 537         /* PLL enter normal-mode */
 538         rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK,
 539                      APLL_MODE_NORMAL << APLL_MODE_SHIFT);
 540 }
 541
 542 /* Get pll rate by id */
 543 static uint32_t rkclk_pll_get_rate(struct rockchip_cru *cru,
 544                                    enum rk_clk_id clk_id)
 545 {
 546         uint32_t nr, no, nf;
 547         uint32_t con;
 548         int pll_id = rk_pll_id(clk_id);
 549         struct rk3288_pll *pll = &cru->pll[pll_id];
 550         static u8 clk_shift[CLK_COUNT] = {
 551                 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
 552                 GPLL_MODE_SHIFT, NPLL_MODE_SHIFT
 553         };
 554         uint shift;
 555
 556         con = readl(&cru->cru_mode_con);
 557         shift = clk_shift[clk_id];
 558         switch ((con >> shift) & CRU_MODE_MASK) {
 559         case APLL_MODE_SLOW:
 560                 return OSC_HZ;
 561         case APLL_MODE_NORMAL:
 562                 /* normal mode */
 563                 con = readl(&pll->con0);
 564                 no = ((con & CLKOD_MASK) >> CLKOD_SHIFT) + 1;
 565                 nr = ((con & CLKR_MASK) >> CLKR_SHIFT) + 1;
 566                 con = readl(&pll->con1);
 567                 nf = ((con & CLKF_MASK) >> CLKF_SHIFT) + 1;
 568
 569                 return (24 * nf / (nr * no)) * 1000000;
 570         case APLL_MODE_DEEP:
 571         default:
 572                 return 32768;
 573         }
 574 }
 575
 576 static ulong rockchip_mmc_get_clk(struct rockchip_cru *cru, uint gclk_rate,
 577                                   int periph)
 578 {
 579         uint src_rate;
 580         uint div, mux;
 581         u32 con;
 582
 583         switch (periph) {
 584         case HCLK_EMMC:
 585         case SCLK_EMMC:
 586                 con = readl(&cru->cru_clksel_con[12]);
 587                 mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
 588                 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
 589                 break;
 590         case HCLK_SDMMC:
 591         case SCLK_SDMMC:
 592                 con = readl(&cru->cru_clksel_con[11]);
 593                 mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
 594                 div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
 595                 break;
 596         case HCLK_SDIO0:
 597         case SCLK_SDIO0:
 598                 con = readl(&cru->cru_clksel_con[12]);
 599                 mux = (con & SDIO0_PLL_MASK) >> SDIO0_PLL_SHIFT;
 600                 div = (con & SDIO0_DIV_MASK) >> SDIO0_DIV_SHIFT;
 601                 break;
 602         default:
 603                 return -EINVAL;
 604         }
 605
 606         src_rate = mux == EMMC_PLL_SELECT_24MHZ ? OSC_HZ : gclk_rate;
 607         return DIV_TO_RATE(src_rate, div);
 608 }
 609
 610 static ulong rockchip_mmc_set_clk(struct rockchip_cru *cru, uint gclk_rate,
 611                                   int  periph, uint freq)
 612 {
 613         int src_clk_div;
 614         int mux;
 615
 616         debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
 617         /* mmc clock default div 2 internal, need provide double in cru */
 618         src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq);
 619
 620         if (src_clk_div > 0x3f) {
 621                 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
 622                 assert(src_clk_div < 0x40);
 623                 mux = EMMC_PLL_SELECT_24MHZ;
 624                 assert((int)EMMC_PLL_SELECT_24MHZ ==
 625                        (int)MMC0_PLL_SELECT_24MHZ);
 626         } else {
 627                 mux = EMMC_PLL_SELECT_GENERAL;
 628                 assert((int)EMMC_PLL_SELECT_GENERAL ==
 629                        (int)MMC0_PLL_SELECT_GENERAL);
 630         }
 631         switch (periph) {
 632         case HCLK_EMMC:
 633         case SCLK_EMMC:
 634                 rk_clrsetreg(&cru->cru_clksel_con[12],
 635                              EMMC_PLL_MASK | EMMC_DIV_MASK,
 636                              mux << EMMC_PLL_SHIFT |
 637                              (src_clk_div - 1) << EMMC_DIV_SHIFT);
 638                 break;
 639         case HCLK_SDMMC:
 640         case SCLK_SDMMC:
 641                 rk_clrsetreg(&cru->cru_clksel_con[11],
 642                              MMC0_PLL_MASK | MMC0_DIV_MASK,
 643                              mux << MMC0_PLL_SHIFT |
 644                              (src_clk_div - 1) << MMC0_DIV_SHIFT);
 645                 break;
 646         case HCLK_SDIO0:
 647         case SCLK_SDIO0:
 648                 rk_clrsetreg(&cru->cru_clksel_con[12],
 649                              SDIO0_PLL_MASK | SDIO0_DIV_MASK,
 650                              mux << SDIO0_PLL_SHIFT |
 651                              (src_clk_div - 1) << SDIO0_DIV_SHIFT);
 652                 break;
 653         default:
 654                 return -EINVAL;
 655         }
 656
 657         return rockchip_mmc_get_clk(cru, gclk_rate, periph);
 658 }
 659
 660 static ulong rockchip_spi_get_clk(struct rockchip_cru *cru, uint gclk_rate,
 661                                   int periph)
 662 {
 663         uint div, mux;
 664         u32 con;
 665
 666         switch (periph) {
 667         case SCLK_SPI0:
 668                 con = readl(&cru->cru_clksel_con[25]);
 669                 mux = (con & SPI0_PLL_MASK) >> SPI0_PLL_SHIFT;
 670                 div = (con & SPI0_DIV_MASK) >> SPI0_DIV_SHIFT;
 671                 break;
 672         case SCLK_SPI1:
 673                 con = readl(&cru->cru_clksel_con[25]);
 674                 mux = (con & SPI1_PLL_MASK) >> SPI1_PLL_SHIFT;
 675                 div = (con & SPI1_DIV_MASK) >> SPI1_DIV_SHIFT;
 676                 break;
 677         case SCLK_SPI2:
 678                 con = readl(&cru->cru_clksel_con[39]);
 679                 mux = (con & SPI2_PLL_MASK) >> SPI2_PLL_SHIFT;
 680                 div = (con & SPI2_DIV_MASK) >> SPI2_DIV_SHIFT;
 681                 break;
 682         default:
 683                 return -EINVAL;
 684         }
 685         assert(mux == SPI0_PLL_SELECT_GENERAL);
 686
 687         return DIV_TO_RATE(gclk_rate, div);
 688 }
 689
 690 static ulong rockchip_spi_set_clk(struct rockchip_cru *cru, uint gclk_rate,
 691                                   int periph, uint freq)
 692 {
 693         int src_clk_div;
 694
 695         debug("%s: clk_general_rate=%u\n", __func__, gclk_rate);
 696         src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1;
 697         assert(src_clk_div < 128);
 698         switch (periph) {
 699         case SCLK_SPI0:
 700                 rk_clrsetreg(&cru->cru_clksel_con[25],
 701                              SPI0_PLL_MASK | SPI0_DIV_MASK,
 702                              SPI0_PLL_SELECT_GENERAL << SPI0_PLL_SHIFT |
 703                              src_clk_div << SPI0_DIV_SHIFT);
 704                 break;
 705         case SCLK_SPI1:
 706                 rk_clrsetreg(&cru->cru_clksel_con[25],
 707                              SPI1_PLL_MASK | SPI1_DIV_MASK,
 708                              SPI1_PLL_SELECT_GENERAL << SPI1_PLL_SHIFT |
 709                              src_clk_div << SPI1_DIV_SHIFT);
 710                 break;
 711         case SCLK_SPI2:
 712                 rk_clrsetreg(&cru->cru_clksel_con[39],
 713                              SPI2_PLL_MASK | SPI2_DIV_MASK,
 714                              SPI2_PLL_SELECT_GENERAL << SPI2_PLL_SHIFT |
 715                              src_clk_div << SPI2_DIV_SHIFT);
 716                 break;
 717         default:
 718                 return -EINVAL;
 719         }
 720
 721         return rockchip_spi_get_clk(cru, gclk_rate, periph);
 722 }
 723
 724 static ulong rockchip_saradc_get_clk(struct rockchip_cru *cru)
 725 {
 726         u32 div, val;
 727
 728         val = readl(&cru->cru_clksel_con[24]);
 729         div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
 730                                CLK_SARADC_DIV_CON_WIDTH);
 731
 732         return DIV_TO_RATE(OSC_HZ, div);
 733 }
 734
 735 static ulong rockchip_saradc_set_clk(struct rockchip_cru *cru, uint hz)
 736 {
 737         int src_clk_div;
 738
 739         src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
 740         assert(src_clk_div < 128);
 741
 742         rk_clrsetreg(&cru->cru_clksel_con[24],
 743                      CLK_SARADC_DIV_CON_MASK,
 744                      src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
 745
 746         return rockchip_saradc_get_clk(cru);
 747 }
 748
 749 static ulong rk3288_clk_get_rate(struct clk *clk)
 750 {
 751         struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
 752         ulong new_rate, gclk_rate;
 753
 754         gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
 755         switch (clk->id) {
 756         case 0 ... 63:
 757                 new_rate = rkclk_pll_get_rate(priv->cru, clk->id);
 758                 break;
 759         case HCLK_EMMC:
 760         case HCLK_SDMMC:
 761         case HCLK_SDIO0:
 762         case SCLK_EMMC:
 763         case SCLK_SDMMC:
 764         case SCLK_SDIO0:
 765                 new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
 766                 break;
 767         case SCLK_SPI0:
 768         case SCLK_SPI1:
 769         case SCLK_SPI2:
 770                 new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, clk->id);
 771                 break;
 772         case PCLK_I2C0:
 773         case PCLK_I2C1:
 774         case PCLK_I2C2:
 775         case PCLK_I2C3:
 776         case PCLK_I2C4:
 777         case PCLK_I2C5:
 778                 return gclk_rate;
 779         case PCLK_PWM:
 780                 return PD_BUS_PCLK_HZ;
 781         case SCLK_SARADC:
 782                 new_rate = rockchip_saradc_get_clk(priv->cru);
 783                 break;
 784         default:
 785                 return -ENOENT;
 786         }
 787
 788         return new_rate;
 789 }
 790
 791 static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
 792 {
 793         struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
 794         struct rockchip_cru *cru = priv->cru;
 795         ulong new_rate, gclk_rate;
 796
 797         gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
 798         switch (clk->id) {
 799         case PLL_APLL:
 800                 /* We only support a fixed rate here */
 801                 if (rate != 1800000000)
 802                         return -EINVAL;
 803                 rk3288_clk_configure_cpu(priv->cru, priv->grf);
 804                 new_rate = rate;
 805                 break;
 806         case CLK_DDR:
 807                 new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate);
 808                 break;
 809         case HCLK_EMMC:
 810         case HCLK_SDMMC:
 811         case HCLK_SDIO0:
 812         case SCLK_EMMC:
 813         case SCLK_SDMMC:
 814         case SCLK_SDIO0:
 815                 new_rate = rockchip_mmc_set_clk(cru, gclk_rate, clk->id, rate);
 816                 break;
 817         case SCLK_SPI0:
 818         case SCLK_SPI1:
 819         case SCLK_SPI2:
 820                 new_rate = rockchip_spi_set_clk(cru, gclk_rate, clk->id, rate);
 821                 break;
 822 #ifndef CONFIG_SPL_BUILD
 823         case SCLK_I2S0:
 824                 new_rate = rockchip_i2s_set_clk(cru, gclk_rate, rate);
 825                 break;
 826         case SCLK_MAC:
 827                 new_rate = rockchip_mac_set_clk(priv->cru, rate);
 828                 break;
 829         case DCLK_VOP0:
 830         case DCLK_VOP1:
 831                 new_rate = rockchip_vop_set_clk(cru, priv->grf, clk->id, rate);
 832                 break;
 833         case SCLK_EDP_24M:
 834                 /* clk_edp_24M source: 24M */
 835                 rk_setreg(&cru->cru_clksel_con[28], 1 << 15);
 836
 837                 /* rst edp */
 838                 rk_setreg(&cru->cru_clksel_con[6], 1 << 15);
 839                 udelay(1);
 840                 rk_clrreg(&cru->cru_clksel_con[6], 1 << 15);
 841                 new_rate = rate;
 842                 break;
 843         case ACLK_VOP0:
 844         case ACLK_VOP1: {
 845                 u32 div;
 846
 847                 /* vop aclk source clk: cpll */
 848                 div = CPLL_HZ / rate;
 849                 assert((div - 1 < 64) && (div * rate == CPLL_HZ));
 850
 851                 switch (clk->id) {
 852                 case ACLK_VOP0:
 853                         rk_clrsetreg(&cru->cru_clksel_con[31],
 854                                      3 << 6 | 0x1f << 0,
 855                                      0 << 6 | (div - 1) << 0);
 856                         break;
 857                 case ACLK_VOP1:
 858                         rk_clrsetreg(&cru->cru_clksel_con[31],
 859                                      3 << 14 | 0x1f << 8,
 860                                      0 << 14 | (div - 1) << 8);
 861                         break;
 862                 }
 863                 new_rate = rate;
 864                 break;
 865         }
 866         case PCLK_HDMI_CTRL:
 867                 /* enable pclk hdmi ctrl */
 868                 rk_clrreg(&cru->cru_clkgate_con[16], 1 << 9);
 869
 870                 /* software reset hdmi */
 871                 rk_setreg(&cru->cru_clkgate_con[7], 1 << 9);
 872                 udelay(1);
 873                 rk_clrreg(&cru->cru_clkgate_con[7], 1 << 9);
 874                 new_rate = rate;
 875                 break;
 876 #endif
 877         case SCLK_SARADC:
 878                 new_rate = rockchip_saradc_set_clk(priv->cru, rate);
 879                 break;
 880         case PLL_GPLL:
 881         case PLL_CPLL:
 882         case PLL_NPLL:
 883         case ACLK_CPU:
 884         case HCLK_CPU:
 885         case PCLK_CPU:
 886         case ACLK_PERI:
 887         case HCLK_PERI:
 888         case PCLK_PERI:
 889         case SCLK_UART0:
 890                 return 0;
 891         default:
 892                 return -ENOENT;
 893         }
 894
 895         return new_rate;
 896 }
 897
 898 static int __maybe_unused rk3288_gmac_set_parent(struct clk *clk, struct clk *parent)
 899 {
 900         struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
 901         struct rockchip_cru *cru = priv->cru;
 902         const char *clock_output_name;
 903         int ret;
 904
 905         /*
 906          * If the requested parent is in the same clock-controller and
 907          * the id is SCLK_MAC_PLL ("mac_pll_src"), switch to the internal
 908          * clock.
 909          */
 910         if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_PLL)) {
 911                 debug("%s: switching GAMC to SCLK_MAC_PLL\n", __func__);
 912                 rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK, 0);
 913                 return 0;
 914         }
 915
 916         /*
 917          * Otherwise, we need to check the clock-output-names of the
 918          * requested parent to see if the requested id is "ext_gmac".
 919          */
 920         ret = dev_read_string_index(parent->dev, "clock-output-names",
 921                                     parent->id, &clock_output_name);
 922         if (ret < 0)
 923                 return -ENODATA;
 924
 925         /* If this is "ext_gmac", switch to the external clock input */
 926         if (!strcmp(clock_output_name, "ext_gmac")) {
 927                 debug("%s: switching GMAC to external clock\n", __func__);
 928                 rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK,
 929                              RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT);
 930                 return 0;
 931         }
 932
 933         return -EINVAL;
 934 }
 935
 936 static int __maybe_unused rk3288_clk_set_parent(struct clk *clk, struct clk *parent)
 937 {
 938         switch (clk->id) {
 939         case SCLK_MAC:
 940                 return rk3288_gmac_set_parent(clk, parent);
 941         case SCLK_USBPHY480M_SRC:
 942                 return 0;
 943         }
 944
 945         debug("%s: unsupported clk %ld\n", __func__, clk->id);
 946         return -ENOENT;
 947 }
 948
 949 static struct clk_ops rk3288_clk_ops = {
 950         .get_rate       = rk3288_clk_get_rate,
 951         .set_rate       = rk3288_clk_set_rate,
 952 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
 953         .set_parent     = rk3288_clk_set_parent,
 954 #endif
 955 };
 956
 957 static int rk3288_clk_ofdata_to_platdata(struct udevice *dev)
 958 {
 959 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 960         struct rk3288_clk_priv *priv = dev_get_priv(dev);
 961
 962         priv->cru = dev_read_addr_ptr(dev);
 963 #endif
 964
 965         return 0;
 966 }
 967
 968 static int rk3288_clk_probe(struct udevice *dev)
 969 {
 970         struct rk3288_clk_priv *priv = dev_get_priv(dev);
 971         bool init_clocks = false;
 972
 973         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 974         if (IS_ERR(priv->grf))
 975                 return PTR_ERR(priv->grf);
 976 #ifdef CONFIG_SPL_BUILD
 977 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 978         struct rk3288_clk_plat *plat = dev_get_platdata(dev);
 979
 980         priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
 981 #endif
 982         init_clocks = true;
 983 #endif
 984         if (!(gd->flags & GD_FLG_RELOC)) {
 985                 u32 reg;
 986
 987                 /*
 988                  * Init clocks in U-Boot proper if the NPLL is runnning. This
 989                  * indicates that a previous boot loader set up the clocks, so
 990                  * we need to redo it. U-Boot's SPL does not set this clock.
 991                  */
 992                 reg = readl(&priv->cru->cru_mode_con);
 993                 if (((reg & NPLL_MODE_MASK) >> NPLL_MODE_SHIFT) ==
 994                                 NPLL_MODE_NORMAL)
 995                         init_clocks = true;
 996         }
 997
 998         if (init_clocks)
 999                 rkclk_init(priv->cru, priv->grf);
1000
1001         return 0;
1002 }
1003
1004 static int rk3288_clk_bind(struct udevice *dev)
1005 {
1006         int ret;
1007         struct udevice *sys_child;
1008         struct sysreset_reg *priv;
1009
1010         /* The reset driver does not have a device node, so bind it here */
1011         ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
1012                                  &sys_child);
1013         if (ret) {
1014                 debug("Warning: No sysreset driver: ret=%d\n", ret);
1015         } else {
1016                 priv = malloc(sizeof(struct sysreset_reg));
1017                 priv->glb_srst_fst_value = offsetof(struct rockchip_cru,
1018                                                     cru_glb_srst_fst_value);
1019                 priv->glb_srst_snd_value = offsetof(struct rockchip_cru,
1020                                                     cru_glb_srst_snd_value);
1021                 sys_child->priv = priv;
1022         }
1023
1024 #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
1025         ret = offsetof(struct rockchip_cru, cru_softrst_con[0]);
1026         ret = rockchip_reset_bind(dev, ret, 12);
1027         if (ret)
1028                 debug("Warning: software reset driver bind faile\n");
1029 #endif
1030
1031         return 0;
1032 }
1033
1034 static const struct udevice_id rk3288_clk_ids[] = {
1035         { .compatible = "rockchip,rk3288-cru" },
1036         { }
1037 };
1038
1039 U_BOOT_DRIVER(rockchip_rk3288_cru) = {
1040         .name           = "rockchip_rk3288_cru",
1041         .id             = UCLASS_CLK,
1042         .of_match       = rk3288_clk_ids,
1043         .priv_auto_alloc_size = sizeof(struct rk3288_clk_priv),
1044         .platdata_auto_alloc_size = sizeof(struct rk3288_clk_plat),
1045         .ops            = &rk3288_clk_ops,
1046         .bind           = rk3288_clk_bind,
1047         .ofdata_to_platdata     = rk3288_clk_ofdata_to_platdata,
1048         .probe          = rk3288_clk_probe,
1049 };