1 // SPDX-License-Identifier: GPL-2.0
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
8 #include <clk-uclass.h>
12 #include <asm/arch-rockchip/clock.h>
13 #include <asm/arch-rockchip/cru_px30.h>
14 #include <asm/arch-rockchip/hardware.h>
17 #include <dt-bindings/clock/px30-cru.h>
19 DECLARE_GLOBAL_DATA_PTR;
22 VCO_MAX_HZ = 3200U * 1000000,
23 VCO_MIN_HZ = 800 * 1000000,
24 OUTPUT_MAX_HZ = 3200U * 1000000,
25 OUTPUT_MIN_HZ = 24 * 1000000,
28 #define PX30_VOP_PLL_LIMIT 600000000
30 #define PX30_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \
31 _postdiv2, _dsmpd, _frac) \
35 .postdiv1 = _postdiv1, \
37 .postdiv2 = _postdiv2, \
42 #define PX30_CPUCLK_RATE(_rate, _aclk_div, _pclk_div) \
45 .aclk_div = _aclk_div, \
46 .pclk_div = _pclk_div, \
49 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
51 #define PX30_CLK_DUMP(_id, _name, _iscru) \
58 static struct pll_rate_table px30_pll_rates[] = {
59 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
60 PX30_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
61 PX30_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
62 PX30_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
63 PX30_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
64 PX30_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
65 PX30_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
66 PX30_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0),
69 static struct cpu_rate_table px30_cpu_rates[] = {
70 PX30_CPUCLK_RATE(1200000000, 1, 5),
71 PX30_CPUCLK_RATE(1008000000, 1, 5),
72 PX30_CPUCLK_RATE(816000000, 1, 3),
73 PX30_CPUCLK_RATE(600000000, 1, 3),
74 PX30_CPUCLK_RATE(408000000, 1, 1),
77 static u8 pll_mode_shift[PLL_COUNT] = {
78 APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
79 NPLL_MODE_SHIFT, GPLL_MODE_SHIFT
82 static u32 pll_mode_mask[PLL_COUNT] = {
83 APLL_MODE_MASK, DPLL_MODE_MASK, CPLL_MODE_MASK,
84 NPLL_MODE_MASK, GPLL_MODE_MASK
87 static struct pll_rate_table auto_table;
89 static ulong px30_clk_get_pll_rate(struct px30_clk_priv *priv,
90 enum px30_pll_id pll_id);
92 static struct pll_rate_table *pll_clk_set_by_auto(u32 drate)
94 struct pll_rate_table *rate = &auto_table;
95 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0;
96 u32 postdiv1, postdiv2 = 1;
98 u32 diff_khz, best_diff_khz;
99 const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16;
100 const u32 max_postdiv1 = 7, max_postdiv2 = 7;
102 u32 rate_khz = drate / KHz;
105 printf("%s: the frequency can't be 0 Hz\n", __func__);
109 postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, rate_khz);
110 if (postdiv1 > max_postdiv1) {
111 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1);
112 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2);
115 vco_khz = rate_khz * postdiv1 * postdiv2;
117 if (vco_khz < (VCO_MIN_HZ / KHz) || vco_khz > (VCO_MAX_HZ / KHz) ||
118 postdiv2 > max_postdiv2) {
119 printf("%s: Cannot find out a supported VCO for Freq (%uHz)\n",
124 rate->postdiv1 = postdiv1;
125 rate->postdiv2 = postdiv2;
127 best_diff_khz = vco_khz;
128 for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) {
129 fref_khz = ref_khz / refdiv;
131 fbdiv = vco_khz / fref_khz;
132 if (fbdiv >= max_fbdiv || fbdiv <= min_fbdiv)
135 diff_khz = vco_khz - fbdiv * fref_khz;
136 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) {
138 diff_khz = fref_khz - diff_khz;
141 if (diff_khz >= best_diff_khz)
144 best_diff_khz = diff_khz;
145 rate->refdiv = refdiv;
149 if (best_diff_khz > 4 * (MHz / KHz)) {
150 printf("%s: Failed to match output frequency %u bestis %u Hz\n",
152 best_diff_khz * KHz);
159 static const struct pll_rate_table *get_pll_settings(unsigned long rate)
161 unsigned int rate_count = ARRAY_SIZE(px30_pll_rates);
164 for (i = 0; i < rate_count; i++) {
165 if (rate == px30_pll_rates[i].rate)
166 return &px30_pll_rates[i];
169 return pll_clk_set_by_auto(rate);
172 static const struct cpu_rate_table *get_cpu_settings(unsigned long rate)
174 unsigned int rate_count = ARRAY_SIZE(px30_cpu_rates);
177 for (i = 0; i < rate_count; i++) {
178 if (rate == px30_cpu_rates[i].rate)
179 return &px30_cpu_rates[i];
186 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63):
187 * Formulas also embedded within the Fractional PLL Verilog model:
188 * If DSMPD = 1 (DSM is disabled, "integer mode")
189 * FOUTVCO = FREF / REFDIV * FBDIV
190 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
192 * FOUTVCO = Fractional PLL non-divided output frequency
193 * FOUTPOSTDIV = Fractional PLL divided output frequency
194 * (output of second post divider)
195 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
196 * REFDIV = Fractional PLL input reference clock divider
197 * FBDIV = Integer value programmed into feedback divide
200 static int rkclk_set_pll(struct px30_pll *pll, unsigned int *mode,
201 enum px30_pll_id pll_id,
204 const struct pll_rate_table *rate;
205 uint vco_hz, output_hz;
207 rate = get_pll_settings(drate);
209 printf("%s unsupport rate\n", __func__);
213 /* All PLLs have same VCO and output frequency range restrictions. */
214 vco_hz = OSC_HZ / 1000 * rate->fbdiv / rate->refdiv * 1000;
215 output_hz = vco_hz / rate->postdiv1 / rate->postdiv2;
217 debug("PLL at %p: fb=%d, ref=%d, pst1=%d, pst2=%d, vco=%u Hz, output=%u Hz\n",
218 pll, rate->fbdiv, rate->refdiv, rate->postdiv1,
219 rate->postdiv2, vco_hz, output_hz);
220 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
221 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
224 * When power on or changing PLL setting,
225 * we must force PLL into slow mode to ensure output stable clock.
227 rk_clrsetreg(mode, pll_mode_mask[pll_id],
228 PLLMUX_FROM_XIN24M << pll_mode_shift[pll_id]);
230 /* use integer mode */
231 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
233 rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT);
235 rk_clrsetreg(&pll->con0,
236 PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
237 (rate->postdiv1 << PLL_POSTDIV1_SHIFT) | rate->fbdiv);
238 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
239 (rate->postdiv2 << PLL_POSTDIV2_SHIFT |
240 rate->refdiv << PLL_REFDIV_SHIFT));
243 rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT);
245 /* waiting for pll lock */
246 while (!(readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)))
249 rk_clrsetreg(mode, pll_mode_mask[pll_id],
250 PLLMUX_FROM_PLL << pll_mode_shift[pll_id]);
255 static uint32_t rkclk_pll_get_rate(struct px30_pll *pll, unsigned int *mode,
256 enum px30_pll_id pll_id)
258 u32 refdiv, fbdiv, postdiv1, postdiv2;
259 u32 con, shift, mask;
262 shift = pll_mode_shift[pll_id];
263 mask = pll_mode_mask[pll_id];
265 switch ((con & mask) >> shift) {
266 case PLLMUX_FROM_XIN24M:
268 case PLLMUX_FROM_PLL:
270 con = readl(&pll->con0);
271 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT;
272 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT;
273 con = readl(&pll->con1);
274 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT;
275 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT;
276 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
277 case PLLMUX_FROM_RTC32K:
283 static ulong px30_i2c_get_clk(struct px30_clk_priv *priv, ulong clk_id)
285 struct px30_cru *cru = priv->cru;
290 con = readl(&cru->clksel_con[49]);
291 div = con >> CLK_I2C0_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
294 con = readl(&cru->clksel_con[49]);
295 div = con >> CLK_I2C1_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
298 con = readl(&cru->clksel_con[50]);
299 div = con >> CLK_I2C2_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
302 con = readl(&cru->clksel_con[50]);
303 div = con >> CLK_I2C3_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
306 printf("do not support this i2c bus\n");
310 return DIV_TO_RATE(priv->gpll_hz, div);
313 static ulong px30_i2c_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz)
315 struct px30_cru *cru = priv->cru;
318 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);
319 assert(src_clk_div - 1 <= 127);
323 rk_clrsetreg(&cru->clksel_con[49],
324 CLK_I2C_DIV_CON_MASK << CLK_I2C0_DIV_CON_SHIFT |
325 CLK_I2C_PLL_SEL_MASK << CLK_I2C0_PLL_SEL_SHIFT,
326 (src_clk_div - 1) << CLK_I2C0_DIV_CON_SHIFT |
327 CLK_I2C_PLL_SEL_GPLL << CLK_I2C0_PLL_SEL_SHIFT);
330 rk_clrsetreg(&cru->clksel_con[49],
331 CLK_I2C_DIV_CON_MASK << CLK_I2C1_DIV_CON_SHIFT |
332 CLK_I2C_PLL_SEL_MASK << CLK_I2C1_PLL_SEL_SHIFT,
333 (src_clk_div - 1) << CLK_I2C1_DIV_CON_SHIFT |
334 CLK_I2C_PLL_SEL_GPLL << CLK_I2C1_PLL_SEL_SHIFT);
337 rk_clrsetreg(&cru->clksel_con[50],
338 CLK_I2C_DIV_CON_MASK << CLK_I2C2_DIV_CON_SHIFT |
339 CLK_I2C_PLL_SEL_MASK << CLK_I2C2_PLL_SEL_SHIFT,
340 (src_clk_div - 1) << CLK_I2C2_DIV_CON_SHIFT |
341 CLK_I2C_PLL_SEL_GPLL << CLK_I2C2_PLL_SEL_SHIFT);
344 rk_clrsetreg(&cru->clksel_con[50],
345 CLK_I2C_DIV_CON_MASK << CLK_I2C3_DIV_CON_SHIFT |
346 CLK_I2C_PLL_SEL_MASK << CLK_I2C3_PLL_SEL_SHIFT,
347 (src_clk_div - 1) << CLK_I2C3_DIV_CON_SHIFT |
348 CLK_I2C_PLL_SEL_GPLL << CLK_I2C3_PLL_SEL_SHIFT);
351 printf("do not support this i2c bus\n");
355 return px30_i2c_get_clk(priv, clk_id);
359 * calculate best rational approximation for a given fraction
360 * taking into account restricted register size, e.g. to find
361 * appropriate values for a pll with 5 bit denominator and
362 * 8 bit numerator register fields, trying to set up with a
363 * frequency ratio of 3.1415, one would say:
365 * rational_best_approximation(31415, 10000,
366 * (1 << 8) - 1, (1 << 5) - 1, &n, &d);
368 * you may look at given_numerator as a fixed point number,
369 * with the fractional part size described in given_denominator.
371 * for theoretical background, see:
372 * http://en.wikipedia.org/wiki/Continued_fraction
374 static void rational_best_approximation(unsigned long given_numerator,
375 unsigned long given_denominator,
376 unsigned long max_numerator,
377 unsigned long max_denominator,
378 unsigned long *best_numerator,
379 unsigned long *best_denominator)
381 unsigned long n, d, n0, d0, n1, d1;
384 d = given_denominator;
392 if (n1 > max_numerator || d1 > max_denominator) {
410 *best_numerator = n1;
411 *best_denominator = d1;
414 static ulong px30_i2s_get_clk(struct px30_clk_priv *priv, ulong clk_id)
416 u32 con, fracdiv, gate;
417 u32 clk_src = priv->gpll_hz / 2;
419 struct px30_cru *cru = priv->cru;
423 con = readl(&cru->clksel_con[30]);
424 fracdiv = readl(&cru->clksel_con[31]);
425 gate = readl(&cru->clkgate_con[10]);
426 m = fracdiv & CLK_I2S1_FRAC_NUMERATOR_MASK;
427 m >>= CLK_I2S1_FRAC_NUMERATOR_SHIFT;
428 n = fracdiv & CLK_I2S1_FRAC_DENOMINATOR_MASK;
429 n >>= CLK_I2S1_FRAC_DENOMINATOR_SHIFT;
430 debug("con30: 0x%x, gate: 0x%x, frac: 0x%x\n",
434 printf("do not support this i2s bus\n");
438 return clk_src * n / m;
441 static ulong px30_i2s_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz)
444 unsigned long m, n, val;
445 struct px30_cru *cru = priv->cru;
447 clk_src = priv->gpll_hz / 2;
448 rational_best_approximation(hz, clk_src,
454 rk_clrsetreg(&cru->clksel_con[30],
455 CLK_I2S1_PLL_SEL_MASK, CLK_I2S1_PLL_SEL_GPLL);
456 rk_clrsetreg(&cru->clksel_con[30],
457 CLK_I2S1_DIV_CON_MASK, 0x1);
458 rk_clrsetreg(&cru->clksel_con[30],
459 CLK_I2S1_SEL_MASK, CLK_I2S1_SEL_FRAC);
460 val = m << CLK_I2S1_FRAC_NUMERATOR_SHIFT | n;
461 writel(val, &cru->clksel_con[31]);
462 rk_clrsetreg(&cru->clkgate_con[10],
463 CLK_I2S1_OUT_MCLK_PAD_MASK,
464 CLK_I2S1_OUT_MCLK_PAD_ENABLE);
467 printf("do not support this i2s bus\n");
471 return px30_i2s_get_clk(priv, clk_id);
474 static ulong px30_nandc_get_clk(struct px30_clk_priv *priv)
476 struct px30_cru *cru = priv->cru;
479 con = readl(&cru->clksel_con[15]);
480 div = (con & NANDC_DIV_MASK) >> NANDC_DIV_SHIFT;
482 return DIV_TO_RATE(priv->gpll_hz, div);
485 static ulong px30_nandc_set_clk(struct px30_clk_priv *priv,
488 struct px30_cru *cru = priv->cru;
491 /* Select nandc source from GPLL by default */
492 /* nandc clock defaulg div 2 internal, need provide double in cru */
493 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, set_rate);
494 assert(src_clk_div - 1 <= 31);
496 rk_clrsetreg(&cru->clksel_con[15],
497 NANDC_CLK_SEL_MASK | NANDC_PLL_MASK |
499 NANDC_CLK_SEL_NANDC << NANDC_CLK_SEL_SHIFT |
500 NANDC_SEL_GPLL << NANDC_PLL_SHIFT |
501 (src_clk_div - 1) << NANDC_DIV_SHIFT);
503 return px30_nandc_get_clk(priv);
506 static ulong px30_mmc_get_clk(struct px30_clk_priv *priv, uint clk_id)
508 struct px30_cru *cru = priv->cru;
509 u32 div, con, con_id;
518 case SCLK_EMMC_SAMPLE:
525 con = readl(&cru->clksel_con[con_id]);
526 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
528 if ((con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT
530 return DIV_TO_RATE(OSC_HZ, div) / 2;
532 return DIV_TO_RATE(priv->gpll_hz, div) / 2;
535 static ulong px30_mmc_set_clk(struct px30_clk_priv *priv,
536 ulong clk_id, ulong set_rate)
538 struct px30_cru *cru = priv->cru;
555 /* Select clk_sdmmc/emmc source from GPLL by default */
556 /* mmc clock defaulg div 2 internal, need provide double in cru */
557 src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, set_rate);
559 if (src_clk_div > 127) {
560 /* use 24MHz source for 400KHz clock */
561 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate);
562 rk_clrsetreg(&cru->clksel_con[con_id],
563 EMMC_PLL_MASK | EMMC_DIV_MASK,
564 EMMC_SEL_24M << EMMC_PLL_SHIFT |
565 (src_clk_div - 1) << EMMC_DIV_SHIFT);
567 rk_clrsetreg(&cru->clksel_con[con_id],
568 EMMC_PLL_MASK | EMMC_DIV_MASK,
569 EMMC_SEL_GPLL << EMMC_PLL_SHIFT |
570 (src_clk_div - 1) << EMMC_DIV_SHIFT);
572 rk_clrsetreg(&cru->clksel_con[con_id + 1], EMMC_CLK_SEL_MASK,
575 return px30_mmc_get_clk(priv, clk_id);
578 static ulong px30_pwm_get_clk(struct px30_clk_priv *priv, ulong clk_id)
580 struct px30_cru *cru = priv->cru;
585 con = readl(&cru->clksel_con[52]);
586 div = con >> CLK_PWM0_DIV_CON_SHIFT & CLK_PWM_DIV_CON_MASK;
589 con = readl(&cru->clksel_con[52]);
590 div = con >> CLK_PWM1_DIV_CON_SHIFT & CLK_PWM_DIV_CON_MASK;
593 printf("do not support this pwm bus\n");
597 return DIV_TO_RATE(priv->gpll_hz, div);
600 static ulong px30_pwm_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz)
602 struct px30_cru *cru = priv->cru;
605 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);
606 assert(src_clk_div - 1 <= 127);
610 rk_clrsetreg(&cru->clksel_con[52],
611 CLK_PWM_DIV_CON_MASK << CLK_PWM0_DIV_CON_SHIFT |
612 CLK_PWM_PLL_SEL_MASK << CLK_PWM0_PLL_SEL_SHIFT,
613 (src_clk_div - 1) << CLK_PWM0_DIV_CON_SHIFT |
614 CLK_PWM_PLL_SEL_GPLL << CLK_PWM0_PLL_SEL_SHIFT);
617 rk_clrsetreg(&cru->clksel_con[52],
618 CLK_PWM_DIV_CON_MASK << CLK_PWM1_DIV_CON_SHIFT |
619 CLK_PWM_PLL_SEL_MASK << CLK_PWM1_PLL_SEL_SHIFT,
620 (src_clk_div - 1) << CLK_PWM1_DIV_CON_SHIFT |
621 CLK_PWM_PLL_SEL_GPLL << CLK_PWM1_PLL_SEL_SHIFT);
624 printf("do not support this pwm bus\n");
628 return px30_pwm_get_clk(priv, clk_id);
631 static ulong px30_saradc_get_clk(struct px30_clk_priv *priv)
633 struct px30_cru *cru = priv->cru;
636 con = readl(&cru->clksel_con[55]);
637 div = con >> CLK_SARADC_DIV_CON_SHIFT & CLK_SARADC_DIV_CON_MASK;
639 return DIV_TO_RATE(OSC_HZ, div);
642 static ulong px30_saradc_set_clk(struct px30_clk_priv *priv, uint hz)
644 struct px30_cru *cru = priv->cru;
647 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz);
648 assert(src_clk_div - 1 <= 2047);
650 rk_clrsetreg(&cru->clksel_con[55],
651 CLK_SARADC_DIV_CON_MASK,
652 (src_clk_div - 1) << CLK_SARADC_DIV_CON_SHIFT);
654 return px30_saradc_get_clk(priv);
657 static ulong px30_tsadc_get_clk(struct px30_clk_priv *priv)
659 struct px30_cru *cru = priv->cru;
662 con = readl(&cru->clksel_con[54]);
663 div = con >> CLK_SARADC_DIV_CON_SHIFT & CLK_SARADC_DIV_CON_MASK;
665 return DIV_TO_RATE(OSC_HZ, div);
668 static ulong px30_tsadc_set_clk(struct px30_clk_priv *priv, uint hz)
670 struct px30_cru *cru = priv->cru;
673 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz);
674 assert(src_clk_div - 1 <= 2047);
676 rk_clrsetreg(&cru->clksel_con[54],
677 CLK_SARADC_DIV_CON_MASK,
678 (src_clk_div - 1) << CLK_SARADC_DIV_CON_SHIFT);
680 return px30_tsadc_get_clk(priv);
683 static ulong px30_spi_get_clk(struct px30_clk_priv *priv, ulong clk_id)
685 struct px30_cru *cru = priv->cru;
690 con = readl(&cru->clksel_con[53]);
691 div = con >> CLK_SPI0_DIV_CON_SHIFT & CLK_SPI_DIV_CON_MASK;
694 con = readl(&cru->clksel_con[53]);
695 div = con >> CLK_SPI1_DIV_CON_SHIFT & CLK_SPI_DIV_CON_MASK;
698 printf("do not support this pwm bus\n");
702 return DIV_TO_RATE(priv->gpll_hz, div);
705 static ulong px30_spi_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz)
707 struct px30_cru *cru = priv->cru;
710 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);
711 assert(src_clk_div - 1 <= 127);
715 rk_clrsetreg(&cru->clksel_con[53],
716 CLK_SPI_DIV_CON_MASK << CLK_SPI0_DIV_CON_SHIFT |
717 CLK_SPI_PLL_SEL_MASK << CLK_SPI0_PLL_SEL_SHIFT,
718 (src_clk_div - 1) << CLK_SPI0_DIV_CON_SHIFT |
719 CLK_SPI_PLL_SEL_GPLL << CLK_SPI0_PLL_SEL_SHIFT);
722 rk_clrsetreg(&cru->clksel_con[53],
723 CLK_SPI_DIV_CON_MASK << CLK_SPI1_DIV_CON_SHIFT |
724 CLK_SPI_PLL_SEL_MASK << CLK_SPI1_PLL_SEL_SHIFT,
725 (src_clk_div - 1) << CLK_SPI1_DIV_CON_SHIFT |
726 CLK_SPI_PLL_SEL_GPLL << CLK_SPI1_PLL_SEL_SHIFT);
729 printf("do not support this pwm bus\n");
733 return px30_spi_get_clk(priv, clk_id);
736 static ulong px30_vop_get_clk(struct px30_clk_priv *priv, ulong clk_id)
738 struct px30_cru *cru = priv->cru;
739 u32 div, con, parent;
744 con = readl(&cru->clksel_con[3]);
745 div = con & ACLK_VO_DIV_MASK;
746 parent = priv->gpll_hz;
749 con = readl(&cru->clksel_con[5]);
750 div = con & DCLK_VOPB_DIV_MASK;
751 parent = rkclk_pll_get_rate(&cru->pll[CPLL], &cru->mode, CPLL);
754 con = readl(&cru->clksel_con[8]);
755 div = con & DCLK_VOPL_DIV_MASK;
756 parent = rkclk_pll_get_rate(&cru->pll[NPLL], &cru->mode, NPLL);
762 return DIV_TO_RATE(parent, div);
765 static ulong px30_vop_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz)
767 struct px30_cru *cru = priv->cru;
774 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);
775 assert(src_clk_div - 1 <= 31);
776 rk_clrsetreg(&cru->clksel_con[3],
777 ACLK_VO_PLL_MASK | ACLK_VO_DIV_MASK,
778 ACLK_VO_SEL_GPLL << ACLK_VO_PLL_SHIFT |
779 (src_clk_div - 1) << ACLK_VO_DIV_SHIFT);
782 if (hz < PX30_VOP_PLL_LIMIT) {
783 src_clk_div = DIV_ROUND_UP(PX30_VOP_PLL_LIMIT, hz);
785 src_clk_div = src_clk_div - 1;
789 assert(src_clk_div - 1 <= 255);
790 rkclk_set_pll(&cru->pll[CPLL], &cru->mode,
791 CPLL, hz * src_clk_div);
792 rk_clrsetreg(&cru->clksel_con[5],
793 DCLK_VOPB_SEL_MASK | DCLK_VOPB_PLL_SEL_MASK |
795 DCLK_VOPB_SEL_DIVOUT << DCLK_VOPB_SEL_SHIFT |
796 DCLK_VOPB_PLL_SEL_CPLL << DCLK_VOPB_PLL_SEL_SHIFT |
797 (src_clk_div - 1) << DCLK_VOPB_DIV_SHIFT);
800 npll_hz = px30_clk_get_pll_rate(priv, NPLL);
801 if (npll_hz >= PX30_VOP_PLL_LIMIT && npll_hz >= hz &&
803 src_clk_div = npll_hz / hz;
804 assert(src_clk_div - 1 <= 255);
806 if (hz < PX30_VOP_PLL_LIMIT) {
807 src_clk_div = DIV_ROUND_UP(PX30_VOP_PLL_LIMIT,
810 src_clk_div = src_clk_div - 1;
814 assert(src_clk_div - 1 <= 255);
815 rkclk_set_pll(&cru->pll[NPLL], &cru->mode, NPLL,
818 rk_clrsetreg(&cru->clksel_con[8],
819 DCLK_VOPL_SEL_MASK | DCLK_VOPL_PLL_SEL_MASK |
821 DCLK_VOPL_SEL_DIVOUT << DCLK_VOPL_SEL_SHIFT |
822 DCLK_VOPL_PLL_SEL_NPLL << DCLK_VOPL_PLL_SEL_SHIFT |
823 (src_clk_div - 1) << DCLK_VOPL_DIV_SHIFT);
826 printf("do not support this vop freq\n");
830 return px30_vop_get_clk(priv, clk_id);
833 static ulong px30_bus_get_clk(struct px30_clk_priv *priv, ulong clk_id)
835 struct px30_cru *cru = priv->cru;
836 u32 div, con, parent;
840 con = readl(&cru->clksel_con[23]);
841 div = (con & BUS_ACLK_DIV_MASK) >> BUS_ACLK_DIV_SHIFT;
842 parent = priv->gpll_hz;
845 con = readl(&cru->clksel_con[24]);
846 div = (con & BUS_HCLK_DIV_MASK) >> BUS_HCLK_DIV_SHIFT;
847 parent = priv->gpll_hz;
851 parent = px30_bus_get_clk(priv, ACLK_BUS_PRE);
852 con = readl(&cru->clksel_con[24]);
853 div = (con & BUS_PCLK_DIV_MASK) >> BUS_PCLK_DIV_SHIFT;
859 return DIV_TO_RATE(parent, div);
862 static ulong px30_bus_set_clk(struct px30_clk_priv *priv, ulong clk_id,
865 struct px30_cru *cru = priv->cru;
869 * select gpll as pd_bus bus clock source and
870 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
874 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);
875 assert(src_clk_div - 1 <= 31);
876 rk_clrsetreg(&cru->clksel_con[23],
877 BUS_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,
878 BUS_PLL_SEL_GPLL << BUS_PLL_SEL_SHIFT |
879 (src_clk_div - 1) << BUS_ACLK_DIV_SHIFT);
882 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);
883 assert(src_clk_div - 1 <= 31);
884 rk_clrsetreg(&cru->clksel_con[24],
885 BUS_PLL_SEL_MASK | BUS_HCLK_DIV_MASK,
886 BUS_PLL_SEL_GPLL << BUS_PLL_SEL_SHIFT |
887 (src_clk_div - 1) << BUS_HCLK_DIV_SHIFT);
891 DIV_ROUND_UP(px30_bus_get_clk(priv, ACLK_BUS_PRE), hz);
892 assert(src_clk_div - 1 <= 3);
893 rk_clrsetreg(&cru->clksel_con[24],
895 (src_clk_div - 1) << BUS_PCLK_DIV_SHIFT);
898 printf("do not support this bus freq\n");
902 return px30_bus_get_clk(priv, clk_id);
905 static ulong px30_peri_get_clk(struct px30_clk_priv *priv, ulong clk_id)
907 struct px30_cru *cru = priv->cru;
908 u32 div, con, parent;
912 con = readl(&cru->clksel_con[14]);
913 div = (con & PERI_ACLK_DIV_MASK) >> PERI_ACLK_DIV_SHIFT;
914 parent = priv->gpll_hz;
917 con = readl(&cru->clksel_con[14]);
918 div = (con & PERI_HCLK_DIV_MASK) >> PERI_HCLK_DIV_SHIFT;
919 parent = priv->gpll_hz;
925 return DIV_TO_RATE(parent, div);
928 static ulong px30_peri_set_clk(struct px30_clk_priv *priv, ulong clk_id,
931 struct px30_cru *cru = priv->cru;
934 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);
935 assert(src_clk_div - 1 <= 31);
938 * select gpll as pd_peri bus clock source and
939 * set up dependent divisors for HCLK and ACLK clocks.
943 rk_clrsetreg(&cru->clksel_con[14],
944 PERI_PLL_SEL_MASK | PERI_ACLK_DIV_MASK,
945 PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT |
946 (src_clk_div - 1) << PERI_ACLK_DIV_SHIFT);
949 rk_clrsetreg(&cru->clksel_con[14],
950 PERI_PLL_SEL_MASK | PERI_HCLK_DIV_MASK,
951 PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT |
952 (src_clk_div - 1) << PERI_HCLK_DIV_SHIFT);
955 printf("do not support this peri freq\n");
959 return px30_peri_get_clk(priv, clk_id);
962 #ifndef CONFIG_SPL_BUILD
963 static ulong px30_crypto_get_clk(struct px30_clk_priv *priv, ulong clk_id)
965 struct px30_cru *cru = priv->cru;
966 u32 div, con, parent;
970 con = readl(&cru->clksel_con[25]);
971 div = (con & CRYPTO_DIV_MASK) >> CRYPTO_DIV_SHIFT;
972 parent = priv->gpll_hz;
974 case SCLK_CRYPTO_APK:
975 con = readl(&cru->clksel_con[25]);
976 div = (con & CRYPTO_APK_DIV_MASK) >> CRYPTO_APK_DIV_SHIFT;
977 parent = priv->gpll_hz;
983 return DIV_TO_RATE(parent, div);
986 static ulong px30_crypto_set_clk(struct px30_clk_priv *priv, ulong clk_id,
989 struct px30_cru *cru = priv->cru;
992 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);
993 assert(src_clk_div - 1 <= 31);
996 * select gpll as crypto clock source and
997 * set up dependent divisors for crypto clocks.
1001 rk_clrsetreg(&cru->clksel_con[25],
1002 CRYPTO_PLL_SEL_MASK | CRYPTO_DIV_MASK,
1003 CRYPTO_PLL_SEL_GPLL << CRYPTO_PLL_SEL_SHIFT |
1004 (src_clk_div - 1) << CRYPTO_DIV_SHIFT);
1006 case SCLK_CRYPTO_APK:
1007 rk_clrsetreg(&cru->clksel_con[25],
1008 CRYPTO_APK_PLL_SEL_MASK | CRYPTO_APK_DIV_MASK,
1009 CRYPTO_PLL_SEL_GPLL << CRYPTO_APK_SEL_SHIFT |
1010 (src_clk_div - 1) << CRYPTO_APK_DIV_SHIFT);
1013 printf("do not support this peri freq\n");
1017 return px30_crypto_get_clk(priv, clk_id);
1020 static ulong px30_i2s1_mclk_get_clk(struct px30_clk_priv *priv, ulong clk_id)
1022 struct px30_cru *cru = priv->cru;
1025 con = readl(&cru->clksel_con[30]);
1027 if (!(con & CLK_I2S1_OUT_SEL_MASK))
1033 static ulong px30_i2s1_mclk_set_clk(struct px30_clk_priv *priv, ulong clk_id,
1036 struct px30_cru *cru = priv->cru;
1038 if (hz != 12000000) {
1039 printf("do not support this i2s1_mclk freq\n");
1043 rk_clrsetreg(&cru->clksel_con[30], CLK_I2S1_OUT_SEL_MASK,
1044 CLK_I2S1_OUT_SEL_OSC);
1045 rk_clrsetreg(&cru->clkgate_con[10], CLK_I2S1_OUT_MCLK_PAD_MASK,
1046 CLK_I2S1_OUT_MCLK_PAD_ENABLE);
1048 return px30_i2s1_mclk_get_clk(priv, clk_id);
1051 static ulong px30_mac_set_clk(struct px30_clk_priv *priv, uint hz)
1053 struct px30_cru *cru = priv->cru;
1054 u32 con = readl(&cru->clksel_con[22]);
1058 if ((con >> GMAC_PLL_SEL_SHIFT) & GMAC_PLL_SEL_CPLL)
1059 pll_rate = px30_clk_get_pll_rate(priv, CPLL);
1060 else if ((con >> GMAC_PLL_SEL_SHIFT) & GMAC_PLL_SEL_NPLL)
1061 pll_rate = px30_clk_get_pll_rate(priv, NPLL);
1063 pll_rate = priv->gpll_hz;
1065 /*default set 50MHZ for gmac*/
1069 div = DIV_ROUND_UP(pll_rate, hz) - 1;
1071 rk_clrsetreg(&cru->clksel_con[22], CLK_GMAC_DIV_MASK,
1072 div << CLK_GMAC_DIV_SHIFT);
1074 return DIV_TO_RATE(pll_rate, div);
1077 static int px30_mac_set_speed_clk(struct px30_clk_priv *priv, uint hz)
1079 struct px30_cru *cru = priv->cru;
1081 if (hz != 2500000 && hz != 25000000) {
1082 debug("Unsupported mac speed:%d\n", hz);
1086 rk_clrsetreg(&cru->clksel_con[23], RMII_CLK_SEL_MASK,
1087 ((hz == 2500000) ? 0 : 1) << RMII_CLK_SEL_SHIFT);
1094 static ulong px30_clk_get_pll_rate(struct px30_clk_priv *priv,
1095 enum px30_pll_id pll_id)
1097 struct px30_cru *cru = priv->cru;
1099 return rkclk_pll_get_rate(&cru->pll[pll_id], &cru->mode, pll_id);
1102 static ulong px30_clk_set_pll_rate(struct px30_clk_priv *priv,
1103 enum px30_pll_id pll_id, ulong hz)
1105 struct px30_cru *cru = priv->cru;
1107 if (rkclk_set_pll(&cru->pll[pll_id], &cru->mode, pll_id, hz))
1109 return rkclk_pll_get_rate(&cru->pll[pll_id], &cru->mode, pll_id);
1112 static ulong px30_armclk_set_clk(struct px30_clk_priv *priv, ulong hz)
1114 struct px30_cru *cru = priv->cru;
1115 const struct cpu_rate_table *rate;
1118 rate = get_cpu_settings(hz);
1120 printf("%s unsupport rate\n", __func__);
1125 * select apll as cpu/core clock pll source and
1126 * set up dependent divisors for PERI and ACLK clocks.
1127 * core hz : apll = 1:1
1129 old_rate = px30_clk_get_pll_rate(priv, APLL);
1130 if (old_rate > hz) {
1131 if (rkclk_set_pll(&cru->pll[APLL], &cru->mode, APLL, hz))
1133 rk_clrsetreg(&cru->clksel_con[0],
1134 CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK |
1135 CORE_ACLK_DIV_MASK | CORE_DBG_DIV_MASK,
1136 rate->aclk_div << CORE_ACLK_DIV_SHIFT |
1137 rate->pclk_div << CORE_DBG_DIV_SHIFT |
1138 CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
1139 0 << CORE_DIV_CON_SHIFT);
1140 } else if (old_rate < hz) {
1141 rk_clrsetreg(&cru->clksel_con[0],
1142 CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK |
1143 CORE_ACLK_DIV_MASK | CORE_DBG_DIV_MASK,
1144 rate->aclk_div << CORE_ACLK_DIV_SHIFT |
1145 rate->pclk_div << CORE_DBG_DIV_SHIFT |
1146 CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
1147 0 << CORE_DIV_CON_SHIFT);
1148 if (rkclk_set_pll(&cru->pll[APLL], &cru->mode, APLL, hz))
1152 return px30_clk_get_pll_rate(priv, APLL);
1155 static ulong px30_clk_get_rate(struct clk *clk)
1157 struct px30_clk_priv *priv = dev_get_priv(clk->dev);
1160 if (!priv->gpll_hz && clk->id > ARMCLK) {
1161 printf("%s gpll=%lu\n", __func__, priv->gpll_hz);
1165 debug("%s %ld\n", __func__, clk->id);
1168 rate = px30_clk_get_pll_rate(priv, APLL);
1171 rate = px30_clk_get_pll_rate(priv, DPLL);
1174 rate = px30_clk_get_pll_rate(priv, CPLL);
1177 rate = px30_clk_get_pll_rate(priv, NPLL);
1180 rate = px30_clk_get_pll_rate(priv, APLL);
1186 case SCLK_EMMC_SAMPLE:
1187 rate = px30_mmc_get_clk(priv, clk->id);
1193 rate = px30_i2c_get_clk(priv, clk->id);
1196 rate = px30_i2s_get_clk(priv, clk->id);
1199 rate = px30_nandc_get_clk(priv);
1203 rate = px30_pwm_get_clk(priv, clk->id);
1206 rate = px30_saradc_get_clk(priv);
1209 rate = px30_tsadc_get_clk(priv);
1213 rate = px30_spi_get_clk(priv, clk->id);
1219 rate = px30_vop_get_clk(priv, clk->id);
1225 rate = px30_bus_get_clk(priv, clk->id);
1229 rate = px30_peri_get_clk(priv, clk->id);
1231 #ifndef CONFIG_SPL_BUILD
1233 case SCLK_CRYPTO_APK:
1234 rate = px30_crypto_get_clk(priv, clk->id);
1244 static ulong px30_clk_set_rate(struct clk *clk, ulong rate)
1246 struct px30_clk_priv *priv = dev_get_priv(clk->dev);
1249 if (!priv->gpll_hz && clk->id > ARMCLK) {
1250 printf("%s gpll=%lu\n", __func__, priv->gpll_hz);
1254 debug("%s %ld %ld\n", __func__, clk->id, rate);
1257 ret = px30_clk_set_pll_rate(priv, NPLL, rate);
1260 ret = px30_armclk_set_clk(priv, rate);
1266 ret = px30_mmc_set_clk(priv, clk->id, rate);
1272 ret = px30_i2c_set_clk(priv, clk->id, rate);
1275 ret = px30_i2s_set_clk(priv, clk->id, rate);
1278 ret = px30_nandc_set_clk(priv, rate);
1282 ret = px30_pwm_set_clk(priv, clk->id, rate);
1285 ret = px30_saradc_set_clk(priv, rate);
1288 ret = px30_tsadc_set_clk(priv, rate);
1292 ret = px30_spi_set_clk(priv, clk->id, rate);
1298 ret = px30_vop_set_clk(priv, clk->id, rate);
1303 ret = px30_bus_set_clk(priv, clk->id, rate);
1307 ret = px30_peri_set_clk(priv, clk->id, rate);
1309 #ifndef CONFIG_SPL_BUILD
1311 case SCLK_CRYPTO_APK:
1312 ret = px30_crypto_set_clk(priv, clk->id, rate);
1315 ret = px30_i2s1_mclk_set_clk(priv, clk->id, rate);
1319 ret = px30_mac_set_clk(priv, rate);
1321 case SCLK_GMAC_RMII:
1322 ret = px30_mac_set_speed_clk(priv, rate);
1332 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1333 static int px30_gmac_set_parent(struct clk *clk, struct clk *parent)
1335 struct px30_clk_priv *priv = dev_get_priv(clk->dev);
1336 struct px30_cru *cru = priv->cru;
1338 if (parent->id == SCLK_GMAC_SRC) {
1339 debug("%s: switching GAMC to SCLK_GMAC_SRC\n", __func__);
1340 rk_clrsetreg(&cru->clksel_con[23], RMII_EXTCLK_SEL_MASK,
1341 RMII_EXTCLK_SEL_INT << RMII_EXTCLK_SEL_SHIFT);
1343 debug("%s: switching GMAC to external clock\n", __func__);
1344 rk_clrsetreg(&cru->clksel_con[23], RMII_EXTCLK_SEL_MASK,
1345 RMII_EXTCLK_SEL_EXT << RMII_EXTCLK_SEL_SHIFT);
1350 static int px30_clk_set_parent(struct clk *clk, struct clk *parent)
1354 return px30_gmac_set_parent(clk, parent);
1361 static int px30_clk_enable(struct clk *clk)
1366 case SCLK_GMAC_RX_TX:
1368 case SCLK_MAC_REFOUT:
1371 case SCLK_GMAC_RMII:
1372 /* Required to successfully probe the Designware GMAC driver */
1376 debug("%s: unsupported clk %ld\n", __func__, clk->id);
1380 static struct clk_ops px30_clk_ops = {
1381 .get_rate = px30_clk_get_rate,
1382 .set_rate = px30_clk_set_rate,
1383 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1384 .set_parent = px30_clk_set_parent,
1386 .enable = px30_clk_enable,
1389 static void px30_clk_init(struct px30_clk_priv *priv)
1394 npll_hz = px30_clk_get_pll_rate(priv, NPLL);
1395 if (npll_hz != NPLL_HZ) {
1396 ret = px30_clk_set_pll_rate(priv, NPLL, NPLL_HZ);
1398 printf("%s failed to set npll rate\n", __func__);
1401 px30_bus_set_clk(priv, ACLK_BUS_PRE, ACLK_BUS_HZ);
1402 px30_bus_set_clk(priv, HCLK_BUS_PRE, HCLK_BUS_HZ);
1403 px30_bus_set_clk(priv, PCLK_BUS_PRE, PCLK_BUS_HZ);
1404 px30_peri_set_clk(priv, ACLK_PERI_PRE, ACLK_PERI_HZ);
1405 px30_peri_set_clk(priv, HCLK_PERI_PRE, HCLK_PERI_HZ);
1408 static int px30_clk_probe(struct udevice *dev)
1410 struct px30_clk_priv *priv = dev_get_priv(dev);
1411 struct clk clk_gpll;
1414 if (px30_clk_get_pll_rate(priv, APLL) != APLL_HZ)
1415 px30_armclk_set_clk(priv, APLL_HZ);
1417 /* get the GPLL rate from the pmucru */
1418 ret = clk_get_by_name(dev, "gpll", &clk_gpll);
1420 printf("%s: failed to get gpll clk from pmucru\n", __func__);
1424 priv->gpll_hz = clk_get_rate(&clk_gpll);
1426 px30_clk_init(priv);
1431 static int px30_clk_ofdata_to_platdata(struct udevice *dev)
1433 struct px30_clk_priv *priv = dev_get_priv(dev);
1435 priv->cru = dev_read_addr_ptr(dev);
1440 static int px30_clk_bind(struct udevice *dev)
1443 struct udevice *sys_child;
1444 struct sysreset_reg *priv;
1446 /* The reset driver does not have a device node, so bind it here */
1447 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
1450 debug("Warning: No sysreset driver: ret=%d\n", ret);
1452 priv = malloc(sizeof(struct sysreset_reg));
1453 priv->glb_srst_fst_value = offsetof(struct px30_cru,
1455 priv->glb_srst_snd_value = offsetof(struct px30_cru,
1457 sys_child->priv = priv;
1460 #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
1461 ret = offsetof(struct px30_cru, softrst_con[0]);
1462 ret = rockchip_reset_bind(dev, ret, 12);
1464 debug("Warning: software reset driver bind faile\n");
1470 static const struct udevice_id px30_clk_ids[] = {
1471 { .compatible = "rockchip,px30-cru" },
1475 U_BOOT_DRIVER(rockchip_px30_cru) = {
1476 .name = "rockchip_px30_cru",
1478 .of_match = px30_clk_ids,
1479 .priv_auto_alloc_size = sizeof(struct px30_clk_priv),
1480 .ofdata_to_platdata = px30_clk_ofdata_to_platdata,
1481 .ops = &px30_clk_ops,
1482 .bind = px30_clk_bind,
1483 .probe = px30_clk_probe,
1486 static ulong px30_pclk_pmu_get_pmuclk(struct px30_pmuclk_priv *priv)
1488 struct px30_pmucru *pmucru = priv->pmucru;
1491 con = readl(&pmucru->pmu_clksel_con[0]);
1492 div = (con & CLK_PMU_PCLK_DIV_MASK) >> CLK_PMU_PCLK_DIV_SHIFT;
1494 return DIV_TO_RATE(priv->gpll_hz, div);
1497 static ulong px30_pclk_pmu_set_pmuclk(struct px30_pmuclk_priv *priv, ulong hz)
1499 struct px30_pmucru *pmucru = priv->pmucru;
1502 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);
1503 assert(src_clk_div - 1 <= 31);
1505 rk_clrsetreg(&pmucru->pmu_clksel_con[0],
1506 CLK_PMU_PCLK_DIV_MASK,
1507 (src_clk_div - 1) << CLK_PMU_PCLK_DIV_SHIFT);
1509 return px30_pclk_pmu_get_pmuclk(priv);
1512 static ulong px30_pmuclk_get_gpll_rate(struct px30_pmuclk_priv *priv)
1514 struct px30_pmucru *pmucru = priv->pmucru;
1516 return rkclk_pll_get_rate(&pmucru->pll, &pmucru->pmu_mode, GPLL);
1519 static ulong px30_pmuclk_set_gpll_rate(struct px30_pmuclk_priv *priv, ulong hz)
1521 struct px30_pmucru *pmucru = priv->pmucru;
1522 ulong pclk_pmu_rate;
1525 if (priv->gpll_hz == hz)
1526 return priv->gpll_hz;
1528 div = DIV_ROUND_UP(hz, priv->gpll_hz);
1530 /* save clock rate */
1531 pclk_pmu_rate = px30_pclk_pmu_get_pmuclk(priv);
1533 /* avoid rate too large, reduce rate first */
1534 px30_pclk_pmu_set_pmuclk(priv, pclk_pmu_rate / div);
1536 /* change gpll rate */
1537 rkclk_set_pll(&pmucru->pll, &pmucru->pmu_mode, GPLL, hz);
1538 priv->gpll_hz = px30_pmuclk_get_gpll_rate(priv);
1540 /* restore clock rate */
1541 px30_pclk_pmu_set_pmuclk(priv, pclk_pmu_rate);
1543 return priv->gpll_hz;
1546 static ulong px30_pmuclk_get_rate(struct clk *clk)
1548 struct px30_pmuclk_priv *priv = dev_get_priv(clk->dev);
1551 debug("%s %ld\n", __func__, clk->id);
1554 rate = px30_pmuclk_get_gpll_rate(priv);
1557 rate = px30_pclk_pmu_get_pmuclk(priv);
1566 static ulong px30_pmuclk_set_rate(struct clk *clk, ulong rate)
1568 struct px30_pmuclk_priv *priv = dev_get_priv(clk->dev);
1571 debug("%s %ld %ld\n", __func__, clk->id, rate);
1574 ret = px30_pmuclk_set_gpll_rate(priv, rate);
1577 ret = px30_pclk_pmu_set_pmuclk(priv, rate);
1586 static struct clk_ops px30_pmuclk_ops = {
1587 .get_rate = px30_pmuclk_get_rate,
1588 .set_rate = px30_pmuclk_set_rate,
1591 static void px30_pmuclk_init(struct px30_pmuclk_priv *priv)
1593 priv->gpll_hz = px30_pmuclk_get_gpll_rate(priv);
1594 px30_pmuclk_set_gpll_rate(priv, GPLL_HZ);
1596 px30_pclk_pmu_set_pmuclk(priv, PCLK_PMU_HZ);
1599 static int px30_pmuclk_probe(struct udevice *dev)
1601 struct px30_pmuclk_priv *priv = dev_get_priv(dev);
1603 px30_pmuclk_init(priv);
1608 static int px30_pmuclk_ofdata_to_platdata(struct udevice *dev)
1610 struct px30_pmuclk_priv *priv = dev_get_priv(dev);
1612 priv->pmucru = dev_read_addr_ptr(dev);
1617 static const struct udevice_id px30_pmuclk_ids[] = {
1618 { .compatible = "rockchip,px30-pmucru" },
1622 U_BOOT_DRIVER(rockchip_px30_pmucru) = {
1623 .name = "rockchip_px30_pmucru",
1625 .of_match = px30_pmuclk_ids,
1626 .priv_auto_alloc_size = sizeof(struct px30_pmuclk_priv),
1627 .ofdata_to_platdata = px30_pmuclk_ofdata_to_platdata,
1628 .ops = &px30_pmuclk_ops,
1629 .probe = px30_pmuclk_probe,