2 * Renesas RCar Gen3 CPG MSSR driver
4 * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
6 * Based on the following driver from Linux kernel:
7 * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
9 * Copyright (C) 2016 Glider bvba
11 * SPDX-License-Identifier: GPL-2.0+
14 #ifndef __DRIVERS_CLK_RENESAS_CPG_MSSR__
15 #define __DRIVERS_CLK_RENESAS_CPG_MSSR__
17 struct cpg_mssr_info {
18 const struct cpg_core_clk *core_clk;
19 unsigned int core_clk_size;
20 const struct mssr_mod_clk *mod_clk;
21 unsigned int mod_clk_size;
22 const struct mstp_stop_table *mstp_table;
23 unsigned int mstp_table_size;
24 const char *reset_node;
25 const char *extalr_node;
26 unsigned int mod_clk_base;
27 unsigned int clk_extal_id;
28 unsigned int clk_extalr_id;
29 const void *(*get_pll_config)(const u32 cpg_mode);
33 * Definitions of CPG Core Clocks
36 * - Clock outputs exported to DT
37 * - External input clocks
38 * - Internal CPG clocks
45 /* Depending on type */
46 unsigned int parent; /* Core Clocks only */
54 CLK_TYPE_IN, /* External Clock Input */
55 CLK_TYPE_FF, /* Fixed Factor Clock */
57 /* Custom definitions start here */
61 #define DEF_TYPE(_name, _id, _type...) \
62 { .name = _name, .id = _id, .type = _type }
63 #define DEF_BASE(_name, _id, _type, _parent...) \
64 DEF_TYPE(_name, _id, _type, .parent = _parent)
66 #define DEF_INPUT(_name, _id) \
67 DEF_TYPE(_name, _id, CLK_TYPE_IN)
68 #define DEF_FIXED(_name, _id, _parent, _div, _mult) \
69 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
72 * Definitions of Module Clocks
77 unsigned int parent; /* Add MOD_CLK_BASE for Module Clocks */
80 /* Convert from sparse base-100 to packed index space */
81 #define MOD_CLK_PACK(x) ((x) - ((x) / 100) * (100 - 32))
83 #define MOD_CLK_ID(x) (MOD_CLK_BASE + MOD_CLK_PACK(x))
85 #define DEF_MOD(_name, _mod, _parent...) \
86 { .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }
88 struct mstp_stop_table {
96 #define TSTR0_STR0 BIT(0)
98 #endif /* __DRIVERS_CLK_RENESAS_CPG_MSSR__ */