2 * Renesas RCar Gen3 CPG MSSR driver
4 * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
6 * Based on the following driver from Linux kernel:
7 * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
9 * Copyright (C) 2016 Glider bvba
11 * SPDX-License-Identifier: GPL-2.0+
14 #ifndef __DRIVERS_CLK_RENESAS_CPG_MSSR__
15 #define __DRIVERS_CLK_RENESAS_CPG_MSSR__
17 struct cpg_mssr_info {
18 const struct cpg_core_clk *core_clk;
19 unsigned int core_clk_size;
20 const struct mssr_mod_clk *mod_clk;
21 unsigned int mod_clk_size;
22 const struct mstp_stop_table *mstp_table;
23 unsigned int mstp_table_size;
24 const char *reset_node;
25 const char *extalr_node;
26 unsigned int mod_clk_base;
27 unsigned int clk_extal_id;
28 unsigned int clk_extalr_id;
31 struct gen3_clk_priv {
33 struct cpg_mssr_info *info;
35 struct clk clk_extalr;
36 const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
40 * Definitions of CPG Core Clocks
43 * - Clock outputs exported to DT
44 * - External input clocks
45 * - Internal CPG clocks
52 /* Depending on type */
53 unsigned int parent; /* Core Clocks only */
61 CLK_TYPE_IN, /* External Clock Input */
62 CLK_TYPE_FF, /* Fixed Factor Clock */
64 /* Custom definitions start here */
68 #define DEF_TYPE(_name, _id, _type...) \
69 { .name = _name, .id = _id, .type = _type }
70 #define DEF_BASE(_name, _id, _type, _parent...) \
71 DEF_TYPE(_name, _id, _type, .parent = _parent)
73 #define DEF_INPUT(_name, _id) \
74 DEF_TYPE(_name, _id, CLK_TYPE_IN)
75 #define DEF_FIXED(_name, _id, _parent, _div, _mult) \
76 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
77 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \
78 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
79 #define DEF_GEN3_RPC(_name, _id, _parent, _offset) \
80 DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPC, _parent, .offset = _offset)
81 #define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
83 DEF_BASE(_name, _id, CLK_TYPE_FF, \
84 (_parent_clean), .div = (_div_clean), 1)
87 * Definitions of Module Clocks
92 unsigned int parent; /* Add MOD_CLK_BASE for Module Clocks */
95 /* Convert from sparse base-100 to packed index space */
96 #define MOD_CLK_PACK(x) ((x) - ((x) / 100) * (100 - 32))
98 #define MOD_CLK_ID(x) (MOD_CLK_BASE + MOD_CLK_PACK(x))
100 #define DEF_MOD(_name, _mod, _parent...) \
101 { .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }
103 enum rcar_gen3_clk_types {
104 CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM,
117 struct rcar_gen3_cpg_pll_config {
118 unsigned int extal_div;
119 unsigned int pll1_mult;
120 unsigned int pll3_mult;
123 struct mstp_stop_table {
129 #define TSTR0_STR0 BIT(0)
131 int gen3_clk_probe(struct udevice *dev);
132 int gen3_clk_remove(struct udevice *dev);
134 extern const struct clk_ops gen3_clk_ops;
136 #endif /* __DRIVERS_CLK_RENESAS_CPG_MSSR__ */