1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Renesas RCar Gen3 CPG MSSR driver
5 * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
7 * Based on the following driver from Linux kernel:
8 * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
10 * Copyright (C) 2016 Glider bvba
13 #ifndef __DRIVERS_CLK_RENESAS_CPG_MSSR__
14 #define __DRIVERS_CLK_RENESAS_CPG_MSSR__
16 #include <linux/bitops.h>
17 struct cpg_mssr_info {
18 const struct cpg_core_clk *core_clk;
19 unsigned int core_clk_size;
20 const struct mssr_mod_clk *mod_clk;
21 unsigned int mod_clk_size;
22 const struct mstp_stop_table *mstp_table;
23 unsigned int mstp_table_size;
24 const char *reset_node;
25 const char *extalr_node;
26 const char *extal_usb_node;
27 unsigned int mod_clk_base;
28 unsigned int clk_extal_id;
29 unsigned int clk_extalr_id;
30 unsigned int clk_extal_usb_id;
31 unsigned int pll0_div;
32 const void *(*get_pll_config)(const u32 cpg_mode);
36 * Definitions of CPG Core Clocks
39 * - Clock outputs exported to DT
40 * - External input clocks
41 * - Internal CPG clocks
48 /* Depending on type */
49 unsigned int parent; /* Core Clocks only */
57 CLK_TYPE_IN, /* External Clock Input */
58 CLK_TYPE_FF, /* Fixed Factor Clock */
59 CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */
60 CLK_TYPE_DIV6_RO, /* DIV6 Clock read only with extra divisor */
61 CLK_TYPE_FR, /* Fixed Rate Clock */
63 /* Custom definitions start here */
67 #define DEF_TYPE(_name, _id, _type...) \
68 { .name = _name, .id = _id, .type = _type }
69 #define DEF_BASE(_name, _id, _type, _parent...) \
70 DEF_TYPE(_name, _id, _type, .parent = _parent)
72 #define DEF_INPUT(_name, _id) \
73 DEF_TYPE(_name, _id, CLK_TYPE_IN)
74 #define DEF_FIXED(_name, _id, _parent, _div, _mult) \
75 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
76 #define DEF_DIV6P1(_name, _id, _parent, _offset) \
77 DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
78 #define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \
79 DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
80 #define DEF_RATE(_name, _id, _rate) \
81 DEF_TYPE(_name, _id, CLK_TYPE_FR, .mult = _rate)
84 * Definitions of Module Clocks
89 unsigned int parent; /* Add MOD_CLK_BASE for Module Clocks */
92 /* Convert from sparse base-100 to packed index space */
93 #define MOD_CLK_PACK(x) ((x) - ((x) / 100) * (100 - 32))
95 #define MOD_CLK_ID(x) (MOD_CLK_BASE + MOD_CLK_PACK(x))
97 #define DEF_MOD(_name, _mod, _parent...) \
98 { .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }
100 struct mstp_stop_table {
108 #define TSTR0_STR0 BIT(0)
110 bool renesas_clk_is_mod(struct clk *clk);
111 int renesas_clk_get_mod(struct clk *clk, struct cpg_mssr_info *info,
112 const struct mssr_mod_clk **mssr);
113 int renesas_clk_get_core(struct clk *clk, struct cpg_mssr_info *info,
114 const struct cpg_core_clk **core);
115 int renesas_clk_get_parent(struct clk *clk, struct cpg_mssr_info *info,
117 int renesas_clk_endisable(struct clk *clk, void __iomem *base, bool enable);
118 int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info);
120 #endif /* __DRIVERS_CLK_RENESAS_CPG_MSSR__ */