2 * Renesas RCar Gen3 CPG MSSR driver
4 * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
6 * Based on the following driver from Linux kernel:
7 * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
9 * Copyright (C) 2016 Glider bvba
11 * SPDX-License-Identifier: GPL-2.0+
14 #ifndef __DRIVERS_CLK_RENESAS_CPG_MSSR__
15 #define __DRIVERS_CLK_RENESAS_CPG_MSSR__
17 struct cpg_mssr_info {
18 const struct cpg_core_clk *core_clk;
19 unsigned int core_clk_size;
20 const struct mssr_mod_clk *mod_clk;
21 unsigned int mod_clk_size;
22 const struct mstp_stop_table *mstp_table;
23 unsigned int mstp_table_size;
24 const char *reset_node;
25 const char *extalr_node;
26 unsigned int mod_clk_base;
27 unsigned int clk_extal_id;
28 unsigned int clk_extalr_id;
29 const void *(*get_pll_config)(const u32 cpg_mode);
33 * Definitions of CPG Core Clocks
36 * - Clock outputs exported to DT
37 * - External input clocks
38 * - Internal CPG clocks
45 /* Depending on type */
46 unsigned int parent; /* Core Clocks only */
54 CLK_TYPE_IN, /* External Clock Input */
55 CLK_TYPE_FF, /* Fixed Factor Clock */
56 CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */
57 CLK_TYPE_DIV6_RO, /* DIV6 Clock read only with extra divisor */
59 /* Custom definitions start here */
63 #define DEF_TYPE(_name, _id, _type...) \
64 { .name = _name, .id = _id, .type = _type }
65 #define DEF_BASE(_name, _id, _type, _parent...) \
66 DEF_TYPE(_name, _id, _type, .parent = _parent)
68 #define DEF_INPUT(_name, _id) \
69 DEF_TYPE(_name, _id, CLK_TYPE_IN)
70 #define DEF_FIXED(_name, _id, _parent, _div, _mult) \
71 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
72 #define DEF_DIV6P1(_name, _id, _parent, _offset) \
73 DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
74 #define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \
75 DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
78 * Definitions of Module Clocks
83 unsigned int parent; /* Add MOD_CLK_BASE for Module Clocks */
86 /* Convert from sparse base-100 to packed index space */
87 #define MOD_CLK_PACK(x) ((x) - ((x) / 100) * (100 - 32))
89 #define MOD_CLK_ID(x) (MOD_CLK_BASE + MOD_CLK_PACK(x))
91 #define DEF_MOD(_name, _mod, _parent...) \
92 { .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }
94 struct mstp_stop_table {
102 #define TSTR0_STR0 BIT(0)
104 bool renesas_clk_is_mod(struct clk *clk);
105 int renesas_clk_get_mod(struct clk *clk, struct cpg_mssr_info *info,
106 const struct mssr_mod_clk **mssr);
107 int renesas_clk_get_core(struct clk *clk, struct cpg_mssr_info *info,
108 const struct cpg_core_clk **core);
109 int renesas_clk_get_parent(struct clk *clk, struct cpg_mssr_info *info,
111 int renesas_clk_endisable(struct clk *clk, void __iomem *base, bool enable);
112 int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info);
114 #endif /* __DRIVERS_CLK_RENESAS_CPG_MSSR__ */