drivers/clk/renesas/r8a77980-cpg-mssr.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * r8a77980 Clock Pulse Generator / Module Standby and Software Reset
   4  *
   5  * Copyright (C) 2018 Renesas Electronics Corp.
   6  * Copyright (C) 2018 Cogent Embedded, Inc.
   7  *
   8  * Based on r8a7795-cpg-mssr.c
   9  *
  10  * Copyright (C) 2015 Glider bvba
  11  */
  12
  13 #include <common.h>
  14 #include <clk-uclass.h>
  15 #include <dm.h>
  16 #include <linux/bitops.h>
  17
  18 #include <dt-bindings/clock/r8a77980-cpg-mssr.h>
  19
  20 #include "renesas-cpg-mssr.h"
  21 #include "rcar-gen3-cpg.h"
  22
  23 enum clk_ids {
  24         /* Core Clock Outputs exported to DT */
  25         LAST_DT_CORE_CLK = R8A77980_CLK_OSC,
  26
  27         /* External Input Clocks */
  28         CLK_EXTAL,
  29         CLK_EXTALR,
  30
  31         /* Internal Core Clocks */
  32         CLK_MAIN,
  33         CLK_PLL1,
  34         CLK_PLL2,
  35         CLK_PLL3,
  36         CLK_PLL1_DIV2,
  37         CLK_PLL1_DIV4,
  38         CLK_S0,
  39         CLK_S1,
  40         CLK_S2,
  41         CLK_S3,
  42         CLK_SDSRC,
  43         CLK_RPCSRC,
  44         CLK_OCO,
  45
  46         /* Module Clocks */
  47         MOD_CLK_BASE
  48 };
  49
  50 static const struct cpg_core_clk r8a77980_core_clks[] = {
  51         /* External Clock Inputs */
  52         DEF_INPUT("extal",  CLK_EXTAL),
  53         DEF_INPUT("extalr", CLK_EXTALR),
  54
  55         /* Internal Core Clocks */
  56         DEF_BASE(".main",       CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
  57         DEF_BASE(".pll1",       CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
  58         DEF_BASE(".pll2",       CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
  59         DEF_BASE(".pll3",       CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
  60
  61         DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2,     CLK_PLL1,       2, 1),
  62         DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4,     CLK_PLL1_DIV2,  2, 1),
  63         DEF_FIXED(".s0",        CLK_S0,            CLK_PLL1_DIV2,  2, 1),
  64         DEF_FIXED(".s1",        CLK_S1,            CLK_PLL1_DIV2,  3, 1),
  65         DEF_FIXED(".s2",        CLK_S2,            CLK_PLL1_DIV2,  4, 1),
  66         DEF_FIXED(".s3",        CLK_S3,            CLK_PLL1_DIV2,  6, 1),
  67         DEF_FIXED(".sdsrc",     CLK_SDSRC,         CLK_PLL1_DIV2,  2, 1),
  68         DEF_BASE(".rpcsrc",     CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
  69         DEF_RATE(".oco",        CLK_OCO,           32768),
  70
  71         DEF_BASE("rpc",         R8A77980_CLK_RPC, CLK_TYPE_GEN3_RPC,
  72                  CLK_RPCSRC),
  73         DEF_BASE("rpcd2",       R8A77980_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
  74                  R8A77980_CLK_RPC),
  75
  76         /* Core Clock Outputs */
  77         DEF_FIXED("ztr",        R8A77980_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
  78         DEF_FIXED("ztrd2",      R8A77980_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
  79         DEF_FIXED("zt",         R8A77980_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
  80         DEF_FIXED("zx",         R8A77980_CLK_ZX,    CLK_PLL1_DIV2,  2, 1),
  81         DEF_FIXED("s0d1",       R8A77980_CLK_S0D1,  CLK_S0,         1, 1),
  82         DEF_FIXED("s0d2",       R8A77980_CLK_S0D2,  CLK_S0,         2, 1),
  83         DEF_FIXED("s0d3",       R8A77980_CLK_S0D3,  CLK_S0,         3, 1),
  84         DEF_FIXED("s0d4",       R8A77980_CLK_S0D4,  CLK_S0,         4, 1),
  85         DEF_FIXED("s0d6",       R8A77980_CLK_S0D6,  CLK_S0,         6, 1),
  86         DEF_FIXED("s0d12",      R8A77980_CLK_S0D12, CLK_S0,        12, 1),
  87         DEF_FIXED("s0d24",      R8A77980_CLK_S0D24, CLK_S0,        24, 1),
  88         DEF_FIXED("s1d1",       R8A77980_CLK_S1D1,  CLK_S1,         1, 1),
  89         DEF_FIXED("s1d2",       R8A77980_CLK_S1D2,  CLK_S1,         2, 1),
  90         DEF_FIXED("s1d4",       R8A77980_CLK_S1D4,  CLK_S1,         4, 1),
  91         DEF_FIXED("s2d1",       R8A77980_CLK_S2D1,  CLK_S2,         1, 1),
  92         DEF_FIXED("s2d2",       R8A77980_CLK_S2D2,  CLK_S2,         2, 1),
  93         DEF_FIXED("s2d4",       R8A77980_CLK_S2D4,  CLK_S2,         4, 1),
  94         DEF_FIXED("s3d1",       R8A77980_CLK_S3D1,  CLK_S3,         1, 1),
  95         DEF_FIXED("s3d2",       R8A77980_CLK_S3D2,  CLK_S3,         2, 1),
  96         DEF_FIXED("s3d4",       R8A77980_CLK_S3D4,  CLK_S3,         4, 1),
  97
  98         DEF_GEN3_SD("sd0",      R8A77980_CLK_SD0,   CLK_SDSRC,    0x0074),
  99
 100         DEF_FIXED("cl",         R8A77980_CLK_CL,    CLK_PLL1_DIV2, 48, 1),
 101         DEF_FIXED("cp",         R8A77980_CLK_CP,    CLK_EXTAL,      2, 1),
 102         DEF_FIXED("cpex",       R8A77980_CLK_CPEX,  CLK_EXTAL,      2, 1),
 103
 104         DEF_DIV6P1("canfd",     R8A77980_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
 105         DEF_DIV6P1("csi0",      R8A77980_CLK_CSI0,  CLK_PLL1_DIV4, 0x00c),
 106         DEF_DIV6P1("mso",       R8A77980_CLK_MSO,   CLK_PLL1_DIV4, 0x014),
 107
 108         DEF_GEN3_OSC("osc",     R8A77980_CLK_OSC,   CLK_EXTAL,     8),
 109         DEF_GEN3_MDSEL("r",     R8A77980_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
 110 };
 111
 112 static const struct mssr_mod_clk r8a77980_mod_clks[] = {
 113         DEF_MOD("tmu4",                  121,   R8A77980_CLK_S0D6),
 114         DEF_MOD("tmu3",                  122,   R8A77980_CLK_S0D6),
 115         DEF_MOD("tmu2",                  123,   R8A77980_CLK_S0D6),
 116         DEF_MOD("tmu1",                  124,   R8A77980_CLK_S0D6),
 117         DEF_MOD("tmu0",                  125,   R8A77980_CLK_CP),
 118         DEF_MOD("scif4",                 203,   R8A77980_CLK_S3D4),
 119         DEF_MOD("scif3",                 204,   R8A77980_CLK_S3D4),
 120         DEF_MOD("scif1",                 206,   R8A77980_CLK_S3D4),
 121         DEF_MOD("scif0",                 207,   R8A77980_CLK_S3D4),
 122         DEF_MOD("msiof3",                208,   R8A77980_CLK_MSO),
 123         DEF_MOD("msiof2",                209,   R8A77980_CLK_MSO),
 124         DEF_MOD("msiof1",                210,   R8A77980_CLK_MSO),
 125         DEF_MOD("msiof0",                211,   R8A77980_CLK_MSO),
 126         DEF_MOD("sys-dmac2",             217,   R8A77980_CLK_S0D3),
 127         DEF_MOD("sys-dmac1",             218,   R8A77980_CLK_S0D3),
 128         DEF_MOD("cmt3",                  300,   R8A77980_CLK_R),
 129         DEF_MOD("cmt2",                  301,   R8A77980_CLK_R),
 130         DEF_MOD("cmt1",                  302,   R8A77980_CLK_R),
 131         DEF_MOD("cmt0",                  303,   R8A77980_CLK_R),
 132         DEF_MOD("tpu0",                  304,   R8A77980_CLK_S3D4),
 133         DEF_MOD("sdif",                  314,   R8A77980_CLK_SD0),
 134         DEF_MOD("pciec0",                319,   R8A77980_CLK_S2D2),
 135         DEF_MOD("rwdt",                  402,   R8A77980_CLK_R),
 136         DEF_MOD("intc-ex",               407,   R8A77980_CLK_CP),
 137         DEF_MOD("intc-ap",               408,   R8A77980_CLK_S0D3),
 138         DEF_MOD("hscif3",                517,   R8A77980_CLK_S3D1),
 139         DEF_MOD("hscif2",                518,   R8A77980_CLK_S3D1),
 140         DEF_MOD("hscif1",                519,   R8A77980_CLK_S3D1),
 141         DEF_MOD("hscif0",                520,   R8A77980_CLK_S3D1),
 142         DEF_MOD("imp4",                  521,   R8A77980_CLK_S1D1),
 143         DEF_MOD("thermal",               522,   R8A77980_CLK_CP),
 144         DEF_MOD("pwm",                   523,   R8A77980_CLK_S0D12),
 145         DEF_MOD("impdma1",               526,   R8A77980_CLK_S1D1),
 146         DEF_MOD("impdma0",               527,   R8A77980_CLK_S1D1),
 147         DEF_MOD("imp-ocv4",              528,   R8A77980_CLK_S1D1),
 148         DEF_MOD("imp-ocv3",              529,   R8A77980_CLK_S1D1),
 149         DEF_MOD("imp-ocv2",              531,   R8A77980_CLK_S1D1),
 150         DEF_MOD("fcpvd0",                603,   R8A77980_CLK_S3D1),
 151         DEF_MOD("vspd0",                 623,   R8A77980_CLK_S3D1),
 152         DEF_MOD("csi41",                 715,   R8A77980_CLK_CSI0),
 153         DEF_MOD("csi40",                 716,   R8A77980_CLK_CSI0),
 154         DEF_MOD("du0",                   724,   R8A77980_CLK_S2D1),
 155         DEF_MOD("lvds",                  727,   R8A77980_CLK_S2D1),
 156         DEF_MOD("etheravb",              812,   R8A77980_CLK_S3D2),
 157         DEF_MOD("gether",                813,   R8A77980_CLK_S3D2),
 158         DEF_MOD("imp3",                  824,   R8A77980_CLK_S1D1),
 159         DEF_MOD("imp2",                  825,   R8A77980_CLK_S1D1),
 160         DEF_MOD("imp1",                  826,   R8A77980_CLK_S1D1),
 161         DEF_MOD("imp0",                  827,   R8A77980_CLK_S1D1),
 162         DEF_MOD("imp-ocv1",              828,   R8A77980_CLK_S1D1),
 163         DEF_MOD("imp-ocv0",              829,   R8A77980_CLK_S1D1),
 164         DEF_MOD("impram",                830,   R8A77980_CLK_S1D1),
 165         DEF_MOD("impcnn",                831,   R8A77980_CLK_S1D1),
 166         DEF_MOD("gpio5",                 907,   R8A77980_CLK_CP),
 167         DEF_MOD("gpio4",                 908,   R8A77980_CLK_CP),
 168         DEF_MOD("gpio3",                 909,   R8A77980_CLK_CP),
 169         DEF_MOD("gpio2",                 910,   R8A77980_CLK_CP),
 170         DEF_MOD("gpio1",                 911,   R8A77980_CLK_CP),
 171         DEF_MOD("gpio0",                 912,   R8A77980_CLK_CP),
 172         DEF_MOD("can-fd",                914,   R8A77980_CLK_S3D2),
 173         DEF_MOD("rpc-if",                917,   R8A77980_CLK_RPCD2),
 174         DEF_MOD("i2c4",                  927,   R8A77980_CLK_S0D6),
 175         DEF_MOD("i2c3",                  928,   R8A77980_CLK_S0D6),
 176         DEF_MOD("i2c2",                  929,   R8A77980_CLK_S3D2),
 177         DEF_MOD("i2c1",                  930,   R8A77980_CLK_S3D2),
 178         DEF_MOD("i2c0",                  931,   R8A77980_CLK_S3D2),
 179 };
 180
 181 /*
 182  * CPG Clock Data
 183  */
 184
 185 /*
 186  *   MD         EXTAL           PLL2    PLL1    PLL3    OSC
 187  * 14 13        (MHz)
 188  * --------------------------------------------------------
 189  * 0  0         16.66 x 1       x240    x192    x192    /16
 190  * 0  1         20    x 1       x200    x160    x160    /19
 191  * 1  0         27    x 1       x148    x118    x118    /26
 192  * 1  1         33.33 / 2       x240    x192    x192    /32
 193  */
 194 #define CPG_PLL_CONFIG_INDEX(md)        ((((md) & BIT(14)) >> 13) | \
 195                                          (((md) & BIT(13)) >> 13))
 196
 197 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[4] = {
 198         /* EXTAL div    PLL1 mult/div   PLL3 mult/div   OSC prediv */
 199         { 1,            192,    1,      192,    1,      16,     },
 200         { 1,            160,    1,      160,    1,      19,     },
 201         { 1,            118,    1,      118,    1,      26,     },
 202         { 2,            192,    1,      192,    1,      32,     },
 203 };
 204
 205 static const struct mstp_stop_table r8a77980_mstp_table[] = {
 206         { 0x00230000, 0x0, 0x00230000, 0 },
 207         { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
 208         { 0x14062FD8, 0x2040, 0x14062FD8, 0 },
 209         { 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 },
 210         { 0x80000184, 0x180, 0x80000184, 0 },
 211         { 0x83FFFFFF, 0x0, 0x83FFFFFF, 0 },
 212         { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
 213         { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
 214         { 0x7FF3FFF4, 0x0, 0x7FF3FFF4, 0 },
 215         { 0xFBF7FF97, 0x0, 0xFBF7FF97, 0 },
 216         { 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
 217         { 0x000000B7, 0x0, 0x000000B7, 0 },
 218 };
 219
 220 static const void *r8a77980_get_pll_config(const u32 cpg_mode)
 221 {
 222         return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
 223 }
 224
 225 static const struct cpg_mssr_info r8a77980_cpg_mssr_info = {
 226         .core_clk               = r8a77980_core_clks,
 227         .core_clk_size          = ARRAY_SIZE(r8a77980_core_clks),
 228         .mod_clk                = r8a77980_mod_clks,
 229         .mod_clk_size           = ARRAY_SIZE(r8a77980_mod_clks),
 230         .mstp_table             = r8a77980_mstp_table,
 231         .mstp_table_size        = ARRAY_SIZE(r8a77980_mstp_table),
 232         .reset_node             = "renesas,r8a77980-rst",
 233         .extalr_node            = "extalr",
 234         .mod_clk_base           = MOD_CLK_BASE,
 235         .clk_extal_id           = CLK_EXTAL,
 236         .clk_extalr_id          = CLK_EXTALR,
 237         .get_pll_config         = r8a77980_get_pll_config,
 238 };
 239
 240 static const struct udevice_id r8a77980_clk_ids[] = {
 241         {
 242                 .compatible     = "renesas,r8a77980-cpg-mssr",
 243                 .data           = (ulong)&r8a77980_cpg_mssr_info
 244         },
 245         { }
 246 };
 247
 248 U_BOOT_DRIVER(clk_r8a77980) = {
 249         .name           = "clk_r8a77980",
 250         .id             = UCLASS_CLK,
 251         .of_match       = r8a77980_clk_ids,
 252         .priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
 253         .ops            = &gen3_clk_ops,
 254         .probe          = gen3_clk_probe,
 255         .remove         = gen3_clk_remove,
 256 };