2 * Renesas R8A77970 CPG MSSR driver
4 * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
6 * Based on the following driver from Linux kernel:
7 * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
9 * Copyright (C) 2016 Glider bvba
11 * SPDX-License-Identifier: GPL-2.0+
15 #include <clk-uclass.h>
18 #include <dt-bindings/clock/r8a77970-cpg-mssr.h>
20 #include "renesas-cpg-mssr.h"
22 static const struct cpg_core_clk r8a77970_core_clks[] = {
23 /* External Clock Inputs */
24 DEF_INPUT("extal", CLK_EXTAL),
25 DEF_INPUT("extalr", CLK_EXTALR),
27 /* Internal Core Clocks */
28 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
29 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
30 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
31 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
33 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
34 DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
35 DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 4, 1),
36 DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 6, 1),
37 DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
39 /* Core Clock Outputs */
40 DEF_BASE("z2", R8A77970_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL1_DIV4),
41 DEF_FIXED("ztr", R8A77970_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
42 DEF_FIXED("ztrd2", R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
43 DEF_FIXED("zt", R8A77970_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
44 DEF_FIXED("zx", R8A77970_CLK_ZX, CLK_PLL1_DIV2, 3, 1),
45 DEF_FIXED("s1d1", R8A77970_CLK_S1D1, CLK_S1, 1, 1),
46 DEF_FIXED("s1d2", R8A77970_CLK_S1D2, CLK_S1, 2, 1),
47 DEF_FIXED("s1d4", R8A77970_CLK_S1D4, CLK_S1, 4, 1),
48 DEF_FIXED("s2d1", R8A77970_CLK_S2D1, CLK_S2, 1, 1),
49 DEF_FIXED("s2d2", R8A77970_CLK_S2D2, CLK_S2, 2, 1),
50 DEF_FIXED("s2d4", R8A77970_CLK_S2D4, CLK_S2, 4, 1),
52 DEF_GEN3_SD("sd0", R8A77970_CLK_SD0, CLK_PLL1_DIV4, 0x0074),
54 DEF_GEN3_RPC("rpc", R8A77970_CLK_RPC, CLK_RPCSRC, 0x238),
56 DEF_FIXED("cl", R8A77970_CLK_CL, CLK_PLL1_DIV2, 48, 1),
57 DEF_FIXED("cp", R8A77970_CLK_CP, CLK_EXTAL, 2, 1),
59 /* NOTE: HDMI, CSI, CAN etc. clock are missing */
61 DEF_BASE("r", R8A77970_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
64 static const struct mssr_mod_clk r8a77970_mod_clks[] = {
65 DEF_MOD("ivcp1e", 127, R8A77970_CLK_S2D1),
66 DEF_MOD("scif4", 203, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
67 DEF_MOD("scif3", 204, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
68 DEF_MOD("scif1", 206, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
69 DEF_MOD("scif0", 207, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
70 DEF_MOD("msiof3", 208, R8A77970_CLK_MSO),
71 DEF_MOD("msiof2", 209, R8A77970_CLK_MSO),
72 DEF_MOD("msiof1", 210, R8A77970_CLK_MSO),
73 DEF_MOD("msiof0", 211, R8A77970_CLK_MSO),
74 DEF_MOD("mfis", 213, R8A77970_CLK_S2D2), /* @@ H3=S3D2 */
75 DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
76 DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
77 DEF_MOD("sdif", 314, R8A77970_CLK_SD0),
78 DEF_MOD("rwdt0", 402, R8A77970_CLK_R),
79 DEF_MOD("intc-ex", 407, R8A77970_CLK_CP),
80 DEF_MOD("intc-ap", 408, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
81 DEF_MOD("hscif3", 517, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
82 DEF_MOD("hscif2", 518, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
83 DEF_MOD("hscif1", 519, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
84 DEF_MOD("hscif0", 520, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
85 DEF_MOD("thermal", 522, R8A77970_CLK_CP),
86 DEF_MOD("pwm", 523, R8A77970_CLK_S2D4),
87 DEF_MOD("fcpvd0", 603, R8A77970_CLK_S2D1),
88 DEF_MOD("vspd0", 623, R8A77970_CLK_S2D1),
89 DEF_MOD("csi40", 716, R8A77970_CLK_CSI0),
90 DEF_MOD("du0", 724, R8A77970_CLK_S2D1),
91 DEF_MOD("lvds", 727, R8A77970_CLK_S2D1),
92 DEF_MOD("vin3", 808, R8A77970_CLK_S2D1),
93 DEF_MOD("vin2", 809, R8A77970_CLK_S2D1),
94 DEF_MOD("vin1", 810, R8A77970_CLK_S2D1),
95 DEF_MOD("vin0", 811, R8A77970_CLK_S2D1),
96 DEF_MOD("etheravb", 812, R8A77970_CLK_S2D2),
97 DEF_MOD("isp", 817, R8A77970_CLK_S2D1),
98 DEF_MOD("gpio5", 907, R8A77970_CLK_CP),
99 DEF_MOD("gpio4", 908, R8A77970_CLK_CP),
100 DEF_MOD("gpio3", 909, R8A77970_CLK_CP),
101 DEF_MOD("gpio2", 910, R8A77970_CLK_CP),
102 DEF_MOD("gpio1", 911, R8A77970_CLK_CP),
103 DEF_MOD("gpio0", 912, R8A77970_CLK_CP),
104 DEF_MOD("can-fd", 914, R8A77970_CLK_S2D2),
105 DEF_MOD("rpc", 917, R8A77970_CLK_RPC),
106 DEF_MOD("i2c4", 927, R8A77970_CLK_S2D2),
107 DEF_MOD("i2c3", 928, R8A77970_CLK_S2D2),
108 DEF_MOD("i2c2", 929, R8A77970_CLK_S2D2),
109 DEF_MOD("i2c1", 930, R8A77970_CLK_S2D2),
110 DEF_MOD("i2c0", 931, R8A77970_CLK_S2D2),
113 static const struct mstp_stop_table r8a77970_mstp_table[] = {
114 { 0x00230000, 0x0 }, { 0xFFFFFFFF, 0x0 },
115 { 0x14062FD8, 0x2040 }, { 0xFFFFFFDF, 0x400 },
116 { 0x80000184, 0x180 }, { 0x83FFFFFF, 0x0 },
117 { 0xFFFFFFFF, 0x0 }, { 0xFFFFFFFF, 0x0 },
118 { 0x7FF3FFF4, 0x0 }, { 0xFBF7FF97, 0x0 },
119 { 0xFFFEFFE0, 0x0 }, { 0x000000B7, 0x0 },
122 static const struct cpg_mssr_info r8a77970_cpg_mssr_info = {
123 .core_clk = r8a77970_core_clks,
124 .core_clk_size = ARRAY_SIZE(r8a77970_core_clks),
125 .mod_clk = r8a77970_mod_clks,
126 .mod_clk_size = ARRAY_SIZE(r8a77970_mod_clks),
127 .mstp_table = r8a77970_mstp_table,
128 .mstp_table_size = ARRAY_SIZE(r8a77970_mstp_table),
129 .reset_node = "renesas,r8a77970-rst",
130 .extalr_node = "extalr",
133 static const struct udevice_id r8a77970_clk_ids[] = {
135 .compatible = "renesas,r8a77970-cpg-mssr",
136 .data = (ulong)&r8a77970_cpg_mssr_info
141 U_BOOT_DRIVER(clk_r8a77970) = {
142 .name = "clk_r8a77970",
144 .of_match = r8a77970_clk_ids,
145 .priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
146 .ops = &gen3_clk_ops,
147 .probe = gen3_clk_probe,
148 .remove = gen3_clk_remove,