drivers/clk/renesas/clk-rcar-gen3.c

   1 /*
   2  * Renesas RCar Gen3 R8A7795/R8A7796 CPG MSSR driver
   3  *
   4  * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
   5  *
   6  * Based on the following driver from Linux kernel:
   7  * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
   8  *
   9  * Copyright (C) 2016 Glider bvba
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13
  14 #include <common.h>
  15 #include <clk-uclass.h>
  16 #include <dm.h>
  17 #include <errno.h>
  18 #include <wait_bit.h>
  19 #include <asm/io.h>
  20
  21 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
  22 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
  23
  24 #define CPG_RST_MODEMR          0x0060
  25
  26 #define CPG_PLL0CR              0x00d8
  27 #define CPG_PLL2CR              0x002c
  28 #define CPG_PLL4CR              0x01f4
  29
  30 /*
  31  * Module Standby and Software Reset register offets.
  32  *
  33  * If the registers exist, these are valid for SH-Mobile, R-Mobile,
  34  * R-Car Gen2, R-Car Gen3, and RZ/G1.
  35  * These are NOT valid for R-Car Gen1 and RZ/A1!
  36  */
  37
  38 /*
  39  * Module Stop Status Register offsets
  40  */
  41
  42 static const u16 mstpsr[] = {
  43         0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
  44         0x9A0, 0x9A4, 0x9A8, 0x9AC,
  45 };
  46
  47 #define MSTPSR(i)       mstpsr[i]
  48
  49
  50 /*
  51  * System Module Stop Control Register offsets
  52  */
  53
  54 static const u16 smstpcr[] = {
  55         0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
  56         0x990, 0x994, 0x998, 0x99C,
  57 };
  58
  59 #define SMSTPCR(i)      smstpcr[i]
  60
  61
  62 /* Realtime Module Stop Control Register offsets */
  63 #define RMSTPCR(i)      (smstpcr[i] - 0x20)
  64
  65 /* Modem Module Stop Control Register offsets (r8a73a4) */
  66 #define MMSTPCR(i)      (smstpcr[i] + 0x20)
  67
  68 /* Software Reset Clearing Register offsets */
  69 #define SRSTCLR(i)      (0x940 + (i) * 4)
  70
  71 struct gen3_clk_priv {
  72         void __iomem    *base;
  73         struct clk      clk_extal;
  74         struct clk      clk_extalr;
  75         const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
  76         const struct cpg_core_clk *core_clk;
  77         u32             core_clk_size;
  78         const struct mssr_mod_clk *mod_clk;
  79         u32             mod_clk_size;
  80 };
  81
  82 /*
  83  * Definitions of CPG Core Clocks
  84  *
  85  * These include:
  86  *   - Clock outputs exported to DT
  87  *   - External input clocks
  88  *   - Internal CPG clocks
  89  */
  90 struct cpg_core_clk {
  91         /* Common */
  92         const char *name;
  93         unsigned int id;
  94         unsigned int type;
  95         /* Depending on type */
  96         unsigned int parent;    /* Core Clocks only */
  97         unsigned int div;
  98         unsigned int mult;
  99         unsigned int offset;
 100 };
 101
 102 enum clk_types {
 103         /* Generic */
 104         CLK_TYPE_IN,            /* External Clock Input */
 105         CLK_TYPE_FF,            /* Fixed Factor Clock */
 106
 107         /* Custom definitions start here */
 108         CLK_TYPE_CUSTOM,
 109 };
 110
 111 #define DEF_TYPE(_name, _id, _type...)  \
 112         { .name = _name, .id = _id, .type = _type }
 113 #define DEF_BASE(_name, _id, _type, _parent...) \
 114         DEF_TYPE(_name, _id, _type, .parent = _parent)
 115
 116 #define DEF_INPUT(_name, _id) \
 117         DEF_TYPE(_name, _id, CLK_TYPE_IN)
 118 #define DEF_FIXED(_name, _id, _parent, _div, _mult)     \
 119         DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
 120 #define DEF_GEN3_SD(_name, _id, _parent, _offset)       \
 121         DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
 122
 123 /*
 124  * Definitions of Module Clocks
 125  */
 126 struct mssr_mod_clk {
 127         const char *name;
 128         unsigned int id;
 129         unsigned int parent;    /* Add MOD_CLK_BASE for Module Clocks */
 130 };
 131
 132 /* Convert from sparse base-100 to packed index space */
 133 #define MOD_CLK_PACK(x) ((x) - ((x) / 100) * (100 - 32))
 134
 135 #define MOD_CLK_ID(x)   (MOD_CLK_BASE + MOD_CLK_PACK(x))
 136
 137 #define DEF_MOD(_name, _mod, _parent...)        \
 138         { .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }
 139
 140 enum rcar_gen3_clk_types {
 141         CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM,
 142         CLK_TYPE_GEN3_PLL0,
 143         CLK_TYPE_GEN3_PLL1,
 144         CLK_TYPE_GEN3_PLL2,
 145         CLK_TYPE_GEN3_PLL3,
 146         CLK_TYPE_GEN3_PLL4,
 147         CLK_TYPE_GEN3_SD,
 148         CLK_TYPE_GEN3_R,
 149 };
 150
 151 struct rcar_gen3_cpg_pll_config {
 152         unsigned int extal_div;
 153         unsigned int pll1_mult;
 154         unsigned int pll3_mult;
 155 };
 156
 157 enum clk_ids {
 158         /* Core Clock Outputs exported to DT */
 159         LAST_DT_CORE_CLK = R8A7796_CLK_OSC,
 160
 161         /* External Input Clocks */
 162         CLK_EXTAL,
 163         CLK_EXTALR,
 164
 165         /* Internal Core Clocks */
 166         CLK_MAIN,
 167         CLK_PLL0,
 168         CLK_PLL1,
 169         CLK_PLL2,
 170         CLK_PLL3,
 171         CLK_PLL4,
 172         CLK_PLL1_DIV2,
 173         CLK_PLL1_DIV4,
 174         CLK_S0,
 175         CLK_S1,
 176         CLK_S2,
 177         CLK_S3,
 178         CLK_SDSRC,
 179         CLK_SSPSRC,
 180         CLK_RINT,
 181
 182         /* Module Clocks */
 183         MOD_CLK_BASE
 184 };
 185
 186 static const struct cpg_core_clk r8a7795_core_clks[] = {
 187         /* External Clock Inputs */
 188         DEF_INPUT("extal",      CLK_EXTAL),
 189         DEF_INPUT("extalr",     CLK_EXTALR),
 190
 191         /* Internal Core Clocks */
 192         DEF_BASE(".main",       CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
 193         DEF_BASE(".pll0",       CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
 194         DEF_BASE(".pll1",       CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
 195         DEF_BASE(".pll2",       CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
 196         DEF_BASE(".pll3",       CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
 197         DEF_BASE(".pll4",       CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
 198
 199         DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2,     CLK_PLL1,       2, 1),
 200         DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4,     CLK_PLL1_DIV2,  2, 1),
 201         DEF_FIXED(".s0",        CLK_S0,            CLK_PLL1_DIV2,  2, 1),
 202         DEF_FIXED(".s1",        CLK_S1,            CLK_PLL1_DIV2,  3, 1),
 203         DEF_FIXED(".s2",        CLK_S2,            CLK_PLL1_DIV2,  4, 1),
 204         DEF_FIXED(".s3",        CLK_S3,            CLK_PLL1_DIV2,  6, 1),
 205         DEF_FIXED(".sdsrc",     CLK_SDSRC,         CLK_PLL1_DIV2,  2, 1),
 206
 207         /* Core Clock Outputs */
 208         DEF_FIXED("ztr",        R8A7795_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
 209         DEF_FIXED("ztrd2",      R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
 210         DEF_FIXED("zt",         R8A7795_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
 211         DEF_FIXED("zx",         R8A7795_CLK_ZX,    CLK_PLL1_DIV2,  2, 1),
 212         DEF_FIXED("s0d1",       R8A7795_CLK_S0D1,  CLK_S0,         1, 1),
 213         DEF_FIXED("s0d2",       R8A7795_CLK_S0D2,  CLK_S0,         2, 1),
 214         DEF_FIXED("s0d3",       R8A7795_CLK_S0D3,  CLK_S0,         3, 1),
 215         DEF_FIXED("s0d4",       R8A7795_CLK_S0D4,  CLK_S0,         4, 1),
 216         DEF_FIXED("s0d6",       R8A7795_CLK_S0D6,  CLK_S0,         6, 1),
 217         DEF_FIXED("s0d8",       R8A7795_CLK_S0D8,  CLK_S0,         8, 1),
 218         DEF_FIXED("s0d12",      R8A7795_CLK_S0D12, CLK_S0,        12, 1),
 219         DEF_FIXED("s1d1",       R8A7795_CLK_S1D1,  CLK_S1,         1, 1),
 220         DEF_FIXED("s1d2",       R8A7795_CLK_S1D2,  CLK_S1,         2, 1),
 221         DEF_FIXED("s1d4",       R8A7795_CLK_S1D4,  CLK_S1,         4, 1),
 222         DEF_FIXED("s2d1",       R8A7795_CLK_S2D1,  CLK_S2,         1, 1),
 223         DEF_FIXED("s2d2",       R8A7795_CLK_S2D2,  CLK_S2,         2, 1),
 224         DEF_FIXED("s2d4",       R8A7795_CLK_S2D4,  CLK_S2,         4, 1),
 225         DEF_FIXED("s3d1",       R8A7795_CLK_S3D1,  CLK_S3,         1, 1),
 226         DEF_FIXED("s3d2",       R8A7795_CLK_S3D2,  CLK_S3,         2, 1),
 227         DEF_FIXED("s3d4",       R8A7795_CLK_S3D4,  CLK_S3,         4, 1),
 228
 229         DEF_GEN3_SD("sd0",      R8A7795_CLK_SD0,   CLK_SDSRC,     0x074),
 230         DEF_GEN3_SD("sd1",      R8A7795_CLK_SD1,   CLK_SDSRC,     0x078),
 231         DEF_GEN3_SD("sd2",      R8A7795_CLK_SD2,   CLK_SDSRC,     0x268),
 232         DEF_GEN3_SD("sd3",      R8A7795_CLK_SD3,   CLK_SDSRC,     0x26c),
 233
 234         DEF_FIXED("cl",         R8A7795_CLK_CL,    CLK_PLL1_DIV2, 48, 1),
 235         DEF_FIXED("cp",         R8A7795_CLK_CP,    CLK_EXTAL,      2, 1),
 236
 237         /* NOTE: HDMI, CSI, CAN etc. clock are missing */
 238
 239         DEF_BASE("r",           R8A7795_CLK_R,     CLK_TYPE_GEN3_R, CLK_RINT),
 240 };
 241
 242 static const struct mssr_mod_clk r8a7795_mod_clks[] = {
 243         DEF_MOD("fdp1-2",                117,   R8A7795_CLK_S2D1), /* ES1.x */
 244         DEF_MOD("fdp1-1",                118,   R8A7795_CLK_S0D1),
 245         DEF_MOD("fdp1-0",                119,   R8A7795_CLK_S0D1),
 246         DEF_MOD("scif5",                 202,   R8A7795_CLK_S3D4),
 247         DEF_MOD("scif4",                 203,   R8A7795_CLK_S3D4),
 248         DEF_MOD("scif3",                 204,   R8A7795_CLK_S3D4),
 249         DEF_MOD("scif1",                 206,   R8A7795_CLK_S3D4),
 250         DEF_MOD("scif0",                 207,   R8A7795_CLK_S3D4),
 251         DEF_MOD("msiof3",                208,   R8A7795_CLK_MSO),
 252         DEF_MOD("msiof2",                209,   R8A7795_CLK_MSO),
 253         DEF_MOD("msiof1",                210,   R8A7795_CLK_MSO),
 254         DEF_MOD("msiof0",                211,   R8A7795_CLK_MSO),
 255         DEF_MOD("sys-dmac2",             217,   R8A7795_CLK_S0D3),
 256         DEF_MOD("sys-dmac1",             218,   R8A7795_CLK_S0D3),
 257         DEF_MOD("sys-dmac0",             219,   R8A7795_CLK_S0D3),
 258         DEF_MOD("cmt3",                  300,   R8A7795_CLK_R),
 259         DEF_MOD("cmt2",                  301,   R8A7795_CLK_R),
 260         DEF_MOD("cmt1",                  302,   R8A7795_CLK_R),
 261         DEF_MOD("cmt0",                  303,   R8A7795_CLK_R),
 262         DEF_MOD("scif2",                 310,   R8A7795_CLK_S3D4),
 263         DEF_MOD("sdif3",                 311,   R8A7795_CLK_SD3),
 264         DEF_MOD("sdif2",                 312,   R8A7795_CLK_SD2),
 265         DEF_MOD("sdif1",                 313,   R8A7795_CLK_SD1),
 266         DEF_MOD("sdif0",                 314,   R8A7795_CLK_SD0),
 267         DEF_MOD("pcie1",                 318,   R8A7795_CLK_S3D1),
 268         DEF_MOD("pcie0",                 319,   R8A7795_CLK_S3D1),
 269         DEF_MOD("usb-dmac30",            326,   R8A7795_CLK_S3D1),
 270         DEF_MOD("usb3-if1",              327,   R8A7795_CLK_S3D1), /* ES1.x */
 271         DEF_MOD("usb3-if0",              328,   R8A7795_CLK_S3D1),
 272         DEF_MOD("usb-dmac31",            329,   R8A7795_CLK_S3D1),
 273         DEF_MOD("usb-dmac0",             330,   R8A7795_CLK_S3D1),
 274         DEF_MOD("usb-dmac1",             331,   R8A7795_CLK_S3D1),
 275         DEF_MOD("rwdt",                  402,   R8A7795_CLK_R),
 276         DEF_MOD("intc-ex",               407,   R8A7795_CLK_CP),
 277         DEF_MOD("intc-ap",               408,   R8A7795_CLK_S3D1),
 278         DEF_MOD("audmac1",               501,   R8A7795_CLK_S0D3),
 279         DEF_MOD("audmac0",               502,   R8A7795_CLK_S0D3),
 280         DEF_MOD("drif7",                 508,   R8A7795_CLK_S3D2),
 281         DEF_MOD("drif6",                 509,   R8A7795_CLK_S3D2),
 282         DEF_MOD("drif5",                 510,   R8A7795_CLK_S3D2),
 283         DEF_MOD("drif4",                 511,   R8A7795_CLK_S3D2),
 284         DEF_MOD("drif3",                 512,   R8A7795_CLK_S3D2),
 285         DEF_MOD("drif2",                 513,   R8A7795_CLK_S3D2),
 286         DEF_MOD("drif1",                 514,   R8A7795_CLK_S3D2),
 287         DEF_MOD("drif0",                 515,   R8A7795_CLK_S3D2),
 288         DEF_MOD("hscif4",                516,   R8A7795_CLK_S3D1),
 289         DEF_MOD("hscif3",                517,   R8A7795_CLK_S3D1),
 290         DEF_MOD("hscif2",                518,   R8A7795_CLK_S3D1),
 291         DEF_MOD("hscif1",                519,   R8A7795_CLK_S3D1),
 292         DEF_MOD("hscif0",                520,   R8A7795_CLK_S3D1),
 293         DEF_MOD("thermal",               522,   R8A7795_CLK_CP),
 294         DEF_MOD("pwm",                   523,   R8A7795_CLK_S0D12),
 295         DEF_MOD("fcpvd3",                600,   R8A7795_CLK_S2D1), /* ES1.x */
 296         DEF_MOD("fcpvd2",                601,   R8A7795_CLK_S0D2),
 297         DEF_MOD("fcpvd1",                602,   R8A7795_CLK_S0D2),
 298         DEF_MOD("fcpvd0",                603,   R8A7795_CLK_S0D2),
 299         DEF_MOD("fcpvb1",                606,   R8A7795_CLK_S0D1),
 300         DEF_MOD("fcpvb0",                607,   R8A7795_CLK_S0D1),
 301         DEF_MOD("fcpvi2",                609,   R8A7795_CLK_S2D1), /* ES1.x */
 302         DEF_MOD("fcpvi1",                610,   R8A7795_CLK_S0D1),
 303         DEF_MOD("fcpvi0",                611,   R8A7795_CLK_S0D1),
 304         DEF_MOD("fcpf2",                 613,   R8A7795_CLK_S2D1), /* ES1.x */
 305         DEF_MOD("fcpf1",                 614,   R8A7795_CLK_S0D1),
 306         DEF_MOD("fcpf0",                 615,   R8A7795_CLK_S0D1),
 307         DEF_MOD("fcpci1",                616,   R8A7795_CLK_S2D1), /* ES1.x */
 308         DEF_MOD("fcpci0",                617,   R8A7795_CLK_S2D1), /* ES1.x */
 309         DEF_MOD("fcpcs",                 619,   R8A7795_CLK_S0D1),
 310         DEF_MOD("vspd3",                 620,   R8A7795_CLK_S2D1), /* ES1.x */
 311         DEF_MOD("vspd2",                 621,   R8A7795_CLK_S0D2),
 312         DEF_MOD("vspd1",                 622,   R8A7795_CLK_S0D2),
 313         DEF_MOD("vspd0",                 623,   R8A7795_CLK_S0D2),
 314         DEF_MOD("vspbc",                 624,   R8A7795_CLK_S0D1),
 315         DEF_MOD("vspbd",                 626,   R8A7795_CLK_S0D1),
 316         DEF_MOD("vspi2",                 629,   R8A7795_CLK_S2D1), /* ES1.x */
 317         DEF_MOD("vspi1",                 630,   R8A7795_CLK_S0D1),
 318         DEF_MOD("vspi0",                 631,   R8A7795_CLK_S0D1),
 319         DEF_MOD("ehci3",                 700,   R8A7795_CLK_S3D4),
 320         DEF_MOD("ehci2",                 701,   R8A7795_CLK_S3D4),
 321         DEF_MOD("ehci1",                 702,   R8A7795_CLK_S3D4),
 322         DEF_MOD("ehci0",                 703,   R8A7795_CLK_S3D4),
 323         DEF_MOD("hsusb",                 704,   R8A7795_CLK_S3D4),
 324         DEF_MOD("hsusb3",                705,   R8A7795_CLK_S3D4),
 325         DEF_MOD("csi21",                 713,   R8A7795_CLK_CSI0), /* ES1.x */
 326         DEF_MOD("csi20",                 714,   R8A7795_CLK_CSI0),
 327         DEF_MOD("csi41",                 715,   R8A7795_CLK_CSI0),
 328         DEF_MOD("csi40",                 716,   R8A7795_CLK_CSI0),
 329         DEF_MOD("du3",                   721,   R8A7795_CLK_S2D1),
 330         DEF_MOD("du2",                   722,   R8A7795_CLK_S2D1),
 331         DEF_MOD("du1",                   723,   R8A7795_CLK_S2D1),
 332         DEF_MOD("du0",                   724,   R8A7795_CLK_S2D1),
 333         DEF_MOD("lvds",                  727,   R8A7795_CLK_S0D4),
 334         DEF_MOD("hdmi1",                 728,   R8A7795_CLK_HDMI),
 335         DEF_MOD("hdmi0",                 729,   R8A7795_CLK_HDMI),
 336         DEF_MOD("vin7",                  804,   R8A7795_CLK_S0D2),
 337         DEF_MOD("vin6",                  805,   R8A7795_CLK_S0D2),
 338         DEF_MOD("vin5",                  806,   R8A7795_CLK_S0D2),
 339         DEF_MOD("vin4",                  807,   R8A7795_CLK_S0D2),
 340         DEF_MOD("vin3",                  808,   R8A7795_CLK_S0D2),
 341         DEF_MOD("vin2",                  809,   R8A7795_CLK_S0D2),
 342         DEF_MOD("vin1",                  810,   R8A7795_CLK_S0D2),
 343         DEF_MOD("vin0",                  811,   R8A7795_CLK_S0D2),
 344         DEF_MOD("etheravb",              812,   R8A7795_CLK_S0D6),
 345         DEF_MOD("sata0",                 815,   R8A7795_CLK_S3D2),
 346         DEF_MOD("imr3",                  820,   R8A7795_CLK_S0D2),
 347         DEF_MOD("imr2",                  821,   R8A7795_CLK_S0D2),
 348         DEF_MOD("imr1",                  822,   R8A7795_CLK_S0D2),
 349         DEF_MOD("imr0",                  823,   R8A7795_CLK_S0D2),
 350         DEF_MOD("gpio7",                 905,   R8A7795_CLK_S3D4),
 351         DEF_MOD("gpio6",                 906,   R8A7795_CLK_S3D4),
 352         DEF_MOD("gpio5",                 907,   R8A7795_CLK_S3D4),
 353         DEF_MOD("gpio4",                 908,   R8A7795_CLK_S3D4),
 354         DEF_MOD("gpio3",                 909,   R8A7795_CLK_S3D4),
 355         DEF_MOD("gpio2",                 910,   R8A7795_CLK_S3D4),
 356         DEF_MOD("gpio1",                 911,   R8A7795_CLK_S3D4),
 357         DEF_MOD("gpio0",                 912,   R8A7795_CLK_S3D4),
 358         DEF_MOD("can-fd",                914,   R8A7795_CLK_S3D2),
 359         DEF_MOD("can-if1",               915,   R8A7795_CLK_S3D4),
 360         DEF_MOD("can-if0",               916,   R8A7795_CLK_S3D4),
 361         DEF_MOD("i2c6",                  918,   R8A7795_CLK_S0D6),
 362         DEF_MOD("i2c5",                  919,   R8A7795_CLK_S0D6),
 363         DEF_MOD("i2c-dvfs",              926,   R8A7795_CLK_CP),
 364         DEF_MOD("i2c4",                  927,   R8A7795_CLK_S0D6),
 365         DEF_MOD("i2c3",                  928,   R8A7795_CLK_S0D6),
 366         DEF_MOD("i2c2",                  929,   R8A7795_CLK_S3D2),
 367         DEF_MOD("i2c1",                  930,   R8A7795_CLK_S3D2),
 368         DEF_MOD("i2c0",                  931,   R8A7795_CLK_S3D2),
 369         DEF_MOD("ssi-all",              1005,   R8A7795_CLK_S3D4),
 370         DEF_MOD("ssi9",                 1006,   MOD_CLK_ID(1005)),
 371         DEF_MOD("ssi8",                 1007,   MOD_CLK_ID(1005)),
 372         DEF_MOD("ssi7",                 1008,   MOD_CLK_ID(1005)),
 373         DEF_MOD("ssi6",                 1009,   MOD_CLK_ID(1005)),
 374         DEF_MOD("ssi5",                 1010,   MOD_CLK_ID(1005)),
 375         DEF_MOD("ssi4",                 1011,   MOD_CLK_ID(1005)),
 376         DEF_MOD("ssi3",                 1012,   MOD_CLK_ID(1005)),
 377         DEF_MOD("ssi2",                 1013,   MOD_CLK_ID(1005)),
 378         DEF_MOD("ssi1",                 1014,   MOD_CLK_ID(1005)),
 379         DEF_MOD("ssi0",                 1015,   MOD_CLK_ID(1005)),
 380         DEF_MOD("scu-all",              1017,   R8A7795_CLK_S3D4),
 381         DEF_MOD("scu-dvc1",             1018,   MOD_CLK_ID(1017)),
 382         DEF_MOD("scu-dvc0",             1019,   MOD_CLK_ID(1017)),
 383         DEF_MOD("scu-ctu1-mix1",        1020,   MOD_CLK_ID(1017)),
 384         DEF_MOD("scu-ctu0-mix0",        1021,   MOD_CLK_ID(1017)),
 385         DEF_MOD("scu-src9",             1022,   MOD_CLK_ID(1017)),
 386         DEF_MOD("scu-src8",             1023,   MOD_CLK_ID(1017)),
 387         DEF_MOD("scu-src7",             1024,   MOD_CLK_ID(1017)),
 388         DEF_MOD("scu-src6",             1025,   MOD_CLK_ID(1017)),
 389         DEF_MOD("scu-src5",             1026,   MOD_CLK_ID(1017)),
 390         DEF_MOD("scu-src4",             1027,   MOD_CLK_ID(1017)),
 391         DEF_MOD("scu-src3",             1028,   MOD_CLK_ID(1017)),
 392         DEF_MOD("scu-src2",             1029,   MOD_CLK_ID(1017)),
 393         DEF_MOD("scu-src1",             1030,   MOD_CLK_ID(1017)),
 394         DEF_MOD("scu-src0",             1031,   MOD_CLK_ID(1017)),
 395 };
 396
 397 static const struct cpg_core_clk r8a7796_core_clks[] = {
 398         /* External Clock Inputs */
 399         DEF_INPUT("extal",      CLK_EXTAL),
 400         DEF_INPUT("extalr",     CLK_EXTALR),
 401
 402         /* Internal Core Clocks */
 403         DEF_BASE(".main",       CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
 404         DEF_BASE(".pll0",       CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
 405         DEF_BASE(".pll1",       CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
 406         DEF_BASE(".pll2",       CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
 407         DEF_BASE(".pll3",       CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
 408         DEF_BASE(".pll4",       CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
 409
 410         DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2,     CLK_PLL1,       2, 1),
 411         DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4,     CLK_PLL1_DIV2,  2, 1),
 412         DEF_FIXED(".s0",        CLK_S0,            CLK_PLL1_DIV2,  2, 1),
 413         DEF_FIXED(".s1",        CLK_S1,            CLK_PLL1_DIV2,  3, 1),
 414         DEF_FIXED(".s2",        CLK_S2,            CLK_PLL1_DIV2,  4, 1),
 415         DEF_FIXED(".s3",        CLK_S3,            CLK_PLL1_DIV2,  6, 1),
 416         DEF_FIXED(".sdsrc",     CLK_SDSRC,         CLK_PLL1_DIV2,  2, 1),
 417
 418         /* Core Clock Outputs */
 419         DEF_FIXED("ztr",        R8A7796_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
 420         DEF_FIXED("ztrd2",      R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
 421         DEF_FIXED("zt",         R8A7796_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
 422         DEF_FIXED("zx",         R8A7796_CLK_ZX,    CLK_PLL1_DIV2,  2, 1),
 423         DEF_FIXED("s0d1",       R8A7796_CLK_S0D1,  CLK_S0,         1, 1),
 424         DEF_FIXED("s0d2",       R8A7796_CLK_S0D2,  CLK_S0,         2, 1),
 425         DEF_FIXED("s0d3",       R8A7796_CLK_S0D3,  CLK_S0,         3, 1),
 426         DEF_FIXED("s0d4",       R8A7796_CLK_S0D4,  CLK_S0,         4, 1),
 427         DEF_FIXED("s0d6",       R8A7796_CLK_S0D6,  CLK_S0,         6, 1),
 428         DEF_FIXED("s0d8",       R8A7796_CLK_S0D8,  CLK_S0,         8, 1),
 429         DEF_FIXED("s0d12",      R8A7796_CLK_S0D12, CLK_S0,        12, 1),
 430         DEF_FIXED("s1d1",       R8A7796_CLK_S1D1,  CLK_S1,         1, 1),
 431         DEF_FIXED("s1d2",       R8A7796_CLK_S1D2,  CLK_S1,         2, 1),
 432         DEF_FIXED("s1d4",       R8A7796_CLK_S1D4,  CLK_S1,         4, 1),
 433         DEF_FIXED("s2d1",       R8A7796_CLK_S2D1,  CLK_S2,         1, 1),
 434         DEF_FIXED("s2d2",       R8A7796_CLK_S2D2,  CLK_S2,         2, 1),
 435         DEF_FIXED("s2d4",       R8A7796_CLK_S2D4,  CLK_S2,         4, 1),
 436         DEF_FIXED("s3d1",       R8A7796_CLK_S3D1,  CLK_S3,         1, 1),
 437         DEF_FIXED("s3d2",       R8A7796_CLK_S3D2,  CLK_S3,         2, 1),
 438         DEF_FIXED("s3d4",       R8A7796_CLK_S3D4,  CLK_S3,         4, 1),
 439
 440         DEF_GEN3_SD("sd0",      R8A7796_CLK_SD0,   CLK_SDSRC,     0x074),
 441         DEF_GEN3_SD("sd1",      R8A7796_CLK_SD1,   CLK_SDSRC,     0x078),
 442         DEF_GEN3_SD("sd2",      R8A7796_CLK_SD2,   CLK_SDSRC,     0x268),
 443         DEF_GEN3_SD("sd3",      R8A7796_CLK_SD3,   CLK_SDSRC,     0x26c),
 444
 445         DEF_FIXED("cl",         R8A7796_CLK_CL,    CLK_PLL1_DIV2, 48, 1),
 446         DEF_FIXED("cp",         R8A7796_CLK_CP,    CLK_EXTAL,      2, 1),
 447
 448         /* NOTE: HDMI, CSI, CAN etc. clock are missing */
 449
 450         DEF_BASE("r",           R8A7796_CLK_R,     CLK_TYPE_GEN3_R, CLK_RINT),
 451 };
 452
 453 static const struct mssr_mod_clk r8a7796_mod_clks[] = {
 454         DEF_MOD("scif5",                 202,   R8A7796_CLK_S3D4),
 455         DEF_MOD("scif4",                 203,   R8A7796_CLK_S3D4),
 456         DEF_MOD("scif3",                 204,   R8A7796_CLK_S3D4),
 457         DEF_MOD("scif1",                 206,   R8A7796_CLK_S3D4),
 458         DEF_MOD("scif0",                 207,   R8A7796_CLK_S3D4),
 459         DEF_MOD("msiof3",                208,   R8A7796_CLK_MSO),
 460         DEF_MOD("msiof2",                209,   R8A7796_CLK_MSO),
 461         DEF_MOD("msiof1",                210,   R8A7796_CLK_MSO),
 462         DEF_MOD("msiof0",                211,   R8A7796_CLK_MSO),
 463         DEF_MOD("sys-dmac2",             217,   R8A7796_CLK_S0D3),
 464         DEF_MOD("sys-dmac1",             218,   R8A7796_CLK_S0D3),
 465         DEF_MOD("sys-dmac0",             219,   R8A7796_CLK_S0D3),
 466         DEF_MOD("cmt3",                  300,   R8A7796_CLK_R),
 467         DEF_MOD("cmt2",                  301,   R8A7796_CLK_R),
 468         DEF_MOD("cmt1",                  302,   R8A7796_CLK_R),
 469         DEF_MOD("cmt0",                  303,   R8A7796_CLK_R),
 470         DEF_MOD("scif2",                 310,   R8A7796_CLK_S3D4),
 471         DEF_MOD("sdif3",                 311,   R8A7796_CLK_SD3),
 472         DEF_MOD("sdif2",                 312,   R8A7796_CLK_SD2),
 473         DEF_MOD("sdif1",                 313,   R8A7796_CLK_SD1),
 474         DEF_MOD("sdif0",                 314,   R8A7796_CLK_SD0),
 475         DEF_MOD("pcie1",                 318,   R8A7796_CLK_S3D1),
 476         DEF_MOD("pcie0",                 319,   R8A7796_CLK_S3D1),
 477         DEF_MOD("usb-dmac0",             330,   R8A7796_CLK_S3D1),
 478         DEF_MOD("usb-dmac1",             331,   R8A7796_CLK_S3D1),
 479         DEF_MOD("rwdt",                  402,   R8A7796_CLK_R),
 480         DEF_MOD("intc-ex",               407,   R8A7796_CLK_CP),
 481         DEF_MOD("intc-ap",               408,   R8A7796_CLK_S3D1),
 482         DEF_MOD("audmac1",               501,   R8A7796_CLK_S0D3),
 483         DEF_MOD("audmac0",               502,   R8A7796_CLK_S0D3),
 484         DEF_MOD("drif7",                 508,   R8A7796_CLK_S3D2),
 485         DEF_MOD("drif6",                 509,   R8A7796_CLK_S3D2),
 486         DEF_MOD("drif5",                 510,   R8A7796_CLK_S3D2),
 487         DEF_MOD("drif4",                 511,   R8A7796_CLK_S3D2),
 488         DEF_MOD("drif3",                 512,   R8A7796_CLK_S3D2),
 489         DEF_MOD("drif2",                 513,   R8A7796_CLK_S3D2),
 490         DEF_MOD("drif1",                 514,   R8A7796_CLK_S3D2),
 491         DEF_MOD("drif0",                 515,   R8A7796_CLK_S3D2),
 492         DEF_MOD("hscif4",                516,   R8A7796_CLK_S3D1),
 493         DEF_MOD("hscif3",                517,   R8A7796_CLK_S3D1),
 494         DEF_MOD("hscif2",                518,   R8A7796_CLK_S3D1),
 495         DEF_MOD("hscif1",                519,   R8A7796_CLK_S3D1),
 496         DEF_MOD("hscif0",                520,   R8A7796_CLK_S3D1),
 497         DEF_MOD("thermal",               522,   R8A7796_CLK_CP),
 498         DEF_MOD("pwm",                   523,   R8A7796_CLK_S0D12),
 499         DEF_MOD("fcpvd2",                601,   R8A7796_CLK_S0D2),
 500         DEF_MOD("fcpvd1",                602,   R8A7796_CLK_S0D2),
 501         DEF_MOD("fcpvd0",                603,   R8A7796_CLK_S0D2),
 502         DEF_MOD("fcpvb0",                607,   R8A7796_CLK_S0D1),
 503         DEF_MOD("fcpvi0",                611,   R8A7796_CLK_S0D1),
 504         DEF_MOD("fcpf0",                 615,   R8A7796_CLK_S0D1),
 505         DEF_MOD("fcpci0",                617,   R8A7796_CLK_S0D2),
 506         DEF_MOD("fcpcs",                 619,   R8A7796_CLK_S0D2),
 507         DEF_MOD("vspd2",                 621,   R8A7796_CLK_S0D2),
 508         DEF_MOD("vspd1",                 622,   R8A7796_CLK_S0D2),
 509         DEF_MOD("vspd0",                 623,   R8A7796_CLK_S0D2),
 510         DEF_MOD("vspb",                  626,   R8A7796_CLK_S0D1),
 511         DEF_MOD("vspi0",                 631,   R8A7796_CLK_S0D1),
 512         DEF_MOD("ehci1",                 702,   R8A7796_CLK_S3D4),
 513         DEF_MOD("ehci0",                 703,   R8A7796_CLK_S3D4),
 514         DEF_MOD("hsusb",                 704,   R8A7796_CLK_S3D4),
 515         DEF_MOD("csi20",                 714,   R8A7796_CLK_CSI0),
 516         DEF_MOD("csi40",                 716,   R8A7796_CLK_CSI0),
 517         DEF_MOD("du2",                   722,   R8A7796_CLK_S2D1),
 518         DEF_MOD("du1",                   723,   R8A7796_CLK_S2D1),
 519         DEF_MOD("du0",                   724,   R8A7796_CLK_S2D1),
 520         DEF_MOD("lvds",                  727,   R8A7796_CLK_S2D1),
 521         DEF_MOD("hdmi0",                 729,   R8A7796_CLK_HDMI),
 522         DEF_MOD("vin7",                  804,   R8A7796_CLK_S0D2),
 523         DEF_MOD("vin6",                  805,   R8A7796_CLK_S0D2),
 524         DEF_MOD("vin5",                  806,   R8A7796_CLK_S0D2),
 525         DEF_MOD("vin4",                  807,   R8A7796_CLK_S0D2),
 526         DEF_MOD("vin3",                  808,   R8A7796_CLK_S0D2),
 527         DEF_MOD("vin2",                  809,   R8A7796_CLK_S0D2),
 528         DEF_MOD("vin1",                  810,   R8A7796_CLK_S0D2),
 529         DEF_MOD("vin0",                  811,   R8A7796_CLK_S0D2),
 530         DEF_MOD("etheravb",              812,   R8A7796_CLK_S0D6),
 531         DEF_MOD("imr1",                  822,   R8A7796_CLK_S0D2),
 532         DEF_MOD("imr0",                  823,   R8A7796_CLK_S0D2),
 533         DEF_MOD("gpio7",                 905,   R8A7796_CLK_S3D4),
 534         DEF_MOD("gpio6",                 906,   R8A7796_CLK_S3D4),
 535         DEF_MOD("gpio5",                 907,   R8A7796_CLK_S3D4),
 536         DEF_MOD("gpio4",                 908,   R8A7796_CLK_S3D4),
 537         DEF_MOD("gpio3",                 909,   R8A7796_CLK_S3D4),
 538         DEF_MOD("gpio2",                 910,   R8A7796_CLK_S3D4),
 539         DEF_MOD("gpio1",                 911,   R8A7796_CLK_S3D4),
 540         DEF_MOD("gpio0",                 912,   R8A7796_CLK_S3D4),
 541         DEF_MOD("can-fd",                914,   R8A7796_CLK_S3D2),
 542         DEF_MOD("can-if1",               915,   R8A7796_CLK_S3D4),
 543         DEF_MOD("can-if0",               916,   R8A7796_CLK_S3D4),
 544         DEF_MOD("i2c6",                  918,   R8A7796_CLK_S0D6),
 545         DEF_MOD("i2c5",                  919,   R8A7796_CLK_S0D6),
 546         DEF_MOD("i2c-dvfs",              926,   R8A7796_CLK_CP),
 547         DEF_MOD("i2c4",                  927,   R8A7796_CLK_S0D6),
 548         DEF_MOD("i2c3",                  928,   R8A7796_CLK_S0D6),
 549         DEF_MOD("i2c2",                  929,   R8A7796_CLK_S3D2),
 550         DEF_MOD("i2c1",                  930,   R8A7796_CLK_S3D2),
 551         DEF_MOD("i2c0",                  931,   R8A7796_CLK_S3D2),
 552         DEF_MOD("ssi-all",              1005,   R8A7796_CLK_S3D4),
 553         DEF_MOD("ssi9",                 1006,   MOD_CLK_ID(1005)),
 554         DEF_MOD("ssi8",                 1007,   MOD_CLK_ID(1005)),
 555         DEF_MOD("ssi7",                 1008,   MOD_CLK_ID(1005)),
 556         DEF_MOD("ssi6",                 1009,   MOD_CLK_ID(1005)),
 557         DEF_MOD("ssi5",                 1010,   MOD_CLK_ID(1005)),
 558         DEF_MOD("ssi4",                 1011,   MOD_CLK_ID(1005)),
 559         DEF_MOD("ssi3",                 1012,   MOD_CLK_ID(1005)),
 560         DEF_MOD("ssi2",                 1013,   MOD_CLK_ID(1005)),
 561         DEF_MOD("ssi1",                 1014,   MOD_CLK_ID(1005)),
 562         DEF_MOD("ssi0",                 1015,   MOD_CLK_ID(1005)),
 563         DEF_MOD("scu-all",              1017,   R8A7796_CLK_S3D4),
 564         DEF_MOD("scu-dvc1",             1018,   MOD_CLK_ID(1017)),
 565         DEF_MOD("scu-dvc0",             1019,   MOD_CLK_ID(1017)),
 566         DEF_MOD("scu-ctu1-mix1",        1020,   MOD_CLK_ID(1017)),
 567         DEF_MOD("scu-ctu0-mix0",        1021,   MOD_CLK_ID(1017)),
 568         DEF_MOD("scu-src9",             1022,   MOD_CLK_ID(1017)),
 569         DEF_MOD("scu-src8",             1023,   MOD_CLK_ID(1017)),
 570         DEF_MOD("scu-src7",             1024,   MOD_CLK_ID(1017)),
 571         DEF_MOD("scu-src6",             1025,   MOD_CLK_ID(1017)),
 572         DEF_MOD("scu-src5",             1026,   MOD_CLK_ID(1017)),
 573         DEF_MOD("scu-src4",             1027,   MOD_CLK_ID(1017)),
 574         DEF_MOD("scu-src3",             1028,   MOD_CLK_ID(1017)),
 575         DEF_MOD("scu-src2",             1029,   MOD_CLK_ID(1017)),
 576         DEF_MOD("scu-src1",             1030,   MOD_CLK_ID(1017)),
 577         DEF_MOD("scu-src0",             1031,   MOD_CLK_ID(1017)),
 578 };
 579
 580 /*
 581  * CPG Clock Data
 582  */
 583
 584 /*
 585  *   MD         EXTAL           PLL0    PLL1    PLL2    PLL3    PLL4
 586  * 14 13 19 17  (MHz)
 587  *-------------------------------------------------------------------
 588  * 0  0  0  0   16.66 x 1       x180    x192    x144    x192    x144
 589  * 0  0  0  1   16.66 x 1       x180    x192    x144    x128    x144
 590  * 0  0  1  0   Prohibited setting
 591  * 0  0  1  1   16.66 x 1       x180    x192    x144    x192    x144
 592  * 0  1  0  0   20    x 1       x150    x160    x120    x160    x120
 593  * 0  1  0  1   20    x 1       x150    x160    x120    x106    x120
 594  * 0  1  1  0   Prohibited setting
 595  * 0  1  1  1   20    x 1       x150    x160    x120    x160    x120
 596  * 1  0  0  0   25    x 1       x120    x128    x96     x128    x96
 597  * 1  0  0  1   25    x 1       x120    x128    x96     x84     x96
 598  * 1  0  1  0   Prohibited setting
 599  * 1  0  1  1   25    x 1       x120    x128    x96     x128    x96
 600  * 1  1  0  0   33.33 / 2       x180    x192    x144    x192    x144
 601  * 1  1  0  1   33.33 / 2       x180    x192    x144    x128    x144
 602  * 1  1  1  0   Prohibited setting
 603  * 1  1  1  1   33.33 / 2       x180    x192    x144    x192    x144
 604  */
 605 #define CPG_PLL_CONFIG_INDEX(md)        ((((md) & BIT(14)) >> 11) | \
 606                                          (((md) & BIT(13)) >> 11) | \
 607                                          (((md) & BIT(19)) >> 18) | \
 608                                          (((md) & BIT(17)) >> 17))
 609
 610 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
 611         /* EXTAL div    PLL1 mult       PLL3 mult */
 612         { 1,            192,            192,    },
 613         { 1,            192,            128,    },
 614         { 0, /* Prohibited setting */           },
 615         { 1,            192,            192,    },
 616         { 1,            160,            160,    },
 617         { 1,            160,            106,    },
 618         { 0, /* Prohibited setting */           },
 619         { 1,            160,            160,    },
 620         { 1,            128,            128,    },
 621         { 1,            128,            84,     },
 622         { 0, /* Prohibited setting */           },
 623         { 1,            128,            128,    },
 624         { 2,            192,            192,    },
 625         { 2,            192,            128,    },
 626         { 0, /* Prohibited setting */           },
 627         { 2,            192,            192,    },
 628 };
 629
 630 /*
 631  * SDn Clock
 632  */
 633 #define CPG_SD_STP_HCK          BIT(9)
 634 #define CPG_SD_STP_CK           BIT(8)
 635
 636 #define CPG_SD_STP_MASK         (CPG_SD_STP_HCK | CPG_SD_STP_CK)
 637 #define CPG_SD_FC_MASK          (0x7 << 2 | 0x3 << 0)
 638
 639 #define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \
 640 { \
 641         .val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \
 642                ((stp_ck) ? CPG_SD_STP_CK : 0) | \
 643                ((sd_srcfc) << 2) | \
 644                ((sd_fc) << 0), \
 645         .div = (sd_div), \
 646 }
 647
 648 struct sd_div_table {
 649         u32 val;
 650         unsigned int div;
 651 };
 652
 653 /* SDn divider
 654  *                     sd_srcfc   sd_fc   div
 655  * stp_hck   stp_ck    (div)      (div)     = sd_srcfc x sd_fc
 656  *-------------------------------------------------------------------
 657  *  0         0         0 (1)      1 (4)      4
 658  *  0         0         1 (2)      1 (4)      8
 659  *  1         0         2 (4)      1 (4)     16
 660  *  1         0         3 (8)      1 (4)     32
 661  *  1         0         4 (16)     1 (4)     64
 662  *  0         0         0 (1)      0 (2)      2
 663  *  0         0         1 (2)      0 (2)      4
 664  *  1         0         2 (4)      0 (2)      8
 665  *  1         0         3 (8)      0 (2)     16
 666  *  1         0         4 (16)     0 (2)     32
 667  */
 668 static const struct sd_div_table cpg_sd_div_table[] = {
 669 /*      CPG_SD_DIV_TABLE_DATA(stp_hck,  stp_ck,   sd_srcfc,   sd_fc,  sd_div) */
 670         CPG_SD_DIV_TABLE_DATA(0,        0,        0,          1,        4),
 671         CPG_SD_DIV_TABLE_DATA(0,        0,        1,          1,        8),
 672         CPG_SD_DIV_TABLE_DATA(1,        0,        2,          1,       16),
 673         CPG_SD_DIV_TABLE_DATA(1,        0,        3,          1,       32),
 674         CPG_SD_DIV_TABLE_DATA(1,        0,        4,          1,       64),
 675         CPG_SD_DIV_TABLE_DATA(0,        0,        0,          0,        2),
 676         CPG_SD_DIV_TABLE_DATA(0,        0,        1,          0,        4),
 677         CPG_SD_DIV_TABLE_DATA(1,        0,        2,          0,        8),
 678         CPG_SD_DIV_TABLE_DATA(1,        0,        3,          0,       16),
 679         CPG_SD_DIV_TABLE_DATA(1,        0,        4,          0,       32),
 680 };
 681
 682 static bool gen3_clk_is_mod(struct clk *clk)
 683 {
 684         return (clk->id >> 16) == CPG_MOD;
 685 }
 686
 687 static int gen3_clk_get_mod(struct clk *clk, const struct mssr_mod_clk **mssr)
 688 {
 689         struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
 690         const unsigned long clkid = clk->id & 0xffff;
 691         int i;
 692
 693         if (!gen3_clk_is_mod(clk))
 694                 return -EINVAL;
 695
 696         for (i = 0; i < priv->mod_clk_size; i++) {
 697                 if (priv->mod_clk[i].id != MOD_CLK_ID(clkid))
 698                         continue;
 699
 700                 *mssr = &priv->mod_clk[i];
 701                 return 0;
 702         }
 703
 704         return -ENODEV;
 705 }
 706
 707 static int gen3_clk_get_core(struct clk *clk, const struct cpg_core_clk **core)
 708 {
 709         struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
 710         const unsigned long clkid = clk->id & 0xffff;
 711         int i;
 712
 713         if (gen3_clk_is_mod(clk))
 714                 return -EINVAL;
 715
 716         for (i = 0; i < priv->core_clk_size; i++) {
 717                 if (priv->core_clk[i].id != clkid)
 718                         continue;
 719
 720                 *core = &priv->core_clk[i];
 721                 return 0;
 722         }
 723
 724         return -ENODEV;
 725 }
 726
 727 static int gen3_clk_get_parent(struct clk *clk, struct clk *parent)
 728 {
 729         const struct cpg_core_clk *core;
 730         const struct mssr_mod_clk *mssr;
 731         int ret;
 732
 733         if (gen3_clk_is_mod(clk)) {
 734                 ret = gen3_clk_get_mod(clk, &mssr);
 735                 if (ret)
 736                         return ret;
 737
 738                 parent->id = mssr->parent;
 739         } else {
 740                 ret = gen3_clk_get_core(clk, &core);
 741                 if (ret)
 742                         return ret;
 743
 744                 if (core->type == CLK_TYPE_IN)
 745                         parent->id = ~0;        /* Top-level clock */
 746                 else
 747                         parent->id = core->parent;
 748         }
 749
 750         parent->dev = clk->dev;
 751
 752         return 0;
 753 }
 754
 755 static int gen3_clk_endisable(struct clk *clk, bool enable)
 756 {
 757         struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
 758         const unsigned long clkid = clk->id & 0xffff;
 759         const unsigned int reg = clkid / 100;
 760         const unsigned int bit = clkid % 100;
 761         const u32 bitmask = BIT(bit);
 762
 763         if (!gen3_clk_is_mod(clk))
 764                 return -EINVAL;
 765
 766         debug("%s[%i] MSTP %lu=%02u/%02u %s\n", __func__, __LINE__,
 767               clkid, reg, bit, enable ? "ON" : "OFF");
 768
 769         if (enable) {
 770                 clrbits_le32(priv->base + SMSTPCR(reg), bitmask);
 771                 return wait_for_bit("MSTP", priv->base + MSTPSR(reg),
 772                                     bitmask, 0, 100, 0);
 773         } else {
 774                 setbits_le32(priv->base + SMSTPCR(reg), bitmask);
 775                 return 0;
 776         }
 777 }
 778
 779 static int gen3_clk_enable(struct clk *clk)
 780 {
 781         return gen3_clk_endisable(clk, true);
 782 }
 783
 784 static int gen3_clk_disable(struct clk *clk)
 785 {
 786         return gen3_clk_endisable(clk, false);
 787 }
 788
 789 static ulong gen3_clk_get_rate(struct clk *clk)
 790 {
 791         struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
 792         struct clk parent;
 793         const struct cpg_core_clk *core;
 794         const struct rcar_gen3_cpg_pll_config *pll_config =
 795                                         priv->cpg_pll_config;
 796         u32 value, mult, rate = 0;
 797         int i, ret;
 798
 799         debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id);
 800
 801         ret = gen3_clk_get_parent(clk, &parent);
 802         if (ret) {
 803                 printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
 804                 return ret;
 805         }
 806
 807         if (gen3_clk_is_mod(clk)) {
 808                 rate = gen3_clk_get_rate(&parent);
 809                 debug("%s[%i] MOD clk: parent=%lu => rate=%u\n",
 810                       __func__, __LINE__, parent.id, rate);
 811                 return rate;
 812         }
 813
 814         ret = gen3_clk_get_core(clk, &core);
 815         if (ret)
 816                 return ret;
 817
 818         switch (core->type) {
 819         case CLK_TYPE_IN:
 820                 if (core->id == CLK_EXTAL) {
 821                         rate = clk_get_rate(&priv->clk_extal);
 822                         debug("%s[%i] EXTAL clk: rate=%u\n",
 823                               __func__, __LINE__, rate);
 824                         return rate;
 825                 }
 826
 827                 if (core->id == CLK_EXTALR) {
 828                         rate = clk_get_rate(&priv->clk_extalr);
 829                         debug("%s[%i] EXTALR clk: rate=%u\n",
 830                               __func__, __LINE__, rate);
 831                         return rate;
 832                 }
 833
 834                 return -EINVAL;
 835
 836         case CLK_TYPE_GEN3_MAIN:
 837                 rate = gen3_clk_get_rate(&parent) / pll_config->extal_div;
 838                 debug("%s[%i] MAIN clk: parent=%i extal_div=%i => rate=%u\n",
 839                       __func__, __LINE__,
 840                       core->parent, pll_config->extal_div, rate);
 841                 return rate;
 842
 843         case CLK_TYPE_GEN3_PLL0:
 844                 value = readl(priv->base + CPG_PLL0CR);
 845                 mult = (((value >> 24) & 0x7f) + 1) * 2;
 846                 rate = gen3_clk_get_rate(&parent) * mult;
 847                 debug("%s[%i] PLL0 clk: parent=%i mult=%u => rate=%u\n",
 848                       __func__, __LINE__, core->parent, mult, rate);
 849                 return rate;
 850
 851         case CLK_TYPE_GEN3_PLL1:
 852                 rate = gen3_clk_get_rate(&parent) * pll_config->pll1_mult;
 853                 debug("%s[%i] PLL1 clk: parent=%i mul=%i => rate=%u\n",
 854                       __func__, __LINE__,
 855                       core->parent, pll_config->pll1_mult, rate);
 856                 return rate;
 857
 858         case CLK_TYPE_GEN3_PLL2:
 859                 value = readl(priv->base + CPG_PLL2CR);
 860                 mult = (((value >> 24) & 0x7f) + 1) * 2;
 861                 rate = gen3_clk_get_rate(&parent) * mult;
 862                 debug("%s[%i] PLL2 clk: parent=%i mult=%u => rate=%u\n",
 863                       __func__, __LINE__, core->parent, mult, rate);
 864                 return rate;
 865
 866         case CLK_TYPE_GEN3_PLL3:
 867                 rate = gen3_clk_get_rate(&parent) * pll_config->pll3_mult;
 868                 debug("%s[%i] PLL3 clk: parent=%i mul=%i => rate=%u\n",
 869                       __func__, __LINE__,
 870                       core->parent, pll_config->pll3_mult, rate);
 871                 return rate;
 872
 873         case CLK_TYPE_GEN3_PLL4:
 874                 value = readl(priv->base + CPG_PLL4CR);
 875                 mult = (((value >> 24) & 0x7f) + 1) * 2;
 876                 rate = gen3_clk_get_rate(&parent) * mult;
 877                 debug("%s[%i] PLL4 clk: parent=%i mult=%u => rate=%u\n",
 878                       __func__, __LINE__, core->parent, mult, rate);
 879                 return rate;
 880
 881         case CLK_TYPE_FF:
 882                 rate = (gen3_clk_get_rate(&parent) * core->mult) / core->div;
 883                 debug("%s[%i] FIXED clk: parent=%i div=%i mul=%i => rate=%u\n",
 884                       __func__, __LINE__,
 885                       core->parent, core->mult, core->div, rate);
 886                 return rate;
 887
 888         case CLK_TYPE_GEN3_SD:          /* FIXME */
 889                 value = readl(priv->base + core->offset);
 890                 value &= CPG_SD_STP_MASK | CPG_SD_FC_MASK;
 891
 892                 for (i = 0; i < ARRAY_SIZE(cpg_sd_div_table); i++) {
 893                         if (cpg_sd_div_table[i].val != value)
 894                                 continue;
 895
 896                         rate = gen3_clk_get_rate(&parent) /
 897                                cpg_sd_div_table[i].div;
 898                         debug("%s[%i] SD clk: parent=%i div=%i => rate=%u\n",
 899                               __func__, __LINE__,
 900                               core->parent, cpg_sd_div_table[i].div, rate);
 901
 902                         return rate;
 903                 }
 904
 905                 return -EINVAL;
 906         }
 907
 908         printf("%s[%i] unknown fail\n", __func__, __LINE__);
 909
 910         return -ENOENT;
 911 }
 912
 913 static ulong gen3_clk_set_rate(struct clk *clk, ulong rate)
 914 {
 915         return gen3_clk_get_rate(clk);
 916 }
 917
 918 static int gen3_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
 919 {
 920         if (args->args_count != 2) {
 921                 debug("Invaild args_count: %d\n", args->args_count);
 922                 return -EINVAL;
 923         }
 924
 925         clk->id = (args->args[0] << 16) | args->args[1];
 926
 927         return 0;
 928 }
 929
 930 static const struct clk_ops gen3_clk_ops = {
 931         .enable         = gen3_clk_enable,
 932         .disable        = gen3_clk_disable,
 933         .get_rate       = gen3_clk_get_rate,
 934         .set_rate       = gen3_clk_set_rate,
 935         .of_xlate       = gen3_clk_of_xlate,
 936 };
 937
 938 enum gen3_clk_model {
 939         CLK_R8A7795,
 940         CLK_R8A7796,
 941 };
 942
 943 static int gen3_clk_probe(struct udevice *dev)
 944 {
 945         struct gen3_clk_priv *priv = dev_get_priv(dev);
 946         enum gen3_clk_model model = dev_get_driver_data(dev);
 947         fdt_addr_t rst_base;
 948         u32 cpg_mode;
 949         int ret;
 950
 951         priv->base = (struct gen3_base *)devfdt_get_addr(dev);
 952         if (!priv->base)
 953                 return -EINVAL;
 954
 955         switch (model) {
 956         case CLK_R8A7795:
 957                 priv->core_clk = r8a7795_core_clks;
 958                 priv->core_clk_size = ARRAY_SIZE(r8a7795_core_clks);
 959                 priv->mod_clk = r8a7795_mod_clks;
 960                 priv->mod_clk_size = ARRAY_SIZE(r8a7795_mod_clks);
 961                 ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
 962                                                     "renesas,r8a7795-rst");
 963                 if (ret < 0)
 964                         return ret;
 965                 break;
 966         case CLK_R8A7796:
 967                 priv->core_clk = r8a7796_core_clks;
 968                 priv->core_clk_size = ARRAY_SIZE(r8a7796_core_clks);
 969                 priv->mod_clk = r8a7796_mod_clks;
 970                 priv->mod_clk_size = ARRAY_SIZE(r8a7796_mod_clks);
 971                 ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
 972                                                     "renesas,r8a7796-rst");
 973                 if (ret < 0)
 974                         return ret;
 975                 break;
 976         default:
 977                 return -EINVAL;
 978         }
 979
 980         rst_base = fdtdec_get_addr(gd->fdt_blob, ret, "reg");
 981         if (rst_base == FDT_ADDR_T_NONE)
 982                 return -EINVAL;
 983
 984         cpg_mode = readl(rst_base + CPG_RST_MODEMR);
 985
 986         priv->cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
 987         if (!priv->cpg_pll_config->extal_div)
 988                 return -EINVAL;
 989
 990         ret = clk_get_by_name(dev, "extal", &priv->clk_extal);
 991         if (ret < 0)
 992                 return ret;
 993
 994         ret = clk_get_by_name(dev, "extalr", &priv->clk_extalr);
 995         if (ret < 0)
 996                 return ret;
 997
 998         return 0;
 999 }
1000
1001 static const struct udevice_id gen3_clk_ids[] = {
1002         { .compatible = "renesas,r8a7795-cpg-mssr", .data = CLK_R8A7795 },
1003         { .compatible = "renesas,r8a7796-cpg-mssr", .data = CLK_R8A7796 },
1004         { }
1005 };
1006
1007 U_BOOT_DRIVER(clk_gen3) = {
1008         .name           = "clk_gen3",
1009         .id             = UCLASS_CLK,
1010         .of_match       = gen3_clk_ids,
1011         .priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
1012         .ops            = &gen3_clk_ops,
1013         .probe          = gen3_clk_probe,
1014 };