drivers/clk/renesas/clk-rcar-gen2.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Renesas RCar Gen2 CPG MSSR driver
   4  *
   5  * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
   6  *
   7  * Based on the following driver from Linux kernel:
   8  * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
   9  *
  10  * Copyright (C) 2016 Glider bvba
  11  */
  12
  13 #include <common.h>
  14 #include <clk-uclass.h>
  15 #include <dm.h>
  16 #include <errno.h>
  17 #include <log.h>
  18 #include <asm/io.h>
  19
  20 #include <dt-bindings/clock/renesas-cpg-mssr.h>
  21
  22 #include "renesas-cpg-mssr.h"
  23 #include "rcar-gen2-cpg.h"
  24
  25 #define CPG_RST_MODEMR          0x0060
  26
  27 #define CPG_PLL0CR              0x00d8
  28 #define CPG_SDCKCR              0x0074
  29
  30 struct clk_div_table {
  31         u8      val;
  32         u8      div;
  33 };
  34
  35 /* SDHI divisors */
  36 static const struct clk_div_table cpg_sdh_div_table[] = {
  37         {  0,  2 }, {  1,  3 }, {  2,  4 }, {  3,  6 },
  38         {  4,  8 }, {  5, 12 }, {  6, 16 }, {  7, 18 },
  39         {  8, 24 }, { 10, 36 }, { 11, 48 }, {  0,  0 },
  40 };
  41
  42 static const struct clk_div_table cpg_sd01_div_table[] = {
  43         {  4,  8 }, {  5, 12 }, {  6, 16 }, {  7, 18 },
  44         {  8, 24 }, { 10, 36 }, { 11, 48 }, { 12, 10 },
  45         {  0,  0 },
  46 };
  47
  48 static u8 gen2_clk_get_sdh_div(const struct clk_div_table *table, u8 val)
  49 {
  50         for (;;) {
  51                 if (!(*table).div)
  52                         return 0xff;
  53
  54                 if ((*table).val == val)
  55                         return (*table).div;
  56
  57                 table++;
  58         }
  59 }
  60
  61 static int gen2_clk_enable(struct clk *clk)
  62 {
  63         struct gen2_clk_priv *priv = dev_get_priv(clk->dev);
  64
  65         return renesas_clk_endisable(clk, priv->base, true);
  66 }
  67
  68 static int gen2_clk_disable(struct clk *clk)
  69 {
  70         struct gen2_clk_priv *priv = dev_get_priv(clk->dev);
  71
  72         return renesas_clk_endisable(clk, priv->base, false);
  73 }
  74
  75 static ulong gen2_clk_get_rate(struct clk *clk)
  76 {
  77         struct gen2_clk_priv *priv = dev_get_priv(clk->dev);
  78         struct cpg_mssr_info *info = priv->info;
  79         struct clk parent;
  80         const struct cpg_core_clk *core;
  81         const struct rcar_gen2_cpg_pll_config *pll_config =
  82                                         priv->cpg_pll_config;
  83         u32 value, mult, div, rate = 0;
  84         int ret;
  85
  86         debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id);
  87
  88         ret = renesas_clk_get_parent(clk, info, &parent);
  89         if (ret) {
  90                 printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
  91                 return ret;
  92         }
  93
  94         if (renesas_clk_is_mod(clk)) {
  95                 rate = gen2_clk_get_rate(&parent);
  96                 debug("%s[%i] MOD clk: parent=%lu => rate=%u\n",
  97                       __func__, __LINE__, parent.id, rate);
  98                 return rate;
  99         }
 100
 101         ret = renesas_clk_get_core(clk, info, &core);
 102         if (ret)
 103                 return ret;
 104
 105         switch (core->type) {
 106         case CLK_TYPE_IN:
 107                 if (core->id == info->clk_extal_id) {
 108                         rate = clk_get_rate(&priv->clk_extal);
 109                         debug("%s[%i] EXTAL clk: rate=%u\n",
 110                               __func__, __LINE__, rate);
 111                         return rate;
 112                 }
 113
 114                 if (core->id == info->clk_extal_usb_id) {
 115                         rate = clk_get_rate(&priv->clk_extal_usb);
 116                         debug("%s[%i] EXTALR clk: rate=%u\n",
 117                               __func__, __LINE__, rate);
 118                         return rate;
 119                 }
 120
 121                 return -EINVAL;
 122
 123         case CLK_TYPE_FF:
 124                 rate = (gen2_clk_get_rate(&parent) * core->mult) / core->div;
 125                 debug("%s[%i] FIXED clk: parent=%i mul=%i div=%i => rate=%u\n",
 126                       __func__, __LINE__,
 127                       core->parent, core->mult, core->div, rate);
 128                 return rate;
 129
 130         case CLK_TYPE_DIV6P1:   /* DIV6 Clock with 1 parent clock */
 131                 value = (readl(priv->base + core->offset) & 0x3f) + 1;
 132                 rate = gen2_clk_get_rate(&parent) / value;
 133                 debug("%s[%i] DIV6P1 clk: parent=%i div=%i => rate=%u\n",
 134                       __func__, __LINE__,
 135                       core->parent, value, rate);
 136                 return rate;
 137
 138         case CLK_TYPE_GEN2_MAIN:
 139                 rate = gen2_clk_get_rate(&parent) / pll_config->extal_div;
 140                 debug("%s[%i] MAIN clk: parent=%i extal_div=%i => rate=%u\n",
 141                       __func__, __LINE__,
 142                       core->parent, pll_config->extal_div, rate);
 143                 return rate;
 144
 145         case CLK_TYPE_GEN2_PLL0:
 146                 /*
 147                  * PLL0 is a  configurable multiplier clock except on R-Car
 148                  * V2H/E2. Register the PLL0 clock as a fixed factor clock for
 149                  * now as there's no generic multiplier clock implementation and
 150                  * we  currently  have no need to change  the multiplier value.
 151                  */
 152                 mult = pll_config->pll0_mult;
 153                 if (!mult) {
 154                         value = readl(priv->base + CPG_PLL0CR);
 155                         mult = (((value >> 24) & 0x7f) + 1) * 2;
 156                 }
 157
 158                 rate = (gen2_clk_get_rate(&parent) * mult) / info->pll0_div;
 159                 debug("%s[%i] PLL0 clk: parent=%i mult=%u => rate=%u\n",
 160                       __func__, __LINE__, core->parent, mult, rate);
 161                 return rate;
 162
 163         case CLK_TYPE_GEN2_PLL1:
 164                 rate = (gen2_clk_get_rate(&parent) * pll_config->pll1_mult) / 2;
 165                 debug("%s[%i] PLL1 clk: parent=%i mul=%i => rate=%u\n",
 166                       __func__, __LINE__,
 167                       core->parent, pll_config->pll1_mult, rate);
 168                 return rate;
 169
 170         case CLK_TYPE_GEN2_PLL3:
 171                 rate = gen2_clk_get_rate(&parent) * pll_config->pll3_mult;
 172                 debug("%s[%i] PLL3 clk: parent=%i mul=%i => rate=%u\n",
 173                       __func__, __LINE__,
 174                       core->parent, pll_config->pll3_mult, rate);
 175                 return rate;
 176
 177         case CLK_TYPE_GEN2_SDH:
 178                 value = (readl(priv->base + CPG_SDCKCR) >> 8) & 0xf;
 179                 div = gen2_clk_get_sdh_div(cpg_sdh_div_table, value);
 180                 rate = gen2_clk_get_rate(&parent) / div;
 181                 debug("%s[%i] SDH clk: parent=%i div=%i => rate=%u\n",
 182                       __func__, __LINE__,
 183                       core->parent, div, rate);
 184                 return rate;
 185
 186         case CLK_TYPE_GEN2_SD0:
 187                 value = (readl(priv->base + CPG_SDCKCR) >> 4) & 0xf;
 188                 div = gen2_clk_get_sdh_div(cpg_sd01_div_table, value);
 189                 rate = gen2_clk_get_rate(&parent) / div;
 190                 debug("%s[%i] SD0 clk: parent=%i div=%i => rate=%u\n",
 191                       __func__, __LINE__,
 192                       core->parent, div, rate);
 193                 return rate;
 194
 195         case CLK_TYPE_GEN2_SD1:
 196                 value = (readl(priv->base + CPG_SDCKCR) >> 0) & 0xf;
 197                 div = gen2_clk_get_sdh_div(cpg_sd01_div_table, value);
 198                 rate = gen2_clk_get_rate(&parent) / div;
 199                 debug("%s[%i] SD1 clk: parent=%i div=%i => rate=%u\n",
 200                       __func__, __LINE__,
 201                       core->parent, div, rate);
 202                 return rate;
 203         }
 204
 205         printf("%s[%i] unknown fail\n", __func__, __LINE__);
 206
 207         return -ENOENT;
 208 }
 209
 210 static int gen2_clk_setup_mmcif_div(struct clk *clk, ulong rate)
 211 {
 212         struct gen2_clk_priv *priv = dev_get_priv(clk->dev);
 213         struct cpg_mssr_info *info = priv->info;
 214         const struct cpg_core_clk *core;
 215         struct clk parent, pparent;
 216         u32 val;
 217         int ret;
 218
 219         ret = renesas_clk_get_parent(clk, info, &parent);
 220         if (ret) {
 221                 debug("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
 222                 return ret;
 223         }
 224
 225         if (renesas_clk_is_mod(&parent))
 226                 return 0;
 227
 228         ret = renesas_clk_get_core(&parent, info, &core);
 229         if (ret)
 230                 return ret;
 231
 232         if (strcmp(core->name, "mmc0") && strcmp(core->name, "mmc1"))
 233                 return 0;
 234
 235         ret = renesas_clk_get_parent(&parent, info, &pparent);
 236         if (ret) {
 237                 debug("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
 238                 return ret;
 239         }
 240
 241         val = (gen2_clk_get_rate(&pparent) / rate) - 1;
 242
 243         debug("%s[%i] MMCIF offset=%x\n", __func__, __LINE__, core->offset);
 244
 245         writel(val, priv->base + core->offset);
 246
 247         return 0;
 248 }
 249
 250 static ulong gen2_clk_set_rate(struct clk *clk, ulong rate)
 251 {
 252         /* Force correct MMC-IF divider configuration if applicable */
 253         gen2_clk_setup_mmcif_div(clk, rate);
 254         return gen2_clk_get_rate(clk);
 255 }
 256
 257 static int gen2_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
 258 {
 259         if (args->args_count != 2) {
 260                 debug("Invaild args_count: %d\n", args->args_count);
 261                 return -EINVAL;
 262         }
 263
 264         clk->id = (args->args[0] << 16) | args->args[1];
 265
 266         return 0;
 267 }
 268
 269 const struct clk_ops gen2_clk_ops = {
 270         .enable         = gen2_clk_enable,
 271         .disable        = gen2_clk_disable,
 272         .get_rate       = gen2_clk_get_rate,
 273         .set_rate       = gen2_clk_set_rate,
 274         .of_xlate       = gen2_clk_of_xlate,
 275 };
 276
 277 int gen2_clk_probe(struct udevice *dev)
 278 {
 279         struct gen2_clk_priv *priv = dev_get_priv(dev);
 280         struct cpg_mssr_info *info =
 281                 (struct cpg_mssr_info *)dev_get_driver_data(dev);
 282         fdt_addr_t rst_base;
 283         u32 cpg_mode;
 284         int ret;
 285
 286         priv->base = (struct gen2_base *)devfdt_get_addr(dev);
 287         if (!priv->base)
 288                 return -EINVAL;
 289
 290         priv->info = info;
 291         ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1, info->reset_node);
 292         if (ret < 0)
 293                 return ret;
 294
 295         rst_base = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, ret, "reg",
 296                                                       0, NULL, false);
 297         if (rst_base == FDT_ADDR_T_NONE)
 298                 return -EINVAL;
 299
 300         cpg_mode = readl(rst_base + CPG_RST_MODEMR);
 301
 302         priv->cpg_pll_config =
 303                 (struct rcar_gen2_cpg_pll_config *)info->get_pll_config(cpg_mode);
 304         if (!priv->cpg_pll_config->extal_div)
 305                 return -EINVAL;
 306
 307         ret = clk_get_by_name(dev, "extal", &priv->clk_extal);
 308         if (ret < 0)
 309                 return ret;
 310
 311         if (info->extal_usb_node) {
 312                 ret = clk_get_by_name(dev, info->extal_usb_node,
 313                                       &priv->clk_extal_usb);
 314                 if (ret < 0)
 315                         return ret;
 316         }
 317
 318         return 0;
 319 }
 320
 321 int gen2_clk_remove(struct udevice *dev)
 322 {
 323         struct gen2_clk_priv *priv = dev_get_priv(dev);
 324
 325         return renesas_clk_remove(priv->base, priv->info);
 326 }