drivers/clk/qcom/gcc-ipq8074.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/err.h>
   8 #include <linux/platform_device.h>
   9 #include <linux/module.h>
  10 #include <linux/of.h>
  11 #include <linux/of_device.h>
  12 #include <linux/clk-provider.h>
  13 #include <linux/regmap.h>
  14
  15 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
  16
  17 #include "common.h"
  18 #include "clk-regmap.h"
  19 #include "clk-pll.h"
  20 #include "clk-rcg.h"
  21 #include "clk-branch.h"
  22 #include "clk-alpha-pll.h"
  23 #include "clk-regmap-divider.h"
  24 #include "clk-regmap-mux.h"
  25 #include "reset.h"
  26
  27 enum {
  28         P_XO,
  29         P_GPLL0,
  30         P_GPLL0_DIV2,
  31         P_GPLL2,
  32         P_GPLL4,
  33         P_GPLL6,
  34         P_SLEEP_CLK,
  35         P_PCIE20_PHY0_PIPE,
  36         P_PCIE20_PHY1_PIPE,
  37         P_USB3PHY_0_PIPE,
  38         P_USB3PHY_1_PIPE,
  39         P_UBI32_PLL,
  40         P_NSS_CRYPTO_PLL,
  41         P_BIAS_PLL,
  42         P_BIAS_PLL_NSS_NOC,
  43         P_UNIPHY0_RX,
  44         P_UNIPHY0_TX,
  45         P_UNIPHY1_RX,
  46         P_UNIPHY1_TX,
  47         P_UNIPHY2_RX,
  48         P_UNIPHY2_TX,
  49 };
  50
  51 static const char * const gcc_xo_gpll0_gpll0_out_main_div2[] = {
  52         "xo",
  53         "gpll0",
  54         "gpll0_out_main_div2",
  55 };
  56
  57 static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
  58         { P_XO, 0 },
  59         { P_GPLL0, 1 },
  60         { P_GPLL0_DIV2, 4 },
  61 };
  62
  63 static const char * const gcc_xo_gpll0[] = {
  64         "xo",
  65         "gpll0",
  66 };
  67
  68 static const struct parent_map gcc_xo_gpll0_map[] = {
  69         { P_XO, 0 },
  70         { P_GPLL0, 1 },
  71 };
  72
  73 static const char * const gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
  74         "xo",
  75         "gpll0",
  76         "gpll2",
  77         "gpll0_out_main_div2",
  78 };
  79
  80 static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
  81         { P_XO, 0 },
  82         { P_GPLL0, 1 },
  83         { P_GPLL2, 2 },
  84         { P_GPLL0_DIV2, 4 },
  85 };
  86
  87 static const char * const gcc_xo_gpll0_sleep_clk[] = {
  88         "xo",
  89         "gpll0",
  90         "sleep_clk",
  91 };
  92
  93 static const struct parent_map gcc_xo_gpll0_sleep_clk_map[] = {
  94         { P_XO, 0 },
  95         { P_GPLL0, 2 },
  96         { P_SLEEP_CLK, 6 },
  97 };
  98
  99 static const char * const gcc_xo_gpll6_gpll0_gpll0_out_main_div2[] = {
 100         "xo",
 101         "gpll6",
 102         "gpll0",
 103         "gpll0_out_main_div2",
 104 };
 105
 106 static const struct parent_map gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map[] = {
 107         { P_XO, 0 },
 108         { P_GPLL6, 1 },
 109         { P_GPLL0, 3 },
 110         { P_GPLL0_DIV2, 4 },
 111 };
 112
 113 static const char * const gcc_xo_gpll0_out_main_div2_gpll0[] = {
 114         "xo",
 115         "gpll0_out_main_div2",
 116         "gpll0",
 117 };
 118
 119 static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
 120         { P_XO, 0 },
 121         { P_GPLL0_DIV2, 2 },
 122         { P_GPLL0, 1 },
 123 };
 124
 125 static const char * const gcc_usb3phy_0_cc_pipe_clk_xo[] = {
 126         "usb3phy_0_cc_pipe_clk",
 127         "xo",
 128 };
 129
 130 static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
 131         { P_USB3PHY_0_PIPE, 0 },
 132         { P_XO, 2 },
 133 };
 134
 135 static const char * const gcc_usb3phy_1_cc_pipe_clk_xo[] = {
 136         "usb3phy_1_cc_pipe_clk",
 137         "xo",
 138 };
 139
 140 static const struct parent_map gcc_usb3phy_1_cc_pipe_clk_xo_map[] = {
 141         { P_USB3PHY_1_PIPE, 0 },
 142         { P_XO, 2 },
 143 };
 144
 145 static const char * const gcc_pcie20_phy0_pipe_clk_xo[] = {
 146         "pcie20_phy0_pipe_clk",
 147         "xo",
 148 };
 149
 150 static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = {
 151         { P_PCIE20_PHY0_PIPE, 0 },
 152         { P_XO, 2 },
 153 };
 154
 155 static const char * const gcc_pcie20_phy1_pipe_clk_xo[] = {
 156         "pcie20_phy1_pipe_clk",
 157         "xo",
 158 };
 159
 160 static const struct parent_map gcc_pcie20_phy1_pipe_clk_xo_map[] = {
 161         { P_PCIE20_PHY1_PIPE, 0 },
 162         { P_XO, 2 },
 163 };
 164
 165 static const char * const gcc_xo_gpll0_gpll6_gpll0_div2[] = {
 166         "xo",
 167         "gpll0",
 168         "gpll6",
 169         "gpll0_out_main_div2",
 170 };
 171
 172 static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_div2_map[] = {
 173         { P_XO, 0 },
 174         { P_GPLL0, 1 },
 175         { P_GPLL6, 2 },
 176         { P_GPLL0_DIV2, 4 },
 177 };
 178
 179 static const char * const gcc_xo_gpll0_gpll6_gpll0_out_main_div2[] = {
 180         "xo",
 181         "gpll0",
 182         "gpll6",
 183         "gpll0_out_main_div2",
 184 };
 185
 186 static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map[] = {
 187         { P_XO, 0 },
 188         { P_GPLL0, 1 },
 189         { P_GPLL6, 2 },
 190         { P_GPLL0_DIV2, 3 },
 191 };
 192
 193 static const char * const gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
 194         "xo",
 195         "bias_pll_nss_noc_clk",
 196         "gpll0",
 197         "gpll2",
 198 };
 199
 200 static const struct parent_map gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map[] = {
 201         { P_XO, 0 },
 202         { P_BIAS_PLL_NSS_NOC, 1 },
 203         { P_GPLL0, 2 },
 204         { P_GPLL2, 3 },
 205 };
 206
 207 static const char * const gcc_xo_nss_crypto_pll_gpll0[] = {
 208         "xo",
 209         "nss_crypto_pll",
 210         "gpll0",
 211 };
 212
 213 static const struct parent_map gcc_xo_nss_crypto_pll_gpll0_map[] = {
 214         { P_XO, 0 },
 215         { P_NSS_CRYPTO_PLL, 1 },
 216         { P_GPLL0, 2 },
 217 };
 218
 219 static const char * const gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6[] = {
 220         "xo",
 221         "ubi32_pll",
 222         "gpll0",
 223         "gpll2",
 224         "gpll4",
 225         "gpll6",
 226 };
 227
 228 static const struct parent_map gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map[] = {
 229         { P_XO, 0 },
 230         { P_UBI32_PLL, 1 },
 231         { P_GPLL0, 2 },
 232         { P_GPLL2, 3 },
 233         { P_GPLL4, 4 },
 234         { P_GPLL6, 5 },
 235 };
 236
 237 static const char * const gcc_xo_gpll0_out_main_div2[] = {
 238         "xo",
 239         "gpll0_out_main_div2",
 240 };
 241
 242 static const struct parent_map gcc_xo_gpll0_out_main_div2_map[] = {
 243         { P_XO, 0 },
 244         { P_GPLL0_DIV2, 1 },
 245 };
 246
 247 static const char * const gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
 248         "xo",
 249         "bias_pll_cc_clk",
 250         "gpll0",
 251         "gpll4",
 252         "nss_crypto_pll",
 253         "ubi32_pll",
 254 };
 255
 256 static const struct parent_map gcc_xo_bias_gpll0_gpll4_nss_ubi32_map[] = {
 257         { P_XO, 0 },
 258         { P_BIAS_PLL, 1 },
 259         { P_GPLL0, 2 },
 260         { P_GPLL4, 3 },
 261         { P_NSS_CRYPTO_PLL, 4 },
 262         { P_UBI32_PLL, 5 },
 263 };
 264
 265 static const char * const gcc_xo_gpll0_gpll4[] = {
 266         "xo",
 267         "gpll0",
 268         "gpll4",
 269 };
 270
 271 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
 272         { P_XO, 0 },
 273         { P_GPLL0, 1 },
 274         { P_GPLL4, 2 },
 275 };
 276
 277 static const char * const gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
 278         "xo",
 279         "uniphy0_gcc_rx_clk",
 280         "uniphy0_gcc_tx_clk",
 281         "ubi32_pll",
 282         "bias_pll_cc_clk",
 283 };
 284
 285 static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
 286         { P_XO, 0 },
 287         { P_UNIPHY0_RX, 1 },
 288         { P_UNIPHY0_TX, 2 },
 289         { P_UBI32_PLL, 5 },
 290         { P_BIAS_PLL, 6 },
 291 };
 292
 293 static const char * const gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
 294         "xo",
 295         "uniphy0_gcc_tx_clk",
 296         "uniphy0_gcc_rx_clk",
 297         "ubi32_pll",
 298         "bias_pll_cc_clk",
 299 };
 300
 301 static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
 302         { P_XO, 0 },
 303         { P_UNIPHY0_TX, 1 },
 304         { P_UNIPHY0_RX, 2 },
 305         { P_UBI32_PLL, 5 },
 306         { P_BIAS_PLL, 6 },
 307 };
 308
 309 static const char * const gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
 310         "xo",
 311         "uniphy0_gcc_rx_clk",
 312         "uniphy0_gcc_tx_clk",
 313         "uniphy1_gcc_rx_clk",
 314         "uniphy1_gcc_tx_clk",
 315         "ubi32_pll",
 316         "bias_pll_cc_clk",
 317 };
 318
 319 static const struct parent_map
 320 gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = {
 321         { P_XO, 0 },
 322         { P_UNIPHY0_RX, 1 },
 323         { P_UNIPHY0_TX, 2 },
 324         { P_UNIPHY1_RX, 3 },
 325         { P_UNIPHY1_TX, 4 },
 326         { P_UBI32_PLL, 5 },
 327         { P_BIAS_PLL, 6 },
 328 };
 329
 330 static const char * const gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
 331         "xo",
 332         "uniphy0_gcc_tx_clk",
 333         "uniphy0_gcc_rx_clk",
 334         "uniphy1_gcc_tx_clk",
 335         "uniphy1_gcc_rx_clk",
 336         "ubi32_pll",
 337         "bias_pll_cc_clk",
 338 };
 339
 340 static const struct parent_map
 341 gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map[] = {
 342         { P_XO, 0 },
 343         { P_UNIPHY0_TX, 1 },
 344         { P_UNIPHY0_RX, 2 },
 345         { P_UNIPHY1_TX, 3 },
 346         { P_UNIPHY1_RX, 4 },
 347         { P_UBI32_PLL, 5 },
 348         { P_BIAS_PLL, 6 },
 349 };
 350
 351 static const char * const gcc_xo_uniphy2_rx_tx_ubi32_bias[] = {
 352         "xo",
 353         "uniphy2_gcc_rx_clk",
 354         "uniphy2_gcc_tx_clk",
 355         "ubi32_pll",
 356         "bias_pll_cc_clk",
 357 };
 358
 359 static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
 360         { P_XO, 0 },
 361         { P_UNIPHY2_RX, 1 },
 362         { P_UNIPHY2_TX, 2 },
 363         { P_UBI32_PLL, 5 },
 364         { P_BIAS_PLL, 6 },
 365 };
 366
 367 static const char * const gcc_xo_uniphy2_tx_rx_ubi32_bias[] = {
 368         "xo",
 369         "uniphy2_gcc_tx_clk",
 370         "uniphy2_gcc_rx_clk",
 371         "ubi32_pll",
 372         "bias_pll_cc_clk",
 373 };
 374
 375 static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {
 376         { P_XO, 0 },
 377         { P_UNIPHY2_TX, 1 },
 378         { P_UNIPHY2_RX, 2 },
 379         { P_UBI32_PLL, 5 },
 380         { P_BIAS_PLL, 6 },
 381 };
 382
 383 static const char * const gcc_xo_gpll0_gpll6_gpll0_sleep_clk[] = {
 384         "xo",
 385         "gpll0",
 386         "gpll6",
 387         "gpll0_out_main_div2",
 388         "sleep_clk",
 389 };
 390
 391 static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map[] = {
 392         { P_XO, 0 },
 393         { P_GPLL0, 1 },
 394         { P_GPLL6, 2 },
 395         { P_GPLL0_DIV2, 4 },
 396         { P_SLEEP_CLK, 6 },
 397 };
 398
 399 static struct clk_alpha_pll gpll0_main = {
 400         .offset = 0x21000,
 401         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 402         .clkr = {
 403                 .enable_reg = 0x0b000,
 404                 .enable_mask = BIT(0),
 405                 .hw.init = &(struct clk_init_data){
 406                         .name = "gpll0_main",
 407                         .parent_names = (const char *[]){
 408                                 "xo"
 409                         },
 410                         .num_parents = 1,
 411                         .ops = &clk_alpha_pll_ops,
 412                 },
 413         },
 414 };
 415
 416 static struct clk_fixed_factor gpll0_out_main_div2 = {
 417         .mult = 1,
 418         .div = 2,
 419         .hw.init = &(struct clk_init_data){
 420                 .name = "gpll0_out_main_div2",
 421                 .parent_names = (const char *[]){
 422                         "gpll0_main"
 423                 },
 424                 .num_parents = 1,
 425                 .ops = &clk_fixed_factor_ops,
 426                 .flags = CLK_SET_RATE_PARENT,
 427         },
 428 };
 429
 430 static struct clk_alpha_pll_postdiv gpll0 = {
 431         .offset = 0x21000,
 432         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 433         .width = 4,
 434         .clkr.hw.init = &(struct clk_init_data){
 435                 .name = "gpll0",
 436                 .parent_names = (const char *[]){
 437                         "gpll0_main"
 438                 },
 439                 .num_parents = 1,
 440                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 441         },
 442 };
 443
 444 static struct clk_alpha_pll gpll2_main = {
 445         .offset = 0x4a000,
 446         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 447         .clkr = {
 448                 .enable_reg = 0x0b000,
 449                 .enable_mask = BIT(2),
 450                 .hw.init = &(struct clk_init_data){
 451                         .name = "gpll2_main",
 452                         .parent_names = (const char *[]){
 453                                 "xo"
 454                         },
 455                         .num_parents = 1,
 456                         .ops = &clk_alpha_pll_ops,
 457                         .flags = CLK_IS_CRITICAL,
 458                 },
 459         },
 460 };
 461
 462 static struct clk_alpha_pll_postdiv gpll2 = {
 463         .offset = 0x4a000,
 464         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 465         .width = 4,
 466         .clkr.hw.init = &(struct clk_init_data){
 467                 .name = "gpll2",
 468                 .parent_names = (const char *[]){
 469                         "gpll2_main"
 470                 },
 471                 .num_parents = 1,
 472                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 473                 .flags = CLK_SET_RATE_PARENT,
 474         },
 475 };
 476
 477 static struct clk_alpha_pll gpll4_main = {
 478         .offset = 0x24000,
 479         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 480         .clkr = {
 481                 .enable_reg = 0x0b000,
 482                 .enable_mask = BIT(5),
 483                 .hw.init = &(struct clk_init_data){
 484                         .name = "gpll4_main",
 485                         .parent_names = (const char *[]){
 486                                 "xo"
 487                         },
 488                         .num_parents = 1,
 489                         .ops = &clk_alpha_pll_ops,
 490                         .flags = CLK_IS_CRITICAL,
 491                 },
 492         },
 493 };
 494
 495 static struct clk_alpha_pll_postdiv gpll4 = {
 496         .offset = 0x24000,
 497         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 498         .width = 4,
 499         .clkr.hw.init = &(struct clk_init_data){
 500                 .name = "gpll4",
 501                 .parent_names = (const char *[]){
 502                         "gpll4_main"
 503                 },
 504                 .num_parents = 1,
 505                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 506                 .flags = CLK_SET_RATE_PARENT,
 507         },
 508 };
 509
 510 static struct clk_alpha_pll gpll6_main = {
 511         .offset = 0x37000,
 512         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO],
 513         .flags = SUPPORTS_DYNAMIC_UPDATE,
 514         .clkr = {
 515                 .enable_reg = 0x0b000,
 516                 .enable_mask = BIT(7),
 517                 .hw.init = &(struct clk_init_data){
 518                         .name = "gpll6_main",
 519                         .parent_names = (const char *[]){
 520                                 "xo"
 521                         },
 522                         .num_parents = 1,
 523                         .ops = &clk_alpha_pll_ops,
 524                         .flags = CLK_IS_CRITICAL,
 525                 },
 526         },
 527 };
 528
 529 static struct clk_alpha_pll_postdiv gpll6 = {
 530         .offset = 0x37000,
 531         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO],
 532         .width = 2,
 533         .clkr.hw.init = &(struct clk_init_data){
 534                 .name = "gpll6",
 535                 .parent_names = (const char *[]){
 536                         "gpll6_main"
 537                 },
 538                 .num_parents = 1,
 539                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 540                 .flags = CLK_SET_RATE_PARENT,
 541         },
 542 };
 543
 544 static struct clk_fixed_factor gpll6_out_main_div2 = {
 545         .mult = 1,
 546         .div = 2,
 547         .hw.init = &(struct clk_init_data){
 548                 .name = "gpll6_out_main_div2",
 549                 .parent_names = (const char *[]){
 550                         "gpll6_main"
 551                 },
 552                 .num_parents = 1,
 553                 .ops = &clk_fixed_factor_ops,
 554                 .flags = CLK_SET_RATE_PARENT,
 555         },
 556 };
 557
 558 static struct clk_alpha_pll ubi32_pll_main = {
 559         .offset = 0x25000,
 560         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA],
 561         .flags = SUPPORTS_DYNAMIC_UPDATE,
 562         .clkr = {
 563                 .enable_reg = 0x0b000,
 564                 .enable_mask = BIT(6),
 565                 .hw.init = &(struct clk_init_data){
 566                         .name = "ubi32_pll_main",
 567                         .parent_names = (const char *[]){
 568                                 "xo"
 569                         },
 570                         .num_parents = 1,
 571                         .ops = &clk_alpha_pll_huayra_ops,
 572                 },
 573         },
 574 };
 575
 576 static struct clk_alpha_pll_postdiv ubi32_pll = {
 577         .offset = 0x25000,
 578         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA],
 579         .width = 2,
 580         .clkr.hw.init = &(struct clk_init_data){
 581                 .name = "ubi32_pll",
 582                 .parent_names = (const char *[]){
 583                         "ubi32_pll_main"
 584                 },
 585                 .num_parents = 1,
 586                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 587                 .flags = CLK_SET_RATE_PARENT,
 588         },
 589 };
 590
 591 static struct clk_alpha_pll nss_crypto_pll_main = {
 592         .offset = 0x22000,
 593         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 594         .clkr = {
 595                 .enable_reg = 0x0b000,
 596                 .enable_mask = BIT(4),
 597                 .hw.init = &(struct clk_init_data){
 598                         .name = "nss_crypto_pll_main",
 599                         .parent_names = (const char *[]){
 600                                 "xo"
 601                         },
 602                         .num_parents = 1,
 603                         .ops = &clk_alpha_pll_ops,
 604                 },
 605         },
 606 };
 607
 608 static struct clk_alpha_pll_postdiv nss_crypto_pll = {
 609         .offset = 0x22000,
 610         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 611         .width = 4,
 612         .clkr.hw.init = &(struct clk_init_data){
 613                 .name = "nss_crypto_pll",
 614                 .parent_names = (const char *[]){
 615                         "nss_crypto_pll_main"
 616                 },
 617                 .num_parents = 1,
 618                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 619                 .flags = CLK_SET_RATE_PARENT,
 620         },
 621 };
 622
 623 static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = {
 624         F(19200000, P_XO, 1, 0, 0),
 625         F(50000000, P_GPLL0, 16, 0, 0),
 626         F(100000000, P_GPLL0, 8, 0, 0),
 627         { }
 628 };
 629
 630 static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
 631         .cmd_rcgr = 0x27000,
 632         .freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
 633         .hid_width = 5,
 634         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 635         .clkr.hw.init = &(struct clk_init_data){
 636                 .name = "pcnoc_bfdcd_clk_src",
 637                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 638                 .num_parents = 3,
 639                 .ops = &clk_rcg2_ops,
 640                 .flags = CLK_IS_CRITICAL,
 641         },
 642 };
 643
 644 static struct clk_fixed_factor pcnoc_clk_src = {
 645         .mult = 1,
 646         .div = 1,
 647         .hw.init = &(struct clk_init_data){
 648                 .name = "pcnoc_clk_src",
 649                 .parent_names = (const char *[]){
 650                         "pcnoc_bfdcd_clk_src"
 651                 },
 652                 .num_parents = 1,
 653                 .ops = &clk_fixed_factor_ops,
 654                 .flags = CLK_SET_RATE_PARENT,
 655         },
 656 };
 657
 658 static struct clk_branch gcc_sleep_clk_src = {
 659         .halt_reg = 0x30000,
 660         .clkr = {
 661                 .enable_reg = 0x30000,
 662                 .enable_mask = BIT(1),
 663                 .hw.init = &(struct clk_init_data){
 664                         .name = "gcc_sleep_clk_src",
 665                         .parent_names = (const char *[]){
 666                                 "sleep_clk"
 667                         },
 668                         .num_parents = 1,
 669                         .ops = &clk_branch2_ops,
 670                 },
 671         },
 672 };
 673
 674 static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = {
 675         F(19200000, P_XO, 1, 0, 0),
 676         F(25000000, P_GPLL0_DIV2, 16, 0, 0),
 677         F(50000000, P_GPLL0, 16, 0, 0),
 678         { }
 679 };
 680
 681 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 682         .cmd_rcgr = 0x0200c,
 683         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 684         .hid_width = 5,
 685         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 686         .clkr.hw.init = &(struct clk_init_data){
 687                 .name = "blsp1_qup1_i2c_apps_clk_src",
 688                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 689                 .num_parents = 3,
 690                 .ops = &clk_rcg2_ops,
 691         },
 692 };
 693
 694 static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = {
 695         F(960000, P_XO, 10, 1, 2),
 696         F(4800000, P_XO, 4, 0, 0),
 697         F(9600000, P_XO, 2, 0, 0),
 698         F(12500000, P_GPLL0_DIV2, 16, 1, 2),
 699         F(16000000, P_GPLL0, 10, 1, 5),
 700         F(19200000, P_XO, 1, 0, 0),
 701         F(25000000, P_GPLL0, 16, 1, 2),
 702         F(50000000, P_GPLL0, 16, 0, 0),
 703         { }
 704 };
 705
 706 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 707         .cmd_rcgr = 0x02024,
 708         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 709         .mnd_width = 8,
 710         .hid_width = 5,
 711         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 712         .clkr.hw.init = &(struct clk_init_data){
 713                 .name = "blsp1_qup1_spi_apps_clk_src",
 714                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 715                 .num_parents = 3,
 716                 .ops = &clk_rcg2_ops,
 717         },
 718 };
 719
 720 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 721         .cmd_rcgr = 0x03000,
 722         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 723         .hid_width = 5,
 724         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 725         .clkr.hw.init = &(struct clk_init_data){
 726                 .name = "blsp1_qup2_i2c_apps_clk_src",
 727                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 728                 .num_parents = 3,
 729                 .ops = &clk_rcg2_ops,
 730         },
 731 };
 732
 733 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 734         .cmd_rcgr = 0x03014,
 735         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 736         .mnd_width = 8,
 737         .hid_width = 5,
 738         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 739         .clkr.hw.init = &(struct clk_init_data){
 740                 .name = "blsp1_qup2_spi_apps_clk_src",
 741                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 742                 .num_parents = 3,
 743                 .ops = &clk_rcg2_ops,
 744         },
 745 };
 746
 747 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 748         .cmd_rcgr = 0x04000,
 749         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 750         .hid_width = 5,
 751         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 752         .clkr.hw.init = &(struct clk_init_data){
 753                 .name = "blsp1_qup3_i2c_apps_clk_src",
 754                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 755                 .num_parents = 3,
 756                 .ops = &clk_rcg2_ops,
 757         },
 758 };
 759
 760 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 761         .cmd_rcgr = 0x04014,
 762         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 763         .mnd_width = 8,
 764         .hid_width = 5,
 765         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 766         .clkr.hw.init = &(struct clk_init_data){
 767                 .name = "blsp1_qup3_spi_apps_clk_src",
 768                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 769                 .num_parents = 3,
 770                 .ops = &clk_rcg2_ops,
 771         },
 772 };
 773
 774 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 775         .cmd_rcgr = 0x05000,
 776         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 777         .hid_width = 5,
 778         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 779         .clkr.hw.init = &(struct clk_init_data){
 780                 .name = "blsp1_qup4_i2c_apps_clk_src",
 781                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 782                 .num_parents = 3,
 783                 .ops = &clk_rcg2_ops,
 784         },
 785 };
 786
 787 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 788         .cmd_rcgr = 0x05014,
 789         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 790         .mnd_width = 8,
 791         .hid_width = 5,
 792         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 793         .clkr.hw.init = &(struct clk_init_data){
 794                 .name = "blsp1_qup4_spi_apps_clk_src",
 795                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 796                 .num_parents = 3,
 797                 .ops = &clk_rcg2_ops,
 798         },
 799 };
 800
 801 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 802         .cmd_rcgr = 0x06000,
 803         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 804         .hid_width = 5,
 805         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 806         .clkr.hw.init = &(struct clk_init_data){
 807                 .name = "blsp1_qup5_i2c_apps_clk_src",
 808                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 809                 .num_parents = 3,
 810                 .ops = &clk_rcg2_ops,
 811         },
 812 };
 813
 814 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 815         .cmd_rcgr = 0x06014,
 816         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 817         .mnd_width = 8,
 818         .hid_width = 5,
 819         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 820         .clkr.hw.init = &(struct clk_init_data){
 821                 .name = "blsp1_qup5_spi_apps_clk_src",
 822                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 823                 .num_parents = 3,
 824                 .ops = &clk_rcg2_ops,
 825         },
 826 };
 827
 828 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 829         .cmd_rcgr = 0x07000,
 830         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 831         .hid_width = 5,
 832         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 833         .clkr.hw.init = &(struct clk_init_data){
 834                 .name = "blsp1_qup6_i2c_apps_clk_src",
 835                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 836                 .num_parents = 3,
 837                 .ops = &clk_rcg2_ops,
 838         },
 839 };
 840
 841 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 842         .cmd_rcgr = 0x07014,
 843         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 844         .mnd_width = 8,
 845         .hid_width = 5,
 846         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 847         .clkr.hw.init = &(struct clk_init_data){
 848                 .name = "blsp1_qup6_spi_apps_clk_src",
 849                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 850                 .num_parents = 3,
 851                 .ops = &clk_rcg2_ops,
 852         },
 853 };
 854
 855 static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = {
 856         F(3686400, P_GPLL0_DIV2, 1, 144, 15625),
 857         F(7372800, P_GPLL0_DIV2, 1, 288, 15625),
 858         F(14745600, P_GPLL0_DIV2, 1, 576, 15625),
 859         F(16000000, P_GPLL0_DIV2, 5, 1, 5),
 860         F(19200000, P_XO, 1, 0, 0),
 861         F(24000000, P_GPLL0, 1, 3, 100),
 862         F(25000000, P_GPLL0, 16, 1, 2),
 863         F(32000000, P_GPLL0, 1, 1, 25),
 864         F(40000000, P_GPLL0, 1, 1, 20),
 865         F(46400000, P_GPLL0, 1, 29, 500),
 866         F(48000000, P_GPLL0, 1, 3, 50),
 867         F(51200000, P_GPLL0, 1, 8, 125),
 868         F(56000000, P_GPLL0, 1, 7, 100),
 869         F(58982400, P_GPLL0, 1, 1152, 15625),
 870         F(60000000, P_GPLL0, 1, 3, 40),
 871         F(64000000, P_GPLL0, 12.5, 1, 1),
 872         { }
 873 };
 874
 875 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 876         .cmd_rcgr = 0x02044,
 877         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 878         .mnd_width = 16,
 879         .hid_width = 5,
 880         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 881         .clkr.hw.init = &(struct clk_init_data){
 882                 .name = "blsp1_uart1_apps_clk_src",
 883                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 884                 .num_parents = 3,
 885                 .ops = &clk_rcg2_ops,
 886         },
 887 };
 888
 889 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 890         .cmd_rcgr = 0x03034,
 891         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 892         .mnd_width = 16,
 893         .hid_width = 5,
 894         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 895         .clkr.hw.init = &(struct clk_init_data){
 896                 .name = "blsp1_uart2_apps_clk_src",
 897                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 898                 .num_parents = 3,
 899                 .ops = &clk_rcg2_ops,
 900         },
 901 };
 902
 903 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 904         .cmd_rcgr = 0x04034,
 905         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 906         .mnd_width = 16,
 907         .hid_width = 5,
 908         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 909         .clkr.hw.init = &(struct clk_init_data){
 910                 .name = "blsp1_uart3_apps_clk_src",
 911                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 912                 .num_parents = 3,
 913                 .ops = &clk_rcg2_ops,
 914         },
 915 };
 916
 917 static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
 918         .cmd_rcgr = 0x05034,
 919         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 920         .mnd_width = 16,
 921         .hid_width = 5,
 922         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 923         .clkr.hw.init = &(struct clk_init_data){
 924                 .name = "blsp1_uart4_apps_clk_src",
 925                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 926                 .num_parents = 3,
 927                 .ops = &clk_rcg2_ops,
 928         },
 929 };
 930
 931 static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
 932         .cmd_rcgr = 0x06034,
 933         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 934         .mnd_width = 16,
 935         .hid_width = 5,
 936         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 937         .clkr.hw.init = &(struct clk_init_data){
 938                 .name = "blsp1_uart5_apps_clk_src",
 939                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 940                 .num_parents = 3,
 941                 .ops = &clk_rcg2_ops,
 942         },
 943 };
 944
 945 static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
 946         .cmd_rcgr = 0x07034,
 947         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 948         .mnd_width = 16,
 949         .hid_width = 5,
 950         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 951         .clkr.hw.init = &(struct clk_init_data){
 952                 .name = "blsp1_uart6_apps_clk_src",
 953                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 954                 .num_parents = 3,
 955                 .ops = &clk_rcg2_ops,
 956         },
 957 };
 958
 959 static const struct freq_tbl ftbl_pcie_axi_clk_src[] = {
 960         F(19200000, P_XO, 1, 0, 0),
 961         F(200000000, P_GPLL0, 4, 0, 0),
 962         { }
 963 };
 964
 965 static struct clk_rcg2 pcie0_axi_clk_src = {
 966         .cmd_rcgr = 0x75054,
 967         .freq_tbl = ftbl_pcie_axi_clk_src,
 968         .hid_width = 5,
 969         .parent_map = gcc_xo_gpll0_map,
 970         .clkr.hw.init = &(struct clk_init_data){
 971                 .name = "pcie0_axi_clk_src",
 972                 .parent_names = gcc_xo_gpll0,
 973                 .num_parents = 2,
 974                 .ops = &clk_rcg2_ops,
 975         },
 976 };
 977
 978 static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
 979         F(19200000, P_XO, 1, 0, 0),
 980 };
 981
 982 static struct clk_rcg2 pcie0_aux_clk_src = {
 983         .cmd_rcgr = 0x75024,
 984         .freq_tbl = ftbl_pcie_aux_clk_src,
 985         .mnd_width = 16,
 986         .hid_width = 5,
 987         .parent_map = gcc_xo_gpll0_sleep_clk_map,
 988         .clkr.hw.init = &(struct clk_init_data){
 989                 .name = "pcie0_aux_clk_src",
 990                 .parent_names = gcc_xo_gpll0_sleep_clk,
 991                 .num_parents = 3,
 992                 .ops = &clk_rcg2_ops,
 993         },
 994 };
 995
 996 static struct clk_regmap_mux pcie0_pipe_clk_src = {
 997         .reg = 0x7501c,
 998         .shift = 8,
 999         .width = 2,
1000         .parent_map = gcc_pcie20_phy0_pipe_clk_xo_map,
1001         .clkr = {
1002                 .hw.init = &(struct clk_init_data){
1003                         .name = "pcie0_pipe_clk_src",
1004                         .parent_names = gcc_pcie20_phy0_pipe_clk_xo,
1005                         .num_parents = 2,
1006                         .ops = &clk_regmap_mux_closest_ops,
1007                         .flags = CLK_SET_RATE_PARENT,
1008                 },
1009         },
1010 };
1011
1012 static struct clk_rcg2 pcie1_axi_clk_src = {
1013         .cmd_rcgr = 0x76054,
1014         .freq_tbl = ftbl_pcie_axi_clk_src,
1015         .hid_width = 5,
1016         .parent_map = gcc_xo_gpll0_map,
1017         .clkr.hw.init = &(struct clk_init_data){
1018                 .name = "pcie1_axi_clk_src",
1019                 .parent_names = gcc_xo_gpll0,
1020                 .num_parents = 2,
1021                 .ops = &clk_rcg2_ops,
1022         },
1023 };
1024
1025 static struct clk_rcg2 pcie1_aux_clk_src = {
1026         .cmd_rcgr = 0x76024,
1027         .freq_tbl = ftbl_pcie_aux_clk_src,
1028         .mnd_width = 16,
1029         .hid_width = 5,
1030         .parent_map = gcc_xo_gpll0_sleep_clk_map,
1031         .clkr.hw.init = &(struct clk_init_data){
1032                 .name = "pcie1_aux_clk_src",
1033                 .parent_names = gcc_xo_gpll0_sleep_clk,
1034                 .num_parents = 3,
1035                 .ops = &clk_rcg2_ops,
1036         },
1037 };
1038
1039 static struct clk_regmap_mux pcie1_pipe_clk_src = {
1040         .reg = 0x7601c,
1041         .shift = 8,
1042         .width = 2,
1043         .parent_map = gcc_pcie20_phy1_pipe_clk_xo_map,
1044         .clkr = {
1045                 .hw.init = &(struct clk_init_data){
1046                         .name = "pcie1_pipe_clk_src",
1047                         .parent_names = gcc_pcie20_phy1_pipe_clk_xo,
1048                         .num_parents = 2,
1049                         .ops = &clk_regmap_mux_closest_ops,
1050                         .flags = CLK_SET_RATE_PARENT,
1051                 },
1052         },
1053 };
1054
1055 static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
1056         F(144000, P_XO, 16, 3, 25),
1057         F(400000, P_XO, 12, 1, 4),
1058         F(24000000, P_GPLL2, 12, 1, 4),
1059         F(48000000, P_GPLL2, 12, 1, 2),
1060         F(96000000, P_GPLL2, 12, 0, 0),
1061         F(177777778, P_GPLL0, 4.5, 0, 0),
1062         F(192000000, P_GPLL2, 6, 0, 0),
1063         F(384000000, P_GPLL2, 3, 0, 0),
1064         { }
1065 };
1066
1067 static struct clk_rcg2 sdcc1_apps_clk_src = {
1068         .cmd_rcgr = 0x42004,
1069         .freq_tbl = ftbl_sdcc_apps_clk_src,
1070         .mnd_width = 8,
1071         .hid_width = 5,
1072         .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
1073         .clkr.hw.init = &(struct clk_init_data){
1074                 .name = "sdcc1_apps_clk_src",
1075                 .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
1076                 .num_parents = 4,
1077                 .ops = &clk_rcg2_ops,
1078         },
1079 };
1080
1081 static const struct freq_tbl ftbl_sdcc_ice_core_clk_src[] = {
1082         F(19200000, P_XO, 1, 0, 0),
1083         F(160000000, P_GPLL0, 5, 0, 0),
1084         F(308570000, P_GPLL6, 3.5, 0, 0),
1085 };
1086
1087 static struct clk_rcg2 sdcc1_ice_core_clk_src = {
1088         .cmd_rcgr = 0x5d000,
1089         .freq_tbl = ftbl_sdcc_ice_core_clk_src,
1090         .mnd_width = 8,
1091         .hid_width = 5,
1092         .parent_map = gcc_xo_gpll0_gpll6_gpll0_div2_map,
1093         .clkr.hw.init = &(struct clk_init_data){
1094                 .name = "sdcc1_ice_core_clk_src",
1095                 .parent_names = gcc_xo_gpll0_gpll6_gpll0_div2,
1096                 .num_parents = 4,
1097                 .ops = &clk_rcg2_ops,
1098         },
1099 };
1100
1101 static struct clk_rcg2 sdcc2_apps_clk_src = {
1102         .cmd_rcgr = 0x43004,
1103         .freq_tbl = ftbl_sdcc_apps_clk_src,
1104         .mnd_width = 8,
1105         .hid_width = 5,
1106         .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
1107         .clkr.hw.init = &(struct clk_init_data){
1108                 .name = "sdcc2_apps_clk_src",
1109                 .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
1110                 .num_parents = 4,
1111                 .ops = &clk_rcg2_ops,
1112         },
1113 };
1114
1115 static const struct freq_tbl ftbl_usb_master_clk_src[] = {
1116         F(80000000, P_GPLL0_DIV2, 5, 0, 0),
1117         F(100000000, P_GPLL0, 8, 0, 0),
1118         F(133330000, P_GPLL0, 6, 0, 0),
1119         { }
1120 };
1121
1122 static struct clk_rcg2 usb0_master_clk_src = {
1123         .cmd_rcgr = 0x3e00c,
1124         .freq_tbl = ftbl_usb_master_clk_src,
1125         .mnd_width = 8,
1126         .hid_width = 5,
1127         .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
1128         .clkr.hw.init = &(struct clk_init_data){
1129                 .name = "usb0_master_clk_src",
1130                 .parent_names = gcc_xo_gpll0_out_main_div2_gpll0,
1131                 .num_parents = 3,
1132                 .ops = &clk_rcg2_ops,
1133         },
1134 };
1135
1136 static const struct freq_tbl ftbl_usb_aux_clk_src[] = {
1137         F(19200000, P_XO, 1, 0, 0),
1138         { }
1139 };
1140
1141 static struct clk_rcg2 usb0_aux_clk_src = {
1142         .cmd_rcgr = 0x3e05c,
1143         .freq_tbl = ftbl_usb_aux_clk_src,
1144         .mnd_width = 16,
1145         .hid_width = 5,
1146         .parent_map = gcc_xo_gpll0_sleep_clk_map,
1147         .clkr.hw.init = &(struct clk_init_data){
1148                 .name = "usb0_aux_clk_src",
1149                 .parent_names = gcc_xo_gpll0_sleep_clk,
1150                 .num_parents = 3,
1151                 .ops = &clk_rcg2_ops,
1152         },
1153 };
1154
1155 static const struct freq_tbl ftbl_usb_mock_utmi_clk_src[] = {
1156         F(19200000, P_XO, 1, 0, 0),
1157         F(20000000, P_GPLL6, 6, 1, 9),
1158         F(60000000, P_GPLL6, 6, 1, 3),
1159         { }
1160 };
1161
1162 static struct clk_rcg2 usb0_mock_utmi_clk_src = {
1163         .cmd_rcgr = 0x3e020,
1164         .freq_tbl = ftbl_usb_mock_utmi_clk_src,
1165         .mnd_width = 8,
1166         .hid_width = 5,
1167         .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
1168         .clkr.hw.init = &(struct clk_init_data){
1169                 .name = "usb0_mock_utmi_clk_src",
1170                 .parent_names = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
1171                 .num_parents = 4,
1172                 .ops = &clk_rcg2_ops,
1173         },
1174 };
1175
1176 static struct clk_regmap_mux usb0_pipe_clk_src = {
1177         .reg = 0x3e048,
1178         .shift = 8,
1179         .width = 2,
1180         .parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map,
1181         .clkr = {
1182                 .hw.init = &(struct clk_init_data){
1183                         .name = "usb0_pipe_clk_src",
1184                         .parent_names = gcc_usb3phy_0_cc_pipe_clk_xo,
1185                         .num_parents = 2,
1186                         .ops = &clk_regmap_mux_closest_ops,
1187                         .flags = CLK_SET_RATE_PARENT,
1188                 },
1189         },
1190 };
1191
1192 static struct clk_rcg2 usb1_master_clk_src = {
1193         .cmd_rcgr = 0x3f00c,
1194         .freq_tbl = ftbl_usb_master_clk_src,
1195         .mnd_width = 8,
1196         .hid_width = 5,
1197         .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
1198         .clkr.hw.init = &(struct clk_init_data){
1199                 .name = "usb1_master_clk_src",
1200                 .parent_names = gcc_xo_gpll0_out_main_div2_gpll0,
1201                 .num_parents = 3,
1202                 .ops = &clk_rcg2_ops,
1203         },
1204 };
1205
1206 static struct clk_rcg2 usb1_aux_clk_src = {
1207         .cmd_rcgr = 0x3f05c,
1208         .freq_tbl = ftbl_usb_aux_clk_src,
1209         .mnd_width = 16,
1210         .hid_width = 5,
1211         .parent_map = gcc_xo_gpll0_sleep_clk_map,
1212         .clkr.hw.init = &(struct clk_init_data){
1213                 .name = "usb1_aux_clk_src",
1214                 .parent_names = gcc_xo_gpll0_sleep_clk,
1215                 .num_parents = 3,
1216                 .ops = &clk_rcg2_ops,
1217         },
1218 };
1219
1220 static struct clk_rcg2 usb1_mock_utmi_clk_src = {
1221         .cmd_rcgr = 0x3f020,
1222         .freq_tbl = ftbl_usb_mock_utmi_clk_src,
1223         .mnd_width = 8,
1224         .hid_width = 5,
1225         .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
1226         .clkr.hw.init = &(struct clk_init_data){
1227                 .name = "usb1_mock_utmi_clk_src",
1228                 .parent_names = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
1229                 .num_parents = 4,
1230                 .ops = &clk_rcg2_ops,
1231         },
1232 };
1233
1234 static struct clk_regmap_mux usb1_pipe_clk_src = {
1235         .reg = 0x3f048,
1236         .shift = 8,
1237         .width = 2,
1238         .parent_map = gcc_usb3phy_1_cc_pipe_clk_xo_map,
1239         .clkr = {
1240                 .hw.init = &(struct clk_init_data){
1241                         .name = "usb1_pipe_clk_src",
1242                         .parent_names = gcc_usb3phy_1_cc_pipe_clk_xo,
1243                         .num_parents = 2,
1244                         .ops = &clk_regmap_mux_closest_ops,
1245                         .flags = CLK_SET_RATE_PARENT,
1246                 },
1247         },
1248 };
1249
1250 static struct clk_branch gcc_xo_clk_src = {
1251         .halt_reg = 0x30018,
1252         .clkr = {
1253                 .enable_reg = 0x30018,
1254                 .enable_mask = BIT(1),
1255                 .hw.init = &(struct clk_init_data){
1256                         .name = "gcc_xo_clk_src",
1257                         .parent_names = (const char *[]){
1258                                 "xo"
1259                         },
1260                         .num_parents = 1,
1261                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1262                         .ops = &clk_branch2_ops,
1263                 },
1264         },
1265 };
1266
1267 static struct clk_fixed_factor gcc_xo_div4_clk_src = {
1268         .mult = 1,
1269         .div = 4,
1270         .hw.init = &(struct clk_init_data){
1271                 .name = "gcc_xo_div4_clk_src",
1272                 .parent_names = (const char *[]){
1273                         "gcc_xo_clk_src"
1274                 },
1275                 .num_parents = 1,
1276                 .ops = &clk_fixed_factor_ops,
1277                 .flags = CLK_SET_RATE_PARENT,
1278         },
1279 };
1280
1281 static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = {
1282         F(19200000, P_XO, 1, 0, 0),
1283         F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1284         F(100000000, P_GPLL0, 8, 0, 0),
1285         F(133333333, P_GPLL0, 6, 0, 0),
1286         F(160000000, P_GPLL0, 5, 0, 0),
1287         F(200000000, P_GPLL0, 4, 0, 0),
1288         F(266666667, P_GPLL0, 3, 0, 0),
1289         { }
1290 };
1291
1292 static struct clk_rcg2 system_noc_bfdcd_clk_src = {
1293         .cmd_rcgr = 0x26004,
1294         .freq_tbl = ftbl_system_noc_bfdcd_clk_src,
1295         .hid_width = 5,
1296         .parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map,
1297         .clkr.hw.init = &(struct clk_init_data){
1298                 .name = "system_noc_bfdcd_clk_src",
1299                 .parent_names = gcc_xo_gpll0_gpll6_gpll0_out_main_div2,
1300                 .num_parents = 4,
1301                 .ops = &clk_rcg2_ops,
1302                 .flags = CLK_IS_CRITICAL,
1303         },
1304 };
1305
1306 static struct clk_fixed_factor system_noc_clk_src = {
1307         .mult = 1,
1308         .div = 1,
1309         .hw.init = &(struct clk_init_data){
1310                 .name = "system_noc_clk_src",
1311                 .parent_names = (const char *[]){
1312                         "system_noc_bfdcd_clk_src"
1313                 },
1314                 .num_parents = 1,
1315                 .ops = &clk_fixed_factor_ops,
1316                 .flags = CLK_SET_RATE_PARENT,
1317         },
1318 };
1319
1320 static const struct freq_tbl ftbl_nss_ce_clk_src[] = {
1321         F(19200000, P_XO, 1, 0, 0),
1322         F(200000000, P_GPLL0, 4, 0, 0),
1323         { }
1324 };
1325
1326 static struct clk_rcg2 nss_ce_clk_src = {
1327         .cmd_rcgr = 0x68098,
1328         .freq_tbl = ftbl_nss_ce_clk_src,
1329         .hid_width = 5,
1330         .parent_map = gcc_xo_gpll0_map,
1331         .clkr.hw.init = &(struct clk_init_data){
1332                 .name = "nss_ce_clk_src",
1333                 .parent_names = gcc_xo_gpll0,
1334                 .num_parents = 2,
1335                 .ops = &clk_rcg2_ops,
1336         },
1337 };
1338
1339 static const struct freq_tbl ftbl_nss_noc_bfdcd_clk_src[] = {
1340         F(19200000, P_XO, 1, 0, 0),
1341         F(461500000, P_BIAS_PLL_NSS_NOC, 1, 0, 0),
1342         { }
1343 };
1344
1345 static struct clk_rcg2 nss_noc_bfdcd_clk_src = {
1346         .cmd_rcgr = 0x68088,
1347         .freq_tbl = ftbl_nss_noc_bfdcd_clk_src,
1348         .hid_width = 5,
1349         .parent_map = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map,
1350         .clkr.hw.init = &(struct clk_init_data){
1351                 .name = "nss_noc_bfdcd_clk_src",
1352                 .parent_names = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2,
1353                 .num_parents = 4,
1354                 .ops = &clk_rcg2_ops,
1355         },
1356 };
1357
1358 static struct clk_fixed_factor nss_noc_clk_src = {
1359         .mult = 1,
1360         .div = 1,
1361         .hw.init = &(struct clk_init_data){
1362                 .name = "nss_noc_clk_src",
1363                 .parent_names = (const char *[]){
1364                         "nss_noc_bfdcd_clk_src"
1365                 },
1366                 .num_parents = 1,
1367                 .ops = &clk_fixed_factor_ops,
1368                 .flags = CLK_SET_RATE_PARENT,
1369         },
1370 };
1371
1372 static const struct freq_tbl ftbl_nss_crypto_clk_src[] = {
1373         F(19200000, P_XO, 1, 0, 0),
1374         F(600000000, P_NSS_CRYPTO_PLL, 1, 0, 0),
1375         { }
1376 };
1377
1378 static struct clk_rcg2 nss_crypto_clk_src = {
1379         .cmd_rcgr = 0x68144,
1380         .freq_tbl = ftbl_nss_crypto_clk_src,
1381         .mnd_width = 16,
1382         .hid_width = 5,
1383         .parent_map = gcc_xo_nss_crypto_pll_gpll0_map,
1384         .clkr.hw.init = &(struct clk_init_data){
1385                 .name = "nss_crypto_clk_src",
1386                 .parent_names = gcc_xo_nss_crypto_pll_gpll0,
1387                 .num_parents = 3,
1388                 .ops = &clk_rcg2_ops,
1389         },
1390 };
1391
1392 static const struct freq_tbl ftbl_nss_ubi_clk_src[] = {
1393         F(19200000, P_XO, 1, 0, 0),
1394         F(187200000, P_UBI32_PLL, 8, 0, 0),
1395         F(748800000, P_UBI32_PLL, 2, 0, 0),
1396         F(1497600000, P_UBI32_PLL, 1, 0, 0),
1397         F(1689600000, P_UBI32_PLL, 1, 0, 0),
1398         { }
1399 };
1400
1401 static struct clk_rcg2 nss_ubi0_clk_src = {
1402         .cmd_rcgr = 0x68104,
1403         .freq_tbl = ftbl_nss_ubi_clk_src,
1404         .hid_width = 5,
1405         .parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
1406         .clkr.hw.init = &(struct clk_init_data){
1407                 .name = "nss_ubi0_clk_src",
1408                 .parent_names = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
1409                 .num_parents = 6,
1410                 .ops = &clk_rcg2_ops,
1411                 .flags = CLK_SET_RATE_PARENT,
1412         },
1413 };
1414
1415 static struct clk_regmap_div nss_ubi0_div_clk_src = {
1416         .reg = 0x68118,
1417         .shift = 0,
1418         .width = 4,
1419         .clkr = {
1420                 .hw.init = &(struct clk_init_data){
1421                         .name = "nss_ubi0_div_clk_src",
1422                         .parent_names = (const char *[]){
1423                                 "nss_ubi0_clk_src"
1424                         },
1425                         .num_parents = 1,
1426                         .ops = &clk_regmap_div_ro_ops,
1427                         .flags = CLK_SET_RATE_PARENT,
1428                 },
1429         },
1430 };
1431
1432 static struct clk_rcg2 nss_ubi1_clk_src = {
1433         .cmd_rcgr = 0x68124,
1434         .freq_tbl = ftbl_nss_ubi_clk_src,
1435         .hid_width = 5,
1436         .parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
1437         .clkr.hw.init = &(struct clk_init_data){
1438                 .name = "nss_ubi1_clk_src",
1439                 .parent_names = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
1440                 .num_parents = 6,
1441                 .ops = &clk_rcg2_ops,
1442                 .flags = CLK_SET_RATE_PARENT,
1443         },
1444 };
1445
1446 static struct clk_regmap_div nss_ubi1_div_clk_src = {
1447         .reg = 0x68138,
1448         .shift = 0,
1449         .width = 4,
1450         .clkr = {
1451                 .hw.init = &(struct clk_init_data){
1452                         .name = "nss_ubi1_div_clk_src",
1453                         .parent_names = (const char *[]){
1454                                 "nss_ubi1_clk_src"
1455                         },
1456                         .num_parents = 1,
1457                         .ops = &clk_regmap_div_ro_ops,
1458                         .flags = CLK_SET_RATE_PARENT,
1459                 },
1460         },
1461 };
1462
1463 static const struct freq_tbl ftbl_ubi_mpt_clk_src[] = {
1464         F(19200000, P_XO, 1, 0, 0),
1465         F(25000000, P_GPLL0_DIV2, 16, 0, 0),
1466         { }
1467 };
1468
1469 static struct clk_rcg2 ubi_mpt_clk_src = {
1470         .cmd_rcgr = 0x68090,
1471         .freq_tbl = ftbl_ubi_mpt_clk_src,
1472         .hid_width = 5,
1473         .parent_map = gcc_xo_gpll0_out_main_div2_map,
1474         .clkr.hw.init = &(struct clk_init_data){
1475                 .name = "ubi_mpt_clk_src",
1476                 .parent_names = gcc_xo_gpll0_out_main_div2,
1477                 .num_parents = 2,
1478                 .ops = &clk_rcg2_ops,
1479         },
1480 };
1481
1482 static const struct freq_tbl ftbl_nss_imem_clk_src[] = {
1483         F(19200000, P_XO, 1, 0, 0),
1484         F(400000000, P_GPLL0, 2, 0, 0),
1485         { }
1486 };
1487
1488 static struct clk_rcg2 nss_imem_clk_src = {
1489         .cmd_rcgr = 0x68158,
1490         .freq_tbl = ftbl_nss_imem_clk_src,
1491         .hid_width = 5,
1492         .parent_map = gcc_xo_gpll0_gpll4_map,
1493         .clkr.hw.init = &(struct clk_init_data){
1494                 .name = "nss_imem_clk_src",
1495                 .parent_names = gcc_xo_gpll0_gpll4,
1496                 .num_parents = 3,
1497                 .ops = &clk_rcg2_ops,
1498         },
1499 };
1500
1501 static const struct freq_tbl ftbl_nss_ppe_clk_src[] = {
1502         F(19200000, P_XO, 1, 0, 0),
1503         F(300000000, P_BIAS_PLL, 1, 0, 0),
1504         { }
1505 };
1506
1507 static struct clk_rcg2 nss_ppe_clk_src = {
1508         .cmd_rcgr = 0x68080,
1509         .freq_tbl = ftbl_nss_ppe_clk_src,
1510         .hid_width = 5,
1511         .parent_map = gcc_xo_bias_gpll0_gpll4_nss_ubi32_map,
1512         .clkr.hw.init = &(struct clk_init_data){
1513                 .name = "nss_ppe_clk_src",
1514                 .parent_names = gcc_xo_bias_gpll0_gpll4_nss_ubi32,
1515                 .num_parents = 6,
1516                 .ops = &clk_rcg2_ops,
1517         },
1518 };
1519
1520 static struct clk_fixed_factor nss_ppe_cdiv_clk_src = {
1521         .mult = 1,
1522         .div = 4,
1523         .hw.init = &(struct clk_init_data){
1524                 .name = "nss_ppe_cdiv_clk_src",
1525                 .parent_names = (const char *[]){
1526                         "nss_ppe_clk_src"
1527                 },
1528                 .num_parents = 1,
1529                 .ops = &clk_fixed_factor_ops,
1530                 .flags = CLK_SET_RATE_PARENT,
1531         },
1532 };
1533
1534 static const struct freq_tbl ftbl_nss_port1_rx_clk_src[] = {
1535         F(19200000, P_XO, 1, 0, 0),
1536         F(25000000, P_UNIPHY0_RX, 5, 0, 0),
1537         F(125000000, P_UNIPHY0_RX, 1, 0, 0),
1538         { }
1539 };
1540
1541 static struct clk_rcg2 nss_port1_rx_clk_src = {
1542         .cmd_rcgr = 0x68020,
1543         .freq_tbl = ftbl_nss_port1_rx_clk_src,
1544         .hid_width = 5,
1545         .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
1546         .clkr.hw.init = &(struct clk_init_data){
1547                 .name = "nss_port1_rx_clk_src",
1548                 .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1549                 .num_parents = 5,
1550                 .ops = &clk_rcg2_ops,
1551         },
1552 };
1553
1554 static struct clk_regmap_div nss_port1_rx_div_clk_src = {
1555         .reg = 0x68400,
1556         .shift = 0,
1557         .width = 4,
1558         .clkr = {
1559                 .hw.init = &(struct clk_init_data){
1560                         .name = "nss_port1_rx_div_clk_src",
1561                         .parent_names = (const char *[]){
1562                                 "nss_port1_rx_clk_src"
1563                         },
1564                         .num_parents = 1,
1565                         .ops = &clk_regmap_div_ops,
1566                         .flags = CLK_SET_RATE_PARENT,
1567                 },
1568         },
1569 };
1570
1571 static const struct freq_tbl ftbl_nss_port1_tx_clk_src[] = {
1572         F(19200000, P_XO, 1, 0, 0),
1573         F(25000000, P_UNIPHY0_TX, 5, 0, 0),
1574         F(125000000, P_UNIPHY0_TX, 1, 0, 0),
1575         { }
1576 };
1577
1578 static struct clk_rcg2 nss_port1_tx_clk_src = {
1579         .cmd_rcgr = 0x68028,
1580         .freq_tbl = ftbl_nss_port1_tx_clk_src,
1581         .hid_width = 5,
1582         .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
1583         .clkr.hw.init = &(struct clk_init_data){
1584                 .name = "nss_port1_tx_clk_src",
1585                 .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1586                 .num_parents = 5,
1587                 .ops = &clk_rcg2_ops,
1588         },
1589 };
1590
1591 static struct clk_regmap_div nss_port1_tx_div_clk_src = {
1592         .reg = 0x68404,
1593         .shift = 0,
1594         .width = 4,
1595         .clkr = {
1596                 .hw.init = &(struct clk_init_data){
1597                         .name = "nss_port1_tx_div_clk_src",
1598                         .parent_names = (const char *[]){
1599                                 "nss_port1_tx_clk_src"
1600                         },
1601                         .num_parents = 1,
1602                         .ops = &clk_regmap_div_ops,
1603                         .flags = CLK_SET_RATE_PARENT,
1604                 },
1605         },
1606 };
1607
1608 static struct clk_rcg2 nss_port2_rx_clk_src = {
1609         .cmd_rcgr = 0x68030,
1610         .freq_tbl = ftbl_nss_port1_rx_clk_src,
1611         .hid_width = 5,
1612         .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
1613         .clkr.hw.init = &(struct clk_init_data){
1614                 .name = "nss_port2_rx_clk_src",
1615                 .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1616                 .num_parents = 5,
1617                 .ops = &clk_rcg2_ops,
1618         },
1619 };
1620
1621 static struct clk_regmap_div nss_port2_rx_div_clk_src = {
1622         .reg = 0x68410,
1623         .shift = 0,
1624         .width = 4,
1625         .clkr = {
1626                 .hw.init = &(struct clk_init_data){
1627                         .name = "nss_port2_rx_div_clk_src",
1628                         .parent_names = (const char *[]){
1629                                 "nss_port2_rx_clk_src"
1630                         },
1631                         .num_parents = 1,
1632                         .ops = &clk_regmap_div_ops,
1633                         .flags = CLK_SET_RATE_PARENT,
1634                 },
1635         },
1636 };
1637
1638 static struct clk_rcg2 nss_port2_tx_clk_src = {
1639         .cmd_rcgr = 0x68038,
1640         .freq_tbl = ftbl_nss_port1_tx_clk_src,
1641         .hid_width = 5,
1642         .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
1643         .clkr.hw.init = &(struct clk_init_data){
1644                 .name = "nss_port2_tx_clk_src",
1645                 .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1646                 .num_parents = 5,
1647                 .ops = &clk_rcg2_ops,
1648         },
1649 };
1650
1651 static struct clk_regmap_div nss_port2_tx_div_clk_src = {
1652         .reg = 0x68414,
1653         .shift = 0,
1654         .width = 4,
1655         .clkr = {
1656                 .hw.init = &(struct clk_init_data){
1657                         .name = "nss_port2_tx_div_clk_src",
1658                         .parent_names = (const char *[]){
1659                                 "nss_port2_tx_clk_src"
1660                         },
1661                         .num_parents = 1,
1662                         .ops = &clk_regmap_div_ops,
1663                         .flags = CLK_SET_RATE_PARENT,
1664                 },
1665         },
1666 };
1667
1668 static struct clk_rcg2 nss_port3_rx_clk_src = {
1669         .cmd_rcgr = 0x68040,
1670         .freq_tbl = ftbl_nss_port1_rx_clk_src,
1671         .hid_width = 5,
1672         .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
1673         .clkr.hw.init = &(struct clk_init_data){
1674                 .name = "nss_port3_rx_clk_src",
1675                 .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1676                 .num_parents = 5,
1677                 .ops = &clk_rcg2_ops,
1678         },
1679 };
1680
1681 static struct clk_regmap_div nss_port3_rx_div_clk_src = {
1682         .reg = 0x68420,
1683         .shift = 0,
1684         .width = 4,
1685         .clkr = {
1686                 .hw.init = &(struct clk_init_data){
1687                         .name = "nss_port3_rx_div_clk_src",
1688                         .parent_names = (const char *[]){
1689                                 "nss_port3_rx_clk_src"
1690                         },
1691                         .num_parents = 1,
1692                         .ops = &clk_regmap_div_ops,
1693                         .flags = CLK_SET_RATE_PARENT,
1694                 },
1695         },
1696 };
1697
1698 static struct clk_rcg2 nss_port3_tx_clk_src = {
1699         .cmd_rcgr = 0x68048,
1700         .freq_tbl = ftbl_nss_port1_tx_clk_src,
1701         .hid_width = 5,
1702         .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
1703         .clkr.hw.init = &(struct clk_init_data){
1704                 .name = "nss_port3_tx_clk_src",
1705                 .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1706                 .num_parents = 5,
1707                 .ops = &clk_rcg2_ops,
1708         },
1709 };
1710
1711 static struct clk_regmap_div nss_port3_tx_div_clk_src = {
1712         .reg = 0x68424,
1713         .shift = 0,
1714         .width = 4,
1715         .clkr = {
1716                 .hw.init = &(struct clk_init_data){
1717                         .name = "nss_port3_tx_div_clk_src",
1718                         .parent_names = (const char *[]){
1719                                 "nss_port3_tx_clk_src"
1720                         },
1721                         .num_parents = 1,
1722                         .ops = &clk_regmap_div_ops,
1723                         .flags = CLK_SET_RATE_PARENT,
1724                 },
1725         },
1726 };
1727
1728 static struct clk_rcg2 nss_port4_rx_clk_src = {
1729         .cmd_rcgr = 0x68050,
1730         .freq_tbl = ftbl_nss_port1_rx_clk_src,
1731         .hid_width = 5,
1732         .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
1733         .clkr.hw.init = &(struct clk_init_data){
1734                 .name = "nss_port4_rx_clk_src",
1735                 .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
1736                 .num_parents = 5,
1737                 .ops = &clk_rcg2_ops,
1738         },
1739 };
1740
1741 static struct clk_regmap_div nss_port4_rx_div_clk_src = {
1742         .reg = 0x68430,
1743         .shift = 0,
1744         .width = 4,
1745         .clkr = {
1746                 .hw.init = &(struct clk_init_data){
1747                         .name = "nss_port4_rx_div_clk_src",
1748                         .parent_names = (const char *[]){
1749                                 "nss_port4_rx_clk_src"
1750                         },
1751                         .num_parents = 1,
1752                         .ops = &clk_regmap_div_ops,
1753                         .flags = CLK_SET_RATE_PARENT,
1754                 },
1755         },
1756 };
1757
1758 static struct clk_rcg2 nss_port4_tx_clk_src = {
1759         .cmd_rcgr = 0x68058,
1760         .freq_tbl = ftbl_nss_port1_tx_clk_src,
1761         .hid_width = 5,
1762         .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
1763         .clkr.hw.init = &(struct clk_init_data){
1764                 .name = "nss_port4_tx_clk_src",
1765                 .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
1766                 .num_parents = 5,
1767                 .ops = &clk_rcg2_ops,
1768         },
1769 };
1770
1771 static struct clk_regmap_div nss_port4_tx_div_clk_src = {
1772         .reg = 0x68434,
1773         .shift = 0,
1774         .width = 4,
1775         .clkr = {
1776                 .hw.init = &(struct clk_init_data){
1777                         .name = "nss_port4_tx_div_clk_src",
1778                         .parent_names = (const char *[]){
1779                                 "nss_port4_tx_clk_src"
1780                         },
1781                         .num_parents = 1,
1782                         .ops = &clk_regmap_div_ops,
1783                         .flags = CLK_SET_RATE_PARENT,
1784                 },
1785         },
1786 };
1787
1788 static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
1789         F(19200000, P_XO, 1, 0, 0),
1790         F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
1791         F(78125000, P_UNIPHY1_RX, 4, 0, 0),
1792         F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
1793         F(156250000, P_UNIPHY1_RX, 2, 0, 0),
1794         F(312500000, P_UNIPHY1_RX, 1, 0, 0),
1795         { }
1796 };
1797
1798 static struct clk_rcg2 nss_port5_rx_clk_src = {
1799         .cmd_rcgr = 0x68060,
1800         .freq_tbl = ftbl_nss_port5_rx_clk_src,
1801         .hid_width = 5,
1802         .parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map,
1803         .clkr.hw.init = &(struct clk_init_data){
1804                 .name = "nss_port5_rx_clk_src",
1805                 .parent_names = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
1806                 .num_parents = 7,
1807                 .ops = &clk_rcg2_ops,
1808         },
1809 };
1810
1811 static struct clk_regmap_div nss_port5_rx_div_clk_src = {
1812         .reg = 0x68440,
1813         .shift = 0,
1814         .width = 4,
1815         .clkr = {
1816                 .hw.init = &(struct clk_init_data){
1817                         .name = "nss_port5_rx_div_clk_src",
1818                         .parent_names = (const char *[]){
1819                                 "nss_port5_rx_clk_src"
1820                         },
1821                         .num_parents = 1,
1822                         .ops = &clk_regmap_div_ops,
1823                         .flags = CLK_SET_RATE_PARENT,
1824                 },
1825         },
1826 };
1827
1828 static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
1829         F(19200000, P_XO, 1, 0, 0),
1830         F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
1831         F(78125000, P_UNIPHY1_TX, 4, 0, 0),
1832         F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
1833         F(156250000, P_UNIPHY1_TX, 2, 0, 0),
1834         F(312500000, P_UNIPHY1_TX, 1, 0, 0),
1835         { }
1836 };
1837
1838 static struct clk_rcg2 nss_port5_tx_clk_src = {
1839         .cmd_rcgr = 0x68068,
1840         .freq_tbl = ftbl_nss_port5_tx_clk_src,
1841         .hid_width = 5,
1842         .parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map,
1843         .clkr.hw.init = &(struct clk_init_data){
1844                 .name = "nss_port5_tx_clk_src",
1845                 .parent_names = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
1846                 .num_parents = 7,
1847                 .ops = &clk_rcg2_ops,
1848         },
1849 };
1850
1851 static struct clk_regmap_div nss_port5_tx_div_clk_src = {
1852         .reg = 0x68444,
1853         .shift = 0,
1854         .width = 4,
1855         .clkr = {
1856                 .hw.init = &(struct clk_init_data){
1857                         .name = "nss_port5_tx_div_clk_src",
1858                         .parent_names = (const char *[]){
1859                                 "nss_port5_tx_clk_src"
1860                         },
1861                         .num_parents = 1,
1862                         .ops = &clk_regmap_div_ops,
1863                         .flags = CLK_SET_RATE_PARENT,
1864                 },
1865         },
1866 };
1867
1868 static const struct freq_tbl ftbl_nss_port6_rx_clk_src[] = {
1869         F(19200000, P_XO, 1, 0, 0),
1870         F(25000000, P_UNIPHY2_RX, 12.5, 0, 0),
1871         F(78125000, P_UNIPHY2_RX, 4, 0, 0),
1872         F(125000000, P_UNIPHY2_RX, 2.5, 0, 0),
1873         F(156250000, P_UNIPHY2_RX, 2, 0, 0),
1874         F(312500000, P_UNIPHY2_RX, 1, 0, 0),
1875         { }
1876 };
1877
1878 static struct clk_rcg2 nss_port6_rx_clk_src = {
1879         .cmd_rcgr = 0x68070,
1880         .freq_tbl = ftbl_nss_port6_rx_clk_src,
1881         .hid_width = 5,
1882         .parent_map = gcc_xo_uniphy2_rx_tx_ubi32_bias_map,
1883         .clkr.hw.init = &(struct clk_init_data){
1884                 .name = "nss_port6_rx_clk_src",
1885                 .parent_names = gcc_xo_uniphy2_rx_tx_ubi32_bias,
1886                 .num_parents = 5,
1887                 .ops = &clk_rcg2_ops,
1888         },
1889 };
1890
1891 static struct clk_regmap_div nss_port6_rx_div_clk_src = {
1892         .reg = 0x68450,
1893         .shift = 0,
1894         .width = 4,
1895         .clkr = {
1896                 .hw.init = &(struct clk_init_data){
1897                         .name = "nss_port6_rx_div_clk_src",
1898                         .parent_names = (const char *[]){
1899                                 "nss_port6_rx_clk_src"
1900                         },
1901                         .num_parents = 1,
1902                         .ops = &clk_regmap_div_ops,
1903                         .flags = CLK_SET_RATE_PARENT,
1904                 },
1905         },
1906 };
1907
1908 static const struct freq_tbl ftbl_nss_port6_tx_clk_src[] = {
1909         F(19200000, P_XO, 1, 0, 0),
1910         F(25000000, P_UNIPHY2_TX, 12.5, 0, 0),
1911         F(78125000, P_UNIPHY2_TX, 4, 0, 0),
1912         F(125000000, P_UNIPHY2_TX, 2.5, 0, 0),
1913         F(156250000, P_UNIPHY2_TX, 2, 0, 0),
1914         F(312500000, P_UNIPHY2_TX, 1, 0, 0),
1915         { }
1916 };
1917
1918 static struct clk_rcg2 nss_port6_tx_clk_src = {
1919         .cmd_rcgr = 0x68078,
1920         .freq_tbl = ftbl_nss_port6_tx_clk_src,
1921         .hid_width = 5,
1922         .parent_map = gcc_xo_uniphy2_tx_rx_ubi32_bias_map,
1923         .clkr.hw.init = &(struct clk_init_data){
1924                 .name = "nss_port6_tx_clk_src",
1925                 .parent_names = gcc_xo_uniphy2_tx_rx_ubi32_bias,
1926                 .num_parents = 5,
1927                 .ops = &clk_rcg2_ops,
1928         },
1929 };
1930
1931 static struct clk_regmap_div nss_port6_tx_div_clk_src = {
1932         .reg = 0x68454,
1933         .shift = 0,
1934         .width = 4,
1935         .clkr = {
1936                 .hw.init = &(struct clk_init_data){
1937                         .name = "nss_port6_tx_div_clk_src",
1938                         .parent_names = (const char *[]){
1939                                 "nss_port6_tx_clk_src"
1940                         },
1941                         .num_parents = 1,
1942                         .ops = &clk_regmap_div_ops,
1943                         .flags = CLK_SET_RATE_PARENT,
1944                 },
1945         },
1946 };
1947
1948 static struct freq_tbl ftbl_crypto_clk_src[] = {
1949         F(40000000, P_GPLL0_DIV2, 10, 0, 0),
1950         F(80000000, P_GPLL0, 10, 0, 0),
1951         F(100000000, P_GPLL0, 8, 0, 0),
1952         F(160000000, P_GPLL0, 5, 0, 0),
1953         { }
1954 };
1955
1956 static struct clk_rcg2 crypto_clk_src = {
1957         .cmd_rcgr = 0x16004,
1958         .freq_tbl = ftbl_crypto_clk_src,
1959         .hid_width = 5,
1960         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1961         .clkr.hw.init = &(struct clk_init_data){
1962                 .name = "crypto_clk_src",
1963                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
1964                 .num_parents = 3,
1965                 .ops = &clk_rcg2_ops,
1966         },
1967 };
1968
1969 static struct freq_tbl ftbl_gp_clk_src[] = {
1970         F(19200000, P_XO, 1, 0, 0),
1971         { }
1972 };
1973
1974 static struct clk_rcg2 gp1_clk_src = {
1975         .cmd_rcgr = 0x08004,
1976         .freq_tbl = ftbl_gp_clk_src,
1977         .mnd_width = 8,
1978         .hid_width = 5,
1979         .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
1980         .clkr.hw.init = &(struct clk_init_data){
1981                 .name = "gp1_clk_src",
1982                 .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
1983                 .num_parents = 5,
1984                 .ops = &clk_rcg2_ops,
1985         },
1986 };
1987
1988 static struct clk_rcg2 gp2_clk_src = {
1989         .cmd_rcgr = 0x09004,
1990         .freq_tbl = ftbl_gp_clk_src,
1991         .mnd_width = 8,
1992         .hid_width = 5,
1993         .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
1994         .clkr.hw.init = &(struct clk_init_data){
1995                 .name = "gp2_clk_src",
1996                 .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
1997                 .num_parents = 5,
1998                 .ops = &clk_rcg2_ops,
1999         },
2000 };
2001
2002 static struct clk_rcg2 gp3_clk_src = {
2003         .cmd_rcgr = 0x0a004,
2004         .freq_tbl = ftbl_gp_clk_src,
2005         .mnd_width = 8,
2006         .hid_width = 5,
2007         .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
2008         .clkr.hw.init = &(struct clk_init_data){
2009                 .name = "gp3_clk_src",
2010                 .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
2011                 .num_parents = 5,
2012                 .ops = &clk_rcg2_ops,
2013         },
2014 };
2015
2016 static struct clk_branch gcc_blsp1_ahb_clk = {
2017         .halt_reg = 0x01008,
2018         .clkr = {
2019                 .enable_reg = 0x01008,
2020                 .enable_mask = BIT(0),
2021                 .hw.init = &(struct clk_init_data){
2022                         .name = "gcc_blsp1_ahb_clk",
2023                         .parent_names = (const char *[]){
2024                                 "pcnoc_clk_src"
2025                         },
2026                         .num_parents = 1,
2027                         .flags = CLK_SET_RATE_PARENT,
2028                         .ops = &clk_branch2_ops,
2029                 },
2030         },
2031 };
2032
2033 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
2034         .halt_reg = 0x02008,
2035         .clkr = {
2036                 .enable_reg = 0x02008,
2037                 .enable_mask = BIT(0),
2038                 .hw.init = &(struct clk_init_data){
2039                         .name = "gcc_blsp1_qup1_i2c_apps_clk",
2040                         .parent_names = (const char *[]){
2041                                 "blsp1_qup1_i2c_apps_clk_src"
2042                         },
2043                         .num_parents = 1,
2044                         .flags = CLK_SET_RATE_PARENT,
2045                         .ops = &clk_branch2_ops,
2046                 },
2047         },
2048 };
2049
2050 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
2051         .halt_reg = 0x02004,
2052         .clkr = {
2053                 .enable_reg = 0x02004,
2054                 .enable_mask = BIT(0),
2055                 .hw.init = &(struct clk_init_data){
2056                         .name = "gcc_blsp1_qup1_spi_apps_clk",
2057                         .parent_names = (const char *[]){
2058                                 "blsp1_qup1_spi_apps_clk_src"
2059                         },
2060                         .num_parents = 1,
2061                         .flags = CLK_SET_RATE_PARENT,
2062                         .ops = &clk_branch2_ops,
2063                 },
2064         },
2065 };
2066
2067 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
2068         .halt_reg = 0x03010,
2069         .clkr = {
2070                 .enable_reg = 0x03010,
2071                 .enable_mask = BIT(0),
2072                 .hw.init = &(struct clk_init_data){
2073                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
2074                         .parent_names = (const char *[]){
2075                                 "blsp1_qup2_i2c_apps_clk_src"
2076                         },
2077                         .num_parents = 1,
2078                         .flags = CLK_SET_RATE_PARENT,
2079                         .ops = &clk_branch2_ops,
2080                 },
2081         },
2082 };
2083
2084 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
2085         .halt_reg = 0x0300c,
2086         .clkr = {
2087                 .enable_reg = 0x0300c,
2088                 .enable_mask = BIT(0),
2089                 .hw.init = &(struct clk_init_data){
2090                         .name = "gcc_blsp1_qup2_spi_apps_clk",
2091                         .parent_names = (const char *[]){
2092                                 "blsp1_qup2_spi_apps_clk_src"
2093                         },
2094                         .num_parents = 1,
2095                         .flags = CLK_SET_RATE_PARENT,
2096                         .ops = &clk_branch2_ops,
2097                 },
2098         },
2099 };
2100
2101 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
2102         .halt_reg = 0x04010,
2103         .clkr = {
2104                 .enable_reg = 0x04010,
2105                 .enable_mask = BIT(0),
2106                 .hw.init = &(struct clk_init_data){
2107                         .name = "gcc_blsp1_qup3_i2c_apps_clk",
2108                         .parent_names = (const char *[]){
2109                                 "blsp1_qup3_i2c_apps_clk_src"
2110                         },
2111                         .num_parents = 1,
2112                         .flags = CLK_SET_RATE_PARENT,
2113                         .ops = &clk_branch2_ops,
2114                 },
2115         },
2116 };
2117
2118 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
2119         .halt_reg = 0x0400c,
2120         .clkr = {
2121                 .enable_reg = 0x0400c,
2122                 .enable_mask = BIT(0),
2123                 .hw.init = &(struct clk_init_data){
2124                         .name = "gcc_blsp1_qup3_spi_apps_clk",
2125                         .parent_names = (const char *[]){
2126                                 "blsp1_qup3_spi_apps_clk_src"
2127                         },
2128                         .num_parents = 1,
2129                         .flags = CLK_SET_RATE_PARENT,
2130                         .ops = &clk_branch2_ops,
2131                 },
2132         },
2133 };
2134
2135 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
2136         .halt_reg = 0x05010,
2137         .clkr = {
2138                 .enable_reg = 0x05010,
2139                 .enable_mask = BIT(0),
2140                 .hw.init = &(struct clk_init_data){
2141                         .name = "gcc_blsp1_qup4_i2c_apps_clk",
2142                         .parent_names = (const char *[]){
2143                                 "blsp1_qup4_i2c_apps_clk_src"
2144                         },
2145                         .num_parents = 1,
2146                         .flags = CLK_SET_RATE_PARENT,
2147                         .ops = &clk_branch2_ops,
2148                 },
2149         },
2150 };
2151
2152 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
2153         .halt_reg = 0x0500c,
2154         .clkr = {
2155                 .enable_reg = 0x0500c,
2156                 .enable_mask = BIT(0),
2157                 .hw.init = &(struct clk_init_data){
2158                         .name = "gcc_blsp1_qup4_spi_apps_clk",
2159                         .parent_names = (const char *[]){
2160                                 "blsp1_qup4_spi_apps_clk_src"
2161                         },
2162                         .num_parents = 1,
2163                         .flags = CLK_SET_RATE_PARENT,
2164                         .ops = &clk_branch2_ops,
2165                 },
2166         },
2167 };
2168
2169 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
2170         .halt_reg = 0x06010,
2171         .clkr = {
2172                 .enable_reg = 0x06010,
2173                 .enable_mask = BIT(0),
2174                 .hw.init = &(struct clk_init_data){
2175                         .name = "gcc_blsp1_qup5_i2c_apps_clk",
2176                         .parent_names = (const char *[]){
2177                                 "blsp1_qup5_i2c_apps_clk_src"
2178                         },
2179                         .num_parents = 1,
2180                         .flags = CLK_SET_RATE_PARENT,
2181                         .ops = &clk_branch2_ops,
2182                 },
2183         },
2184 };
2185
2186 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
2187         .halt_reg = 0x0600c,
2188         .clkr = {
2189                 .enable_reg = 0x0600c,
2190                 .enable_mask = BIT(0),
2191                 .hw.init = &(struct clk_init_data){
2192                         .name = "gcc_blsp1_qup5_spi_apps_clk",
2193                         .parent_names = (const char *[]){
2194                                 "blsp1_qup5_spi_apps_clk_src"
2195                         },
2196                         .num_parents = 1,
2197                         .flags = CLK_SET_RATE_PARENT,
2198                         .ops = &clk_branch2_ops,
2199                 },
2200         },
2201 };
2202
2203 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
2204         .halt_reg = 0x07010,
2205         .clkr = {
2206                 .enable_reg = 0x07010,
2207                 .enable_mask = BIT(0),
2208                 .hw.init = &(struct clk_init_data){
2209                         .name = "gcc_blsp1_qup6_i2c_apps_clk",
2210                         .parent_names = (const char *[]){
2211                                 "blsp1_qup6_i2c_apps_clk_src"
2212                         },
2213                         .num_parents = 1,
2214                         .flags = CLK_SET_RATE_PARENT,
2215                         .ops = &clk_branch2_ops,
2216                 },
2217         },
2218 };
2219
2220 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
2221         .halt_reg = 0x0700c,
2222         .clkr = {
2223                 .enable_reg = 0x0700c,
2224                 .enable_mask = BIT(0),
2225                 .hw.init = &(struct clk_init_data){
2226                         .name = "gcc_blsp1_qup6_spi_apps_clk",
2227                         .parent_names = (const char *[]){
2228                                 "blsp1_qup6_spi_apps_clk_src"
2229                         },
2230                         .num_parents = 1,
2231                         .flags = CLK_SET_RATE_PARENT,
2232                         .ops = &clk_branch2_ops,
2233                 },
2234         },
2235 };
2236
2237 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
2238         .halt_reg = 0x0203c,
2239         .clkr = {
2240                 .enable_reg = 0x0203c,
2241                 .enable_mask = BIT(0),
2242                 .hw.init = &(struct clk_init_data){
2243                         .name = "gcc_blsp1_uart1_apps_clk",
2244                         .parent_names = (const char *[]){
2245                                 "blsp1_uart1_apps_clk_src"
2246                         },
2247                         .num_parents = 1,
2248                         .flags = CLK_SET_RATE_PARENT,
2249                         .ops = &clk_branch2_ops,
2250                 },
2251         },
2252 };
2253
2254 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
2255         .halt_reg = 0x0302c,
2256         .clkr = {
2257                 .enable_reg = 0x0302c,
2258                 .enable_mask = BIT(0),
2259                 .hw.init = &(struct clk_init_data){
2260                         .name = "gcc_blsp1_uart2_apps_clk",
2261                         .parent_names = (const char *[]){
2262                                 "blsp1_uart2_apps_clk_src"
2263                         },
2264                         .num_parents = 1,
2265                         .flags = CLK_SET_RATE_PARENT,
2266                         .ops = &clk_branch2_ops,
2267                 },
2268         },
2269 };
2270
2271 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
2272         .halt_reg = 0x0402c,
2273         .clkr = {
2274                 .enable_reg = 0x0402c,
2275                 .enable_mask = BIT(0),
2276                 .hw.init = &(struct clk_init_data){
2277                         .name = "gcc_blsp1_uart3_apps_clk",
2278                         .parent_names = (const char *[]){
2279                                 "blsp1_uart3_apps_clk_src"
2280                         },
2281                         .num_parents = 1,
2282                         .flags = CLK_SET_RATE_PARENT,
2283                         .ops = &clk_branch2_ops,
2284                 },
2285         },
2286 };
2287
2288 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
2289         .halt_reg = 0x0502c,
2290         .clkr = {
2291                 .enable_reg = 0x0502c,
2292                 .enable_mask = BIT(0),
2293                 .hw.init = &(struct clk_init_data){
2294                         .name = "gcc_blsp1_uart4_apps_clk",
2295                         .parent_names = (const char *[]){
2296                                 "blsp1_uart4_apps_clk_src"
2297                         },
2298                         .num_parents = 1,
2299                         .flags = CLK_SET_RATE_PARENT,
2300                         .ops = &clk_branch2_ops,
2301                 },
2302         },
2303 };
2304
2305 static struct clk_branch gcc_blsp1_uart5_apps_clk = {
2306         .halt_reg = 0x0602c,
2307         .clkr = {
2308                 .enable_reg = 0x0602c,
2309                 .enable_mask = BIT(0),
2310                 .hw.init = &(struct clk_init_data){
2311                         .name = "gcc_blsp1_uart5_apps_clk",
2312                         .parent_names = (const char *[]){
2313                                 "blsp1_uart5_apps_clk_src"
2314                         },
2315                         .num_parents = 1,
2316                         .flags = CLK_SET_RATE_PARENT,
2317                         .ops = &clk_branch2_ops,
2318                 },
2319         },
2320 };
2321
2322 static struct clk_branch gcc_blsp1_uart6_apps_clk = {
2323         .halt_reg = 0x0702c,
2324         .clkr = {
2325                 .enable_reg = 0x0702c,
2326                 .enable_mask = BIT(0),
2327                 .hw.init = &(struct clk_init_data){
2328                         .name = "gcc_blsp1_uart6_apps_clk",
2329                         .parent_names = (const char *[]){
2330                                 "blsp1_uart6_apps_clk_src"
2331                         },
2332                         .num_parents = 1,
2333                         .flags = CLK_SET_RATE_PARENT,
2334                         .ops = &clk_branch2_ops,
2335                 },
2336         },
2337 };
2338
2339 static struct clk_branch gcc_prng_ahb_clk = {
2340         .halt_reg = 0x13004,
2341         .halt_check = BRANCH_HALT_VOTED,
2342         .clkr = {
2343                 .enable_reg = 0x0b004,
2344                 .enable_mask = BIT(8),
2345                 .hw.init = &(struct clk_init_data){
2346                         .name = "gcc_prng_ahb_clk",
2347                         .parent_names = (const char *[]){
2348                                 "pcnoc_clk_src"
2349                         },
2350                         .num_parents = 1,
2351                         .flags = CLK_SET_RATE_PARENT,
2352                         .ops = &clk_branch2_ops,
2353                 },
2354         },
2355 };
2356
2357 static struct clk_branch gcc_qpic_ahb_clk = {
2358         .halt_reg = 0x57024,
2359         .clkr = {
2360                 .enable_reg = 0x57024,
2361                 .enable_mask = BIT(0),
2362                 .hw.init = &(struct clk_init_data){
2363                         .name = "gcc_qpic_ahb_clk",
2364                         .parent_names = (const char *[]){
2365                                 "pcnoc_clk_src"
2366                         },
2367                         .num_parents = 1,
2368                         .flags = CLK_SET_RATE_PARENT,
2369                         .ops = &clk_branch2_ops,
2370                 },
2371         },
2372 };
2373
2374 static struct clk_branch gcc_qpic_clk = {
2375         .halt_reg = 0x57020,
2376         .clkr = {
2377                 .enable_reg = 0x57020,
2378                 .enable_mask = BIT(0),
2379                 .hw.init = &(struct clk_init_data){
2380                         .name = "gcc_qpic_clk",
2381                         .parent_names = (const char *[]){
2382                                 "pcnoc_clk_src"
2383                         },
2384                         .num_parents = 1,
2385                         .flags = CLK_SET_RATE_PARENT,
2386                         .ops = &clk_branch2_ops,
2387                 },
2388         },
2389 };
2390
2391 static struct clk_branch gcc_pcie0_ahb_clk = {
2392         .halt_reg = 0x75010,
2393         .clkr = {
2394                 .enable_reg = 0x75010,
2395                 .enable_mask = BIT(0),
2396                 .hw.init = &(struct clk_init_data){
2397                         .name = "gcc_pcie0_ahb_clk",
2398                         .parent_names = (const char *[]){
2399                                 "pcnoc_clk_src"
2400                         },
2401                         .num_parents = 1,
2402                         .flags = CLK_SET_RATE_PARENT,
2403                         .ops = &clk_branch2_ops,
2404                 },
2405         },
2406 };
2407
2408 static struct clk_branch gcc_pcie0_aux_clk = {
2409         .halt_reg = 0x75014,
2410         .clkr = {
2411                 .enable_reg = 0x75014,
2412                 .enable_mask = BIT(0),
2413                 .hw.init = &(struct clk_init_data){
2414                         .name = "gcc_pcie0_aux_clk",
2415                         .parent_names = (const char *[]){
2416                                 "pcie0_aux_clk_src"
2417                         },
2418                         .num_parents = 1,
2419                         .flags = CLK_SET_RATE_PARENT,
2420                         .ops = &clk_branch2_ops,
2421                 },
2422         },
2423 };
2424
2425 static struct clk_branch gcc_pcie0_axi_m_clk = {
2426         .halt_reg = 0x75008,
2427         .clkr = {
2428                 .enable_reg = 0x75008,
2429                 .enable_mask = BIT(0),
2430                 .hw.init = &(struct clk_init_data){
2431                         .name = "gcc_pcie0_axi_m_clk",
2432                         .parent_names = (const char *[]){
2433                                 "pcie0_axi_clk_src"
2434                         },
2435                         .num_parents = 1,
2436                         .flags = CLK_SET_RATE_PARENT,
2437                         .ops = &clk_branch2_ops,
2438                 },
2439         },
2440 };
2441
2442 static struct clk_branch gcc_pcie0_axi_s_clk = {
2443         .halt_reg = 0x7500c,
2444         .clkr = {
2445                 .enable_reg = 0x7500c,
2446                 .enable_mask = BIT(0),
2447                 .hw.init = &(struct clk_init_data){
2448                         .name = "gcc_pcie0_axi_s_clk",
2449                         .parent_names = (const char *[]){
2450                                 "pcie0_axi_clk_src"
2451                         },
2452                         .num_parents = 1,
2453                         .flags = CLK_SET_RATE_PARENT,
2454                         .ops = &clk_branch2_ops,
2455                 },
2456         },
2457 };
2458
2459 static struct clk_branch gcc_pcie0_pipe_clk = {
2460         .halt_reg = 0x75018,
2461         .halt_check = BRANCH_HALT_DELAY,
2462         .clkr = {
2463                 .enable_reg = 0x75018,
2464                 .enable_mask = BIT(0),
2465                 .hw.init = &(struct clk_init_data){
2466                         .name = "gcc_pcie0_pipe_clk",
2467                         .parent_names = (const char *[]){
2468                                 "pcie0_pipe_clk_src"
2469                         },
2470                         .num_parents = 1,
2471                         .flags = CLK_SET_RATE_PARENT,
2472                         .ops = &clk_branch2_ops,
2473                 },
2474         },
2475 };
2476
2477 static struct clk_branch gcc_sys_noc_pcie0_axi_clk = {
2478         .halt_reg = 0x26048,
2479         .clkr = {
2480                 .enable_reg = 0x26048,
2481                 .enable_mask = BIT(0),
2482                 .hw.init = &(struct clk_init_data){
2483                         .name = "gcc_sys_noc_pcie0_axi_clk",
2484                         .parent_names = (const char *[]){
2485                                 "pcie0_axi_clk_src"
2486                         },
2487                         .num_parents = 1,
2488                         .flags = CLK_SET_RATE_PARENT,
2489                         .ops = &clk_branch2_ops,
2490                 },
2491         },
2492 };
2493
2494 static struct clk_branch gcc_pcie1_ahb_clk = {
2495         .halt_reg = 0x76010,
2496         .clkr = {
2497                 .enable_reg = 0x76010,
2498                 .enable_mask = BIT(0),
2499                 .hw.init = &(struct clk_init_data){
2500                         .name = "gcc_pcie1_ahb_clk",
2501                         .parent_names = (const char *[]){
2502                                 "pcnoc_clk_src"
2503                         },
2504                         .num_parents = 1,
2505                         .flags = CLK_SET_RATE_PARENT,
2506                         .ops = &clk_branch2_ops,
2507                 },
2508         },
2509 };
2510
2511 static struct clk_branch gcc_pcie1_aux_clk = {
2512         .halt_reg = 0x76014,
2513         .clkr = {
2514                 .enable_reg = 0x76014,
2515                 .enable_mask = BIT(0),
2516                 .hw.init = &(struct clk_init_data){
2517                         .name = "gcc_pcie1_aux_clk",
2518                         .parent_names = (const char *[]){
2519                                 "pcie1_aux_clk_src"
2520                         },
2521                         .num_parents = 1,
2522                         .flags = CLK_SET_RATE_PARENT,
2523                         .ops = &clk_branch2_ops,
2524                 },
2525         },
2526 };
2527
2528 static struct clk_branch gcc_pcie1_axi_m_clk = {
2529         .halt_reg = 0x76008,
2530         .clkr = {
2531                 .enable_reg = 0x76008,
2532                 .enable_mask = BIT(0),
2533                 .hw.init = &(struct clk_init_data){
2534                         .name = "gcc_pcie1_axi_m_clk",
2535                         .parent_names = (const char *[]){
2536                                 "pcie1_axi_clk_src"
2537                         },
2538                         .num_parents = 1,
2539                         .flags = CLK_SET_RATE_PARENT,
2540                         .ops = &clk_branch2_ops,
2541                 },
2542         },
2543 };
2544
2545 static struct clk_branch gcc_pcie1_axi_s_clk = {
2546         .halt_reg = 0x7600c,
2547         .clkr = {
2548                 .enable_reg = 0x7600c,
2549                 .enable_mask = BIT(0),
2550                 .hw.init = &(struct clk_init_data){
2551                         .name = "gcc_pcie1_axi_s_clk",
2552                         .parent_names = (const char *[]){
2553                                 "pcie1_axi_clk_src"
2554                         },
2555                         .num_parents = 1,
2556                         .flags = CLK_SET_RATE_PARENT,
2557                         .ops = &clk_branch2_ops,
2558                 },
2559         },
2560 };
2561
2562 static struct clk_branch gcc_pcie1_pipe_clk = {
2563         .halt_reg = 0x76018,
2564         .halt_check = BRANCH_HALT_DELAY,
2565         .clkr = {
2566                 .enable_reg = 0x76018,
2567                 .enable_mask = BIT(0),
2568                 .hw.init = &(struct clk_init_data){
2569                         .name = "gcc_pcie1_pipe_clk",
2570                         .parent_names = (const char *[]){
2571                                 "pcie1_pipe_clk_src"
2572                         },
2573                         .num_parents = 1,
2574                         .flags = CLK_SET_RATE_PARENT,
2575                         .ops = &clk_branch2_ops,
2576                 },
2577         },
2578 };
2579
2580 static struct clk_branch gcc_sys_noc_pcie1_axi_clk = {
2581         .halt_reg = 0x2604c,
2582         .clkr = {
2583                 .enable_reg = 0x2604c,
2584                 .enable_mask = BIT(0),
2585                 .hw.init = &(struct clk_init_data){
2586                         .name = "gcc_sys_noc_pcie1_axi_clk",
2587                         .parent_names = (const char *[]){
2588                                 "pcie1_axi_clk_src"
2589                         },
2590                         .num_parents = 1,
2591                         .flags = CLK_SET_RATE_PARENT,
2592                         .ops = &clk_branch2_ops,
2593                 },
2594         },
2595 };
2596
2597 static struct clk_branch gcc_usb0_aux_clk = {
2598         .halt_reg = 0x3e044,
2599         .clkr = {
2600                 .enable_reg = 0x3e044,
2601                 .enable_mask = BIT(0),
2602                 .hw.init = &(struct clk_init_data){
2603                         .name = "gcc_usb0_aux_clk",
2604                         .parent_names = (const char *[]){
2605                                 "usb0_aux_clk_src"
2606                         },
2607                         .num_parents = 1,
2608                         .flags = CLK_SET_RATE_PARENT,
2609                         .ops = &clk_branch2_ops,
2610                 },
2611         },
2612 };
2613
2614 static struct clk_branch gcc_sys_noc_usb0_axi_clk = {
2615         .halt_reg = 0x26040,
2616         .clkr = {
2617                 .enable_reg = 0x26040,
2618                 .enable_mask = BIT(0),
2619                 .hw.init = &(struct clk_init_data){
2620                         .name = "gcc_sys_noc_usb0_axi_clk",
2621                         .parent_names = (const char *[]){
2622                                 "usb0_master_clk_src"
2623                         },
2624                         .num_parents = 1,
2625                         .flags = CLK_SET_RATE_PARENT,
2626                         .ops = &clk_branch2_ops,
2627                 },
2628         },
2629 };
2630
2631 static struct clk_branch gcc_usb0_master_clk = {
2632         .halt_reg = 0x3e000,
2633         .clkr = {
2634                 .enable_reg = 0x3e000,
2635                 .enable_mask = BIT(0),
2636                 .hw.init = &(struct clk_init_data){
2637                         .name = "gcc_usb0_master_clk",
2638                         .parent_names = (const char *[]){
2639                                 "usb0_master_clk_src"
2640                         },
2641                         .num_parents = 1,
2642                         .flags = CLK_SET_RATE_PARENT,
2643                         .ops = &clk_branch2_ops,
2644                 },
2645         },
2646 };
2647
2648 static struct clk_branch gcc_usb0_mock_utmi_clk = {
2649         .halt_reg = 0x3e008,
2650         .clkr = {
2651                 .enable_reg = 0x3e008,
2652                 .enable_mask = BIT(0),
2653                 .hw.init = &(struct clk_init_data){
2654                         .name = "gcc_usb0_mock_utmi_clk",
2655                         .parent_names = (const char *[]){
2656                                 "usb0_mock_utmi_clk_src"
2657                         },
2658                         .num_parents = 1,
2659                         .flags = CLK_SET_RATE_PARENT,
2660                         .ops = &clk_branch2_ops,
2661                 },
2662         },
2663 };
2664
2665 static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
2666         .halt_reg = 0x3e080,
2667         .clkr = {
2668                 .enable_reg = 0x3e080,
2669                 .enable_mask = BIT(0),
2670                 .hw.init = &(struct clk_init_data){
2671                         .name = "gcc_usb0_phy_cfg_ahb_clk",
2672                         .parent_names = (const char *[]){
2673                                 "pcnoc_clk_src"
2674                         },
2675                         .num_parents = 1,
2676                         .flags = CLK_SET_RATE_PARENT,
2677                         .ops = &clk_branch2_ops,
2678                 },
2679         },
2680 };
2681
2682 static struct clk_branch gcc_usb0_pipe_clk = {
2683         .halt_reg = 0x3e040,
2684         .halt_check = BRANCH_HALT_DELAY,
2685         .clkr = {
2686                 .enable_reg = 0x3e040,
2687                 .enable_mask = BIT(0),
2688                 .hw.init = &(struct clk_init_data){
2689                         .name = "gcc_usb0_pipe_clk",
2690                         .parent_names = (const char *[]){
2691                                 "usb0_pipe_clk_src"
2692                         },
2693                         .num_parents = 1,
2694                         .flags = CLK_SET_RATE_PARENT,
2695                         .ops = &clk_branch2_ops,
2696                 },
2697         },
2698 };
2699
2700 static struct clk_branch gcc_usb0_sleep_clk = {
2701         .halt_reg = 0x3e004,
2702         .clkr = {
2703                 .enable_reg = 0x3e004,
2704                 .enable_mask = BIT(0),
2705                 .hw.init = &(struct clk_init_data){
2706                         .name = "gcc_usb0_sleep_clk",
2707                         .parent_names = (const char *[]){
2708                                 "gcc_sleep_clk_src"
2709                         },
2710                         .num_parents = 1,
2711                         .flags = CLK_SET_RATE_PARENT,
2712                         .ops = &clk_branch2_ops,
2713                 },
2714         },
2715 };
2716
2717 static struct clk_branch gcc_usb1_aux_clk = {
2718         .halt_reg = 0x3f044,
2719         .clkr = {
2720                 .enable_reg = 0x3f044,
2721                 .enable_mask = BIT(0),
2722                 .hw.init = &(struct clk_init_data){
2723                         .name = "gcc_usb1_aux_clk",
2724                         .parent_names = (const char *[]){
2725                                 "usb1_aux_clk_src"
2726                         },
2727                         .num_parents = 1,
2728                         .flags = CLK_SET_RATE_PARENT,
2729                         .ops = &clk_branch2_ops,
2730                 },
2731         },
2732 };
2733
2734 static struct clk_branch gcc_sys_noc_usb1_axi_clk = {
2735         .halt_reg = 0x26044,
2736         .clkr = {
2737                 .enable_reg = 0x26044,
2738                 .enable_mask = BIT(0),
2739                 .hw.init = &(struct clk_init_data){
2740                         .name = "gcc_sys_noc_usb1_axi_clk",
2741                         .parent_names = (const char *[]){
2742                                 "usb1_master_clk_src"
2743                         },
2744                         .num_parents = 1,
2745                         .flags = CLK_SET_RATE_PARENT,
2746                         .ops = &clk_branch2_ops,
2747                 },
2748         },
2749 };
2750
2751 static struct clk_branch gcc_usb1_master_clk = {
2752         .halt_reg = 0x3f000,
2753         .clkr = {
2754                 .enable_reg = 0x3f000,
2755                 .enable_mask = BIT(0),
2756                 .hw.init = &(struct clk_init_data){
2757                         .name = "gcc_usb1_master_clk",
2758                         .parent_names = (const char *[]){
2759                                 "usb1_master_clk_src"
2760                         },
2761                         .num_parents = 1,
2762                         .flags = CLK_SET_RATE_PARENT,
2763                         .ops = &clk_branch2_ops,
2764                 },
2765         },
2766 };
2767
2768 static struct clk_branch gcc_usb1_mock_utmi_clk = {
2769         .halt_reg = 0x3f008,
2770         .clkr = {
2771                 .enable_reg = 0x3f008,
2772                 .enable_mask = BIT(0),
2773                 .hw.init = &(struct clk_init_data){
2774                         .name = "gcc_usb1_mock_utmi_clk",
2775                         .parent_names = (const char *[]){
2776                                 "usb1_mock_utmi_clk_src"
2777                         },
2778                         .num_parents = 1,
2779                         .flags = CLK_SET_RATE_PARENT,
2780                         .ops = &clk_branch2_ops,
2781                 },
2782         },
2783 };
2784
2785 static struct clk_branch gcc_usb1_phy_cfg_ahb_clk = {
2786         .halt_reg = 0x3f080,
2787         .clkr = {
2788                 .enable_reg = 0x3f080,
2789                 .enable_mask = BIT(0),
2790                 .hw.init = &(struct clk_init_data){
2791                         .name = "gcc_usb1_phy_cfg_ahb_clk",
2792                         .parent_names = (const char *[]){
2793                                 "pcnoc_clk_src"
2794                         },
2795                         .num_parents = 1,
2796                         .flags = CLK_SET_RATE_PARENT,
2797                         .ops = &clk_branch2_ops,
2798                 },
2799         },
2800 };
2801
2802 static struct clk_branch gcc_usb1_pipe_clk = {
2803         .halt_reg = 0x3f040,
2804         .halt_check = BRANCH_HALT_DELAY,
2805         .clkr = {
2806                 .enable_reg = 0x3f040,
2807                 .enable_mask = BIT(0),
2808                 .hw.init = &(struct clk_init_data){
2809                         .name = "gcc_usb1_pipe_clk",
2810                         .parent_names = (const char *[]){
2811                                 "usb1_pipe_clk_src"
2812                         },
2813                         .num_parents = 1,
2814                         .flags = CLK_SET_RATE_PARENT,
2815                         .ops = &clk_branch2_ops,
2816                 },
2817         },
2818 };
2819
2820 static struct clk_branch gcc_usb1_sleep_clk = {
2821         .halt_reg = 0x3f004,
2822         .clkr = {
2823                 .enable_reg = 0x3f004,
2824                 .enable_mask = BIT(0),
2825                 .hw.init = &(struct clk_init_data){
2826                         .name = "gcc_usb1_sleep_clk",
2827                         .parent_names = (const char *[]){
2828                                 "gcc_sleep_clk_src"
2829                         },
2830                         .num_parents = 1,
2831                         .flags = CLK_SET_RATE_PARENT,
2832                         .ops = &clk_branch2_ops,
2833                 },
2834         },
2835 };
2836
2837 static struct clk_branch gcc_sdcc1_ahb_clk = {
2838         .halt_reg = 0x4201c,
2839         .clkr = {
2840                 .enable_reg = 0x4201c,
2841                 .enable_mask = BIT(0),
2842                 .hw.init = &(struct clk_init_data){
2843                         .name = "gcc_sdcc1_ahb_clk",
2844                         .parent_names = (const char *[]){
2845                                 "pcnoc_clk_src"
2846                         },
2847                         .num_parents = 1,
2848                         .flags = CLK_SET_RATE_PARENT,
2849                         .ops = &clk_branch2_ops,
2850                 },
2851         },
2852 };
2853
2854 static struct clk_branch gcc_sdcc1_apps_clk = {
2855         .halt_reg = 0x42018,
2856         .clkr = {
2857                 .enable_reg = 0x42018,
2858                 .enable_mask = BIT(0),
2859                 .hw.init = &(struct clk_init_data){
2860                         .name = "gcc_sdcc1_apps_clk",
2861                         .parent_names = (const char *[]){
2862                                 "sdcc1_apps_clk_src"
2863                         },
2864                         .num_parents = 1,
2865                         .flags = CLK_SET_RATE_PARENT,
2866                         .ops = &clk_branch2_ops,
2867                 },
2868         },
2869 };
2870
2871 static struct clk_branch gcc_sdcc1_ice_core_clk = {
2872         .halt_reg = 0x5d014,
2873         .clkr = {
2874                 .enable_reg = 0x5d014,
2875                 .enable_mask = BIT(0),
2876                 .hw.init = &(struct clk_init_data){
2877                         .name = "gcc_sdcc1_ice_core_clk",
2878                         .parent_names = (const char *[]){
2879                                 "sdcc1_ice_core_clk_src"
2880                         },
2881                         .num_parents = 1,
2882                         .flags = CLK_SET_RATE_PARENT,
2883                         .ops = &clk_branch2_ops,
2884                 },
2885         },
2886 };
2887
2888 static struct clk_branch gcc_sdcc2_ahb_clk = {
2889         .halt_reg = 0x4301c,
2890         .clkr = {
2891                 .enable_reg = 0x4301c,
2892                 .enable_mask = BIT(0),
2893                 .hw.init = &(struct clk_init_data){
2894                         .name = "gcc_sdcc2_ahb_clk",
2895                         .parent_names = (const char *[]){
2896                                 "pcnoc_clk_src"
2897                         },
2898                         .num_parents = 1,
2899                         .flags = CLK_SET_RATE_PARENT,
2900                         .ops = &clk_branch2_ops,
2901                 },
2902         },
2903 };
2904
2905 static struct clk_branch gcc_sdcc2_apps_clk = {
2906         .halt_reg = 0x43018,
2907         .clkr = {
2908                 .enable_reg = 0x43018,
2909                 .enable_mask = BIT(0),
2910                 .hw.init = &(struct clk_init_data){
2911                         .name = "gcc_sdcc2_apps_clk",
2912                         .parent_names = (const char *[]){
2913                                 "sdcc2_apps_clk_src"
2914                         },
2915                         .num_parents = 1,
2916                         .flags = CLK_SET_RATE_PARENT,
2917                         .ops = &clk_branch2_ops,
2918                 },
2919         },
2920 };
2921
2922 static struct clk_branch gcc_mem_noc_nss_axi_clk = {
2923         .halt_reg = 0x1d03c,
2924         .clkr = {
2925                 .enable_reg = 0x1d03c,
2926                 .enable_mask = BIT(0),
2927                 .hw.init = &(struct clk_init_data){
2928                         .name = "gcc_mem_noc_nss_axi_clk",
2929                         .parent_names = (const char *[]){
2930                                 "nss_noc_clk_src"
2931                         },
2932                         .num_parents = 1,
2933                         .flags = CLK_SET_RATE_PARENT,
2934                         .ops = &clk_branch2_ops,
2935                 },
2936         },
2937 };
2938
2939 static struct clk_branch gcc_nss_ce_apb_clk = {
2940         .halt_reg = 0x68174,
2941         .clkr = {
2942                 .enable_reg = 0x68174,
2943                 .enable_mask = BIT(0),
2944                 .hw.init = &(struct clk_init_data){
2945                         .name = "gcc_nss_ce_apb_clk",
2946                         .parent_names = (const char *[]){
2947                                 "nss_ce_clk_src"
2948                         },
2949                         .num_parents = 1,
2950                         .flags = CLK_SET_RATE_PARENT,
2951                         .ops = &clk_branch2_ops,
2952                 },
2953         },
2954 };
2955
2956 static struct clk_branch gcc_nss_ce_axi_clk = {
2957         .halt_reg = 0x68170,
2958         .clkr = {
2959                 .enable_reg = 0x68170,
2960                 .enable_mask = BIT(0),
2961                 .hw.init = &(struct clk_init_data){
2962                         .name = "gcc_nss_ce_axi_clk",
2963                         .parent_names = (const char *[]){
2964                                 "nss_ce_clk_src"
2965                         },
2966                         .num_parents = 1,
2967                         .flags = CLK_SET_RATE_PARENT,
2968                         .ops = &clk_branch2_ops,
2969                 },
2970         },
2971 };
2972
2973 static struct clk_branch gcc_nss_cfg_clk = {
2974         .halt_reg = 0x68160,
2975         .clkr = {
2976                 .enable_reg = 0x68160,
2977                 .enable_mask = BIT(0),
2978                 .hw.init = &(struct clk_init_data){
2979                         .name = "gcc_nss_cfg_clk",
2980                         .parent_names = (const char *[]){
2981                                 "pcnoc_clk_src"
2982                         },
2983                         .num_parents = 1,
2984                         .flags = CLK_SET_RATE_PARENT,
2985                         .ops = &clk_branch2_ops,
2986                 },
2987         },
2988 };
2989
2990 static struct clk_branch gcc_nss_crypto_clk = {
2991         .halt_reg = 0x68164,
2992         .clkr = {
2993                 .enable_reg = 0x68164,
2994                 .enable_mask = BIT(0),
2995                 .hw.init = &(struct clk_init_data){
2996                         .name = "gcc_nss_crypto_clk",
2997                         .parent_names = (const char *[]){
2998                                 "nss_crypto_clk_src"
2999                         },
3000                         .num_parents = 1,
3001                         .flags = CLK_SET_RATE_PARENT,
3002                         .ops = &clk_branch2_ops,
3003                 },
3004         },
3005 };
3006
3007 static struct clk_branch gcc_nss_csr_clk = {
3008         .halt_reg = 0x68318,
3009         .clkr = {
3010                 .enable_reg = 0x68318,
3011                 .enable_mask = BIT(0),
3012                 .hw.init = &(struct clk_init_data){
3013                         .name = "gcc_nss_csr_clk",
3014                         .parent_names = (const char *[]){
3015                                 "nss_ce_clk_src"
3016                         },
3017                         .num_parents = 1,
3018                         .flags = CLK_SET_RATE_PARENT,
3019                         .ops = &clk_branch2_ops,
3020                 },
3021         },
3022 };
3023
3024 static struct clk_branch gcc_nss_edma_cfg_clk = {
3025         .halt_reg = 0x6819c,
3026         .clkr = {
3027                 .enable_reg = 0x6819c,
3028                 .enable_mask = BIT(0),
3029                 .hw.init = &(struct clk_init_data){
3030                         .name = "gcc_nss_edma_cfg_clk",
3031                         .parent_names = (const char *[]){
3032                                 "nss_ppe_clk_src"
3033                         },
3034                         .num_parents = 1,
3035                         .flags = CLK_SET_RATE_PARENT,
3036                         .ops = &clk_branch2_ops,
3037                 },
3038         },
3039 };
3040
3041 static struct clk_branch gcc_nss_edma_clk = {
3042         .halt_reg = 0x68198,
3043         .clkr = {
3044                 .enable_reg = 0x68198,
3045                 .enable_mask = BIT(0),
3046                 .hw.init = &(struct clk_init_data){
3047                         .name = "gcc_nss_edma_clk",
3048                         .parent_names = (const char *[]){
3049                                 "nss_ppe_clk_src"
3050                         },
3051                         .num_parents = 1,
3052                         .flags = CLK_SET_RATE_PARENT,
3053                         .ops = &clk_branch2_ops,
3054                 },
3055         },
3056 };
3057
3058 static struct clk_branch gcc_nss_imem_clk = {
3059         .halt_reg = 0x68178,
3060         .clkr = {
3061                 .enable_reg = 0x68178,
3062                 .enable_mask = BIT(0),
3063                 .hw.init = &(struct clk_init_data){
3064                         .name = "gcc_nss_imem_clk",
3065                         .parent_names = (const char *[]){
3066                                 "nss_imem_clk_src"
3067                         },
3068                         .num_parents = 1,
3069                         .flags = CLK_SET_RATE_PARENT,
3070                         .ops = &clk_branch2_ops,
3071                 },
3072         },
3073 };
3074
3075 static struct clk_branch gcc_nss_noc_clk = {
3076         .halt_reg = 0x68168,
3077         .clkr = {
3078                 .enable_reg = 0x68168,
3079                 .enable_mask = BIT(0),
3080                 .hw.init = &(struct clk_init_data){
3081                         .name = "gcc_nss_noc_clk",
3082                         .parent_names = (const char *[]){
3083                                 "nss_noc_clk_src"
3084                         },
3085                         .num_parents = 1,
3086                         .flags = CLK_SET_RATE_PARENT,
3087                         .ops = &clk_branch2_ops,
3088                 },
3089         },
3090 };
3091
3092 static struct clk_branch gcc_nss_ppe_btq_clk = {
3093         .halt_reg = 0x6833c,
3094         .clkr = {
3095                 .enable_reg = 0x6833c,
3096                 .enable_mask = BIT(0),
3097                 .hw.init = &(struct clk_init_data){
3098                         .name = "gcc_nss_ppe_btq_clk",
3099                         .parent_names = (const char *[]){
3100                                 "nss_ppe_clk_src"
3101                         },
3102                         .num_parents = 1,
3103                         .flags = CLK_SET_RATE_PARENT,
3104                         .ops = &clk_branch2_ops,
3105                 },
3106         },
3107 };
3108
3109 static struct clk_branch gcc_nss_ppe_cfg_clk = {
3110         .halt_reg = 0x68194,
3111         .clkr = {
3112                 .enable_reg = 0x68194,
3113                 .enable_mask = BIT(0),
3114                 .hw.init = &(struct clk_init_data){
3115                         .name = "gcc_nss_ppe_cfg_clk",
3116                         .parent_names = (const char *[]){
3117                                 "nss_ppe_clk_src"
3118                         },
3119                         .num_parents = 1,
3120                         .flags = CLK_SET_RATE_PARENT,
3121                         .ops = &clk_branch2_ops,
3122                 },
3123         },
3124 };
3125
3126 static struct clk_branch gcc_nss_ppe_clk = {
3127         .halt_reg = 0x68190,
3128         .clkr = {
3129                 .enable_reg = 0x68190,
3130                 .enable_mask = BIT(0),
3131                 .hw.init = &(struct clk_init_data){
3132                         .name = "gcc_nss_ppe_clk",
3133                         .parent_names = (const char *[]){
3134                                 "nss_ppe_clk_src"
3135                         },
3136                         .num_parents = 1,
3137                         .flags = CLK_SET_RATE_PARENT,
3138                         .ops = &clk_branch2_ops,
3139                 },
3140         },
3141 };
3142
3143 static struct clk_branch gcc_nss_ppe_ipe_clk = {
3144         .halt_reg = 0x68338,
3145         .clkr = {
3146                 .enable_reg = 0x68338,
3147                 .enable_mask = BIT(0),
3148                 .hw.init = &(struct clk_init_data){
3149                         .name = "gcc_nss_ppe_ipe_clk",
3150                         .parent_names = (const char *[]){
3151                                 "nss_ppe_clk_src"
3152                         },
3153                         .num_parents = 1,
3154                         .flags = CLK_SET_RATE_PARENT,
3155                         .ops = &clk_branch2_ops,
3156                 },
3157         },
3158 };
3159
3160 static struct clk_branch gcc_nss_ptp_ref_clk = {
3161         .halt_reg = 0x6816c,
3162         .clkr = {
3163                 .enable_reg = 0x6816c,
3164                 .enable_mask = BIT(0),
3165                 .hw.init = &(struct clk_init_data){
3166                         .name = "gcc_nss_ptp_ref_clk",
3167                         .parent_names = (const char *[]){
3168                                 "nss_ppe_cdiv_clk_src"
3169                         },
3170                         .num_parents = 1,
3171                         .flags = CLK_SET_RATE_PARENT,
3172                         .ops = &clk_branch2_ops,
3173                 },
3174         },
3175 };
3176
3177 static struct clk_branch gcc_nssnoc_ce_apb_clk = {
3178         .halt_reg = 0x6830c,
3179         .clkr = {
3180                 .enable_reg = 0x6830c,
3181                 .enable_mask = BIT(0),
3182                 .hw.init = &(struct clk_init_data){
3183                         .name = "gcc_nssnoc_ce_apb_clk",
3184                         .parent_names = (const char *[]){
3185                                 "nss_ce_clk_src"
3186                         },
3187                         .num_parents = 1,
3188                         .flags = CLK_SET_RATE_PARENT,
3189                         .ops = &clk_branch2_ops,
3190                 },
3191         },
3192 };
3193
3194 static struct clk_branch gcc_nssnoc_ce_axi_clk = {
3195         .halt_reg = 0x68308,
3196         .clkr = {
3197                 .enable_reg = 0x68308,
3198                 .enable_mask = BIT(0),
3199                 .hw.init = &(struct clk_init_data){
3200                         .name = "gcc_nssnoc_ce_axi_clk",
3201                         .parent_names = (const char *[]){
3202                                 "nss_ce_clk_src"
3203                         },
3204                         .num_parents = 1,
3205                         .flags = CLK_SET_RATE_PARENT,
3206                         .ops = &clk_branch2_ops,
3207                 },
3208         },
3209 };
3210
3211 static struct clk_branch gcc_nssnoc_crypto_clk = {
3212         .halt_reg = 0x68314,
3213         .clkr = {
3214                 .enable_reg = 0x68314,
3215                 .enable_mask = BIT(0),
3216                 .hw.init = &(struct clk_init_data){
3217                         .name = "gcc_nssnoc_crypto_clk",
3218                         .parent_names = (const char *[]){
3219                                 "nss_crypto_clk_src"
3220                         },
3221                         .num_parents = 1,
3222                         .flags = CLK_SET_RATE_PARENT,
3223                         .ops = &clk_branch2_ops,
3224                 },
3225         },
3226 };
3227
3228 static struct clk_branch gcc_nssnoc_ppe_cfg_clk = {
3229         .halt_reg = 0x68304,
3230         .clkr = {
3231                 .enable_reg = 0x68304,
3232                 .enable_mask = BIT(0),
3233                 .hw.init = &(struct clk_init_data){
3234                         .name = "gcc_nssnoc_ppe_cfg_clk",
3235                         .parent_names = (const char *[]){
3236                                 "nss_ppe_clk_src"
3237                         },
3238                         .num_parents = 1,
3239                         .flags = CLK_SET_RATE_PARENT,
3240                         .ops = &clk_branch2_ops,
3241                 },
3242         },
3243 };
3244
3245 static struct clk_branch gcc_nssnoc_ppe_clk = {
3246         .halt_reg = 0x68300,
3247         .clkr = {
3248                 .enable_reg = 0x68300,
3249                 .enable_mask = BIT(0),
3250                 .hw.init = &(struct clk_init_data){
3251                         .name = "gcc_nssnoc_ppe_clk",
3252                         .parent_names = (const char *[]){
3253                                 "nss_ppe_clk_src"
3254                         },
3255                         .num_parents = 1,
3256                         .flags = CLK_SET_RATE_PARENT,
3257                         .ops = &clk_branch2_ops,
3258                 },
3259         },
3260 };
3261
3262 static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {
3263         .halt_reg = 0x68180,
3264         .clkr = {
3265                 .enable_reg = 0x68180,
3266                 .enable_mask = BIT(0),
3267                 .hw.init = &(struct clk_init_data){
3268                         .name = "gcc_nssnoc_qosgen_ref_clk",
3269                         .parent_names = (const char *[]){
3270                                 "gcc_xo_clk_src"
3271                         },
3272                         .num_parents = 1,
3273                         .flags = CLK_SET_RATE_PARENT,
3274                         .ops = &clk_branch2_ops,
3275                 },
3276         },
3277 };
3278
3279 static struct clk_branch gcc_nssnoc_snoc_clk = {
3280         .halt_reg = 0x68188,
3281         .clkr = {
3282                 .enable_reg = 0x68188,
3283                 .enable_mask = BIT(0),
3284                 .hw.init = &(struct clk_init_data){
3285                         .name = "gcc_nssnoc_snoc_clk",
3286                         .parent_names = (const char *[]){
3287                                 "system_noc_clk_src"
3288                         },
3289                         .num_parents = 1,
3290                         .flags = CLK_SET_RATE_PARENT,
3291                         .ops = &clk_branch2_ops,
3292                 },
3293         },
3294 };
3295
3296 static struct clk_branch gcc_nssnoc_timeout_ref_clk = {
3297         .halt_reg = 0x68184,
3298         .clkr = {
3299                 .enable_reg = 0x68184,
3300                 .enable_mask = BIT(0),
3301                 .hw.init = &(struct clk_init_data){
3302                         .name = "gcc_nssnoc_timeout_ref_clk",
3303                         .parent_names = (const char *[]){
3304                                 "gcc_xo_div4_clk_src"
3305                         },
3306                         .num_parents = 1,
3307                         .flags = CLK_SET_RATE_PARENT,
3308                         .ops = &clk_branch2_ops,
3309                 },
3310         },
3311 };
3312
3313 static struct clk_branch gcc_nssnoc_ubi0_ahb_clk = {
3314         .halt_reg = 0x68270,
3315         .clkr = {
3316                 .enable_reg = 0x68270,
3317                 .enable_mask = BIT(0),
3318                 .hw.init = &(struct clk_init_data){
3319                         .name = "gcc_nssnoc_ubi0_ahb_clk",
3320                         .parent_names = (const char *[]){
3321                                 "nss_ce_clk_src"
3322                         },
3323                         .num_parents = 1,
3324                         .flags = CLK_SET_RATE_PARENT,
3325                         .ops = &clk_branch2_ops,
3326                 },
3327         },
3328 };
3329
3330 static struct clk_branch gcc_nssnoc_ubi1_ahb_clk = {
3331         .halt_reg = 0x68274,
3332         .clkr = {
3333                 .enable_reg = 0x68274,
3334                 .enable_mask = BIT(0),
3335                 .hw.init = &(struct clk_init_data){
3336                         .name = "gcc_nssnoc_ubi1_ahb_clk",
3337                         .parent_names = (const char *[]){
3338                                 "nss_ce_clk_src"
3339                         },
3340                         .num_parents = 1,
3341                         .flags = CLK_SET_RATE_PARENT,
3342                         .ops = &clk_branch2_ops,
3343                 },
3344         },
3345 };
3346
3347 static struct clk_branch gcc_ubi0_ahb_clk = {
3348         .halt_reg = 0x6820c,
3349         .clkr = {
3350                 .enable_reg = 0x6820c,
3351                 .enable_mask = BIT(0),
3352                 .hw.init = &(struct clk_init_data){
3353                         .name = "gcc_ubi0_ahb_clk",
3354                         .parent_names = (const char *[]){
3355                                 "nss_ce_clk_src"
3356                         },
3357                         .num_parents = 1,
3358                         .flags = CLK_SET_RATE_PARENT,
3359                         .ops = &clk_branch2_ops,
3360                 },
3361         },
3362 };
3363
3364 static struct clk_branch gcc_ubi0_axi_clk = {
3365         .halt_reg = 0x68200,
3366         .clkr = {
3367                 .enable_reg = 0x68200,
3368                 .enable_mask = BIT(0),
3369                 .hw.init = &(struct clk_init_data){
3370                         .name = "gcc_ubi0_axi_clk",
3371                         .parent_names = (const char *[]){
3372                                 "nss_noc_clk_src"
3373                         },
3374                         .num_parents = 1,
3375                         .flags = CLK_SET_RATE_PARENT,
3376                         .ops = &clk_branch2_ops,
3377                 },
3378         },
3379 };
3380
3381 static struct clk_branch gcc_ubi0_nc_axi_clk = {
3382         .halt_reg = 0x68204,
3383         .clkr = {
3384                 .enable_reg = 0x68204,
3385                 .enable_mask = BIT(0),
3386                 .hw.init = &(struct clk_init_data){
3387                         .name = "gcc_ubi0_nc_axi_clk",
3388                         .parent_names = (const char *[]){
3389                                 "nss_noc_clk_src"
3390                         },
3391                         .num_parents = 1,
3392                         .flags = CLK_SET_RATE_PARENT,
3393                         .ops = &clk_branch2_ops,
3394                 },
3395         },
3396 };
3397
3398 static struct clk_branch gcc_ubi0_core_clk = {
3399         .halt_reg = 0x68210,
3400         .clkr = {
3401                 .enable_reg = 0x68210,
3402                 .enable_mask = BIT(0),
3403                 .hw.init = &(struct clk_init_data){
3404                         .name = "gcc_ubi0_core_clk",
3405                         .parent_names = (const char *[]){
3406                                 "nss_ubi0_div_clk_src"
3407                         },
3408                         .num_parents = 1,
3409                         .flags = CLK_SET_RATE_PARENT,
3410                         .ops = &clk_branch2_ops,
3411                 },
3412         },
3413 };
3414
3415 static struct clk_branch gcc_ubi0_mpt_clk = {
3416         .halt_reg = 0x68208,
3417         .clkr = {
3418                 .enable_reg = 0x68208,
3419                 .enable_mask = BIT(0),
3420                 .hw.init = &(struct clk_init_data){
3421                         .name = "gcc_ubi0_mpt_clk",
3422                         .parent_names = (const char *[]){
3423                                 "ubi_mpt_clk_src"
3424                         },
3425                         .num_parents = 1,
3426                         .flags = CLK_SET_RATE_PARENT,
3427                         .ops = &clk_branch2_ops,
3428                 },
3429         },
3430 };
3431
3432 static struct clk_branch gcc_ubi1_ahb_clk = {
3433         .halt_reg = 0x6822c,
3434         .clkr = {
3435                 .enable_reg = 0x6822c,
3436                 .enable_mask = BIT(0),
3437                 .hw.init = &(struct clk_init_data){
3438                         .name = "gcc_ubi1_ahb_clk",
3439                         .parent_names = (const char *[]){
3440                                 "nss_ce_clk_src"
3441                         },
3442                         .num_parents = 1,
3443                         .flags = CLK_SET_RATE_PARENT,
3444                         .ops = &clk_branch2_ops,
3445                 },
3446         },
3447 };
3448
3449 static struct clk_branch gcc_ubi1_axi_clk = {
3450         .halt_reg = 0x68220,
3451         .clkr = {
3452                 .enable_reg = 0x68220,
3453                 .enable_mask = BIT(0),
3454                 .hw.init = &(struct clk_init_data){
3455                         .name = "gcc_ubi1_axi_clk",
3456                         .parent_names = (const char *[]){
3457                                 "nss_noc_clk_src"
3458                         },
3459                         .num_parents = 1,
3460                         .flags = CLK_SET_RATE_PARENT,
3461                         .ops = &clk_branch2_ops,
3462                 },
3463         },
3464 };
3465
3466 static struct clk_branch gcc_ubi1_nc_axi_clk = {
3467         .halt_reg = 0x68224,
3468         .clkr = {
3469                 .enable_reg = 0x68224,
3470                 .enable_mask = BIT(0),
3471                 .hw.init = &(struct clk_init_data){
3472                         .name = "gcc_ubi1_nc_axi_clk",
3473                         .parent_names = (const char *[]){
3474                                 "nss_noc_clk_src"
3475                         },
3476                         .num_parents = 1,
3477                         .flags = CLK_SET_RATE_PARENT,
3478                         .ops = &clk_branch2_ops,
3479                 },
3480         },
3481 };
3482
3483 static struct clk_branch gcc_ubi1_core_clk = {
3484         .halt_reg = 0x68230,
3485         .clkr = {
3486                 .enable_reg = 0x68230,
3487                 .enable_mask = BIT(0),
3488                 .hw.init = &(struct clk_init_data){
3489                         .name = "gcc_ubi1_core_clk",
3490                         .parent_names = (const char *[]){
3491                                 "nss_ubi1_div_clk_src"
3492                         },
3493                         .num_parents = 1,
3494                         .flags = CLK_SET_RATE_PARENT,
3495                         .ops = &clk_branch2_ops,
3496                 },
3497         },
3498 };
3499
3500 static struct clk_branch gcc_ubi1_mpt_clk = {
3501         .halt_reg = 0x68228,
3502         .clkr = {
3503                 .enable_reg = 0x68228,
3504                 .enable_mask = BIT(0),
3505                 .hw.init = &(struct clk_init_data){
3506                         .name = "gcc_ubi1_mpt_clk",
3507                         .parent_names = (const char *[]){
3508                                 "ubi_mpt_clk_src"
3509                         },
3510                         .num_parents = 1,
3511                         .flags = CLK_SET_RATE_PARENT,
3512                         .ops = &clk_branch2_ops,
3513                 },
3514         },
3515 };
3516
3517 static struct clk_branch gcc_cmn_12gpll_ahb_clk = {
3518         .halt_reg = 0x56308,
3519         .clkr = {
3520                 .enable_reg = 0x56308,
3521                 .enable_mask = BIT(0),
3522                 .hw.init = &(struct clk_init_data){
3523                         .name = "gcc_cmn_12gpll_ahb_clk",
3524                         .parent_names = (const char *[]){
3525                                 "pcnoc_clk_src"
3526                         },
3527                         .num_parents = 1,
3528                         .flags = CLK_SET_RATE_PARENT,
3529                         .ops = &clk_branch2_ops,
3530                 },
3531         },
3532 };
3533
3534 static struct clk_branch gcc_cmn_12gpll_sys_clk = {
3535         .halt_reg = 0x5630c,
3536         .clkr = {
3537                 .enable_reg = 0x5630c,
3538                 .enable_mask = BIT(0),
3539                 .hw.init = &(struct clk_init_data){
3540                         .name = "gcc_cmn_12gpll_sys_clk",
3541                         .parent_names = (const char *[]){
3542                                 "gcc_xo_clk_src"
3543                         },
3544                         .num_parents = 1,
3545                         .flags = CLK_SET_RATE_PARENT,
3546                         .ops = &clk_branch2_ops,
3547                 },
3548         },
3549 };
3550
3551 static struct clk_branch gcc_mdio_ahb_clk = {
3552         .halt_reg = 0x58004,
3553         .clkr = {
3554                 .enable_reg = 0x58004,
3555                 .enable_mask = BIT(0),
3556                 .hw.init = &(struct clk_init_data){
3557                         .name = "gcc_mdio_ahb_clk",
3558                         .parent_names = (const char *[]){
3559                                 "pcnoc_clk_src"
3560                         },
3561                         .num_parents = 1,
3562                         .flags = CLK_SET_RATE_PARENT,
3563                         .ops = &clk_branch2_ops,
3564                 },
3565         },
3566 };
3567
3568 static struct clk_branch gcc_uniphy0_ahb_clk = {
3569         .halt_reg = 0x56008,
3570         .clkr = {
3571                 .enable_reg = 0x56008,
3572                 .enable_mask = BIT(0),
3573                 .hw.init = &(struct clk_init_data){
3574                         .name = "gcc_uniphy0_ahb_clk",
3575                         .parent_names = (const char *[]){
3576                                 "pcnoc_clk_src"
3577                         },
3578                         .num_parents = 1,
3579                         .flags = CLK_SET_RATE_PARENT,
3580                         .ops = &clk_branch2_ops,
3581                 },
3582         },
3583 };
3584
3585 static struct clk_branch gcc_uniphy0_sys_clk = {
3586         .halt_reg = 0x5600c,
3587         .clkr = {
3588                 .enable_reg = 0x5600c,
3589                 .enable_mask = BIT(0),
3590                 .hw.init = &(struct clk_init_data){
3591                         .name = "gcc_uniphy0_sys_clk",
3592                         .parent_names = (const char *[]){
3593                                 "gcc_xo_clk_src"
3594                         },
3595                         .num_parents = 1,
3596                         .flags = CLK_SET_RATE_PARENT,
3597                         .ops = &clk_branch2_ops,
3598                 },
3599         },
3600 };
3601
3602 static struct clk_branch gcc_uniphy1_ahb_clk = {
3603         .halt_reg = 0x56108,
3604         .clkr = {
3605                 .enable_reg = 0x56108,
3606                 .enable_mask = BIT(0),
3607                 .hw.init = &(struct clk_init_data){
3608                         .name = "gcc_uniphy1_ahb_clk",
3609                         .parent_names = (const char *[]){
3610                                 "pcnoc_clk_src"
3611                         },
3612                         .num_parents = 1,
3613                         .flags = CLK_SET_RATE_PARENT,
3614                         .ops = &clk_branch2_ops,
3615                 },
3616         },
3617 };
3618
3619 static struct clk_branch gcc_uniphy1_sys_clk = {
3620         .halt_reg = 0x5610c,
3621         .clkr = {
3622                 .enable_reg = 0x5610c,
3623                 .enable_mask = BIT(0),
3624                 .hw.init = &(struct clk_init_data){
3625                         .name = "gcc_uniphy1_sys_clk",
3626                         .parent_names = (const char *[]){
3627                                 "gcc_xo_clk_src"
3628                         },
3629                         .num_parents = 1,
3630                         .flags = CLK_SET_RATE_PARENT,
3631                         .ops = &clk_branch2_ops,
3632                 },
3633         },
3634 };
3635
3636 static struct clk_branch gcc_uniphy2_ahb_clk = {
3637         .halt_reg = 0x56208,
3638         .clkr = {
3639                 .enable_reg = 0x56208,
3640                 .enable_mask = BIT(0),
3641                 .hw.init = &(struct clk_init_data){
3642                         .name = "gcc_uniphy2_ahb_clk",
3643                         .parent_names = (const char *[]){
3644                                 "pcnoc_clk_src"
3645                         },
3646                         .num_parents = 1,
3647                         .flags = CLK_SET_RATE_PARENT,
3648                         .ops = &clk_branch2_ops,
3649                 },
3650         },
3651 };
3652
3653 static struct clk_branch gcc_uniphy2_sys_clk = {
3654         .halt_reg = 0x5620c,
3655         .clkr = {
3656                 .enable_reg = 0x5620c,
3657                 .enable_mask = BIT(0),
3658                 .hw.init = &(struct clk_init_data){
3659                         .name = "gcc_uniphy2_sys_clk",
3660                         .parent_names = (const char *[]){
3661                                 "gcc_xo_clk_src"
3662                         },
3663                         .num_parents = 1,
3664                         .flags = CLK_SET_RATE_PARENT,
3665                         .ops = &clk_branch2_ops,
3666                 },
3667         },
3668 };
3669
3670 static struct clk_branch gcc_nss_port1_rx_clk = {
3671         .halt_reg = 0x68240,
3672         .clkr = {
3673                 .enable_reg = 0x68240,
3674                 .enable_mask = BIT(0),
3675                 .hw.init = &(struct clk_init_data){
3676                         .name = "gcc_nss_port1_rx_clk",
3677                         .parent_names = (const char *[]){
3678                                 "nss_port1_rx_div_clk_src"
3679                         },
3680                         .num_parents = 1,
3681                         .flags = CLK_SET_RATE_PARENT,
3682                         .ops = &clk_branch2_ops,
3683                 },
3684         },
3685 };
3686
3687 static struct clk_branch gcc_nss_port1_tx_clk = {
3688         .halt_reg = 0x68244,
3689         .clkr = {
3690                 .enable_reg = 0x68244,
3691                 .enable_mask = BIT(0),
3692                 .hw.init = &(struct clk_init_data){
3693                         .name = "gcc_nss_port1_tx_clk",
3694                         .parent_names = (const char *[]){
3695                                 "nss_port1_tx_div_clk_src"
3696                         },
3697                         .num_parents = 1,
3698                         .flags = CLK_SET_RATE_PARENT,
3699                         .ops = &clk_branch2_ops,
3700                 },
3701         },
3702 };
3703
3704 static struct clk_branch gcc_nss_port2_rx_clk = {
3705         .halt_reg = 0x68248,
3706         .clkr = {
3707                 .enable_reg = 0x68248,
3708                 .enable_mask = BIT(0),
3709                 .hw.init = &(struct clk_init_data){
3710                         .name = "gcc_nss_port2_rx_clk",
3711                         .parent_names = (const char *[]){
3712                                 "nss_port2_rx_div_clk_src"
3713                         },
3714                         .num_parents = 1,
3715                         .flags = CLK_SET_RATE_PARENT,
3716                         .ops = &clk_branch2_ops,
3717                 },
3718         },
3719 };
3720
3721 static struct clk_branch gcc_nss_port2_tx_clk = {
3722         .halt_reg = 0x6824c,
3723         .clkr = {
3724                 .enable_reg = 0x6824c,
3725                 .enable_mask = BIT(0),
3726                 .hw.init = &(struct clk_init_data){
3727                         .name = "gcc_nss_port2_tx_clk",
3728                         .parent_names = (const char *[]){
3729                                 "nss_port2_tx_div_clk_src"
3730                         },
3731                         .num_parents = 1,
3732                         .flags = CLK_SET_RATE_PARENT,
3733                         .ops = &clk_branch2_ops,
3734                 },
3735         },
3736 };
3737
3738 static struct clk_branch gcc_nss_port3_rx_clk = {
3739         .halt_reg = 0x68250,
3740         .clkr = {
3741                 .enable_reg = 0x68250,
3742                 .enable_mask = BIT(0),
3743                 .hw.init = &(struct clk_init_data){
3744                         .name = "gcc_nss_port3_rx_clk",
3745                         .parent_names = (const char *[]){
3746                                 "nss_port3_rx_div_clk_src"
3747                         },
3748                         .num_parents = 1,
3749                         .flags = CLK_SET_RATE_PARENT,
3750                         .ops = &clk_branch2_ops,
3751                 },
3752         },
3753 };
3754
3755 static struct clk_branch gcc_nss_port3_tx_clk = {
3756         .halt_reg = 0x68254,
3757         .clkr = {
3758                 .enable_reg = 0x68254,
3759                 .enable_mask = BIT(0),
3760                 .hw.init = &(struct clk_init_data){
3761                         .name = "gcc_nss_port3_tx_clk",
3762                         .parent_names = (const char *[]){
3763                                 "nss_port3_tx_div_clk_src"
3764                         },
3765                         .num_parents = 1,
3766                         .flags = CLK_SET_RATE_PARENT,
3767                         .ops = &clk_branch2_ops,
3768                 },
3769         },
3770 };
3771
3772 static struct clk_branch gcc_nss_port4_rx_clk = {
3773         .halt_reg = 0x68258,
3774         .clkr = {
3775                 .enable_reg = 0x68258,
3776                 .enable_mask = BIT(0),
3777                 .hw.init = &(struct clk_init_data){
3778                         .name = "gcc_nss_port4_rx_clk",
3779                         .parent_names = (const char *[]){
3780                                 "nss_port4_rx_div_clk_src"
3781                         },
3782                         .num_parents = 1,
3783                         .flags = CLK_SET_RATE_PARENT,
3784                         .ops = &clk_branch2_ops,
3785                 },
3786         },
3787 };
3788
3789 static struct clk_branch gcc_nss_port4_tx_clk = {
3790         .halt_reg = 0x6825c,
3791         .clkr = {
3792                 .enable_reg = 0x6825c,
3793                 .enable_mask = BIT(0),
3794                 .hw.init = &(struct clk_init_data){
3795                         .name = "gcc_nss_port4_tx_clk",
3796                         .parent_names = (const char *[]){
3797                                 "nss_port4_tx_div_clk_src"
3798                         },
3799                         .num_parents = 1,
3800                         .flags = CLK_SET_RATE_PARENT,
3801                         .ops = &clk_branch2_ops,
3802                 },
3803         },
3804 };
3805
3806 static struct clk_branch gcc_nss_port5_rx_clk = {
3807         .halt_reg = 0x68260,
3808         .clkr = {
3809                 .enable_reg = 0x68260,
3810                 .enable_mask = BIT(0),
3811                 .hw.init = &(struct clk_init_data){
3812                         .name = "gcc_nss_port5_rx_clk",
3813                         .parent_names = (const char *[]){
3814                                 "nss_port5_rx_div_clk_src"
3815                         },
3816                         .num_parents = 1,
3817                         .flags = CLK_SET_RATE_PARENT,
3818                         .ops = &clk_branch2_ops,
3819                 },
3820         },
3821 };
3822
3823 static struct clk_branch gcc_nss_port5_tx_clk = {
3824         .halt_reg = 0x68264,
3825         .clkr = {
3826                 .enable_reg = 0x68264,
3827                 .enable_mask = BIT(0),
3828                 .hw.init = &(struct clk_init_data){
3829                         .name = "gcc_nss_port5_tx_clk",
3830                         .parent_names = (const char *[]){
3831                                 "nss_port5_tx_div_clk_src"
3832                         },
3833                         .num_parents = 1,
3834                         .flags = CLK_SET_RATE_PARENT,
3835                         .ops = &clk_branch2_ops,
3836                 },
3837         },
3838 };
3839
3840 static struct clk_branch gcc_nss_port6_rx_clk = {
3841         .halt_reg = 0x68268,
3842         .clkr = {
3843                 .enable_reg = 0x68268,
3844                 .enable_mask = BIT(0),
3845                 .hw.init = &(struct clk_init_data){
3846                         .name = "gcc_nss_port6_rx_clk",
3847                         .parent_names = (const char *[]){
3848                                 "nss_port6_rx_div_clk_src"
3849                         },
3850                         .num_parents = 1,
3851                         .flags = CLK_SET_RATE_PARENT,
3852                         .ops = &clk_branch2_ops,
3853                 },
3854         },
3855 };
3856
3857 static struct clk_branch gcc_nss_port6_tx_clk = {
3858         .halt_reg = 0x6826c,
3859         .clkr = {
3860                 .enable_reg = 0x6826c,
3861                 .enable_mask = BIT(0),
3862                 .hw.init = &(struct clk_init_data){
3863                         .name = "gcc_nss_port6_tx_clk",
3864                         .parent_names = (const char *[]){
3865                                 "nss_port6_tx_div_clk_src"
3866                         },
3867                         .num_parents = 1,
3868                         .flags = CLK_SET_RATE_PARENT,
3869                         .ops = &clk_branch2_ops,
3870                 },
3871         },
3872 };
3873
3874 static struct clk_branch gcc_port1_mac_clk = {
3875         .halt_reg = 0x68320,
3876         .clkr = {
3877                 .enable_reg = 0x68320,
3878                 .enable_mask = BIT(0),
3879                 .hw.init = &(struct clk_init_data){
3880                         .name = "gcc_port1_mac_clk",
3881                         .parent_names = (const char *[]){
3882                                 "nss_ppe_clk_src"
3883                         },
3884                         .num_parents = 1,
3885                         .flags = CLK_SET_RATE_PARENT,
3886                         .ops = &clk_branch2_ops,
3887                 },
3888         },
3889 };
3890
3891 static struct clk_branch gcc_port2_mac_clk = {
3892         .halt_reg = 0x68324,
3893         .clkr = {
3894                 .enable_reg = 0x68324,
3895                 .enable_mask = BIT(0),
3896                 .hw.init = &(struct clk_init_data){
3897                         .name = "gcc_port2_mac_clk",
3898                         .parent_names = (const char *[]){
3899                                 "nss_ppe_clk_src"
3900                         },
3901                         .num_parents = 1,
3902                         .flags = CLK_SET_RATE_PARENT,
3903                         .ops = &clk_branch2_ops,
3904                 },
3905         },
3906 };
3907
3908 static struct clk_branch gcc_port3_mac_clk = {
3909         .halt_reg = 0x68328,
3910         .clkr = {
3911                 .enable_reg = 0x68328,
3912                 .enable_mask = BIT(0),
3913                 .hw.init = &(struct clk_init_data){
3914                         .name = "gcc_port3_mac_clk",
3915                         .parent_names = (const char *[]){
3916                                 "nss_ppe_clk_src"
3917                         },
3918                         .num_parents = 1,
3919                         .flags = CLK_SET_RATE_PARENT,
3920                         .ops = &clk_branch2_ops,
3921                 },
3922         },
3923 };
3924
3925 static struct clk_branch gcc_port4_mac_clk = {
3926         .halt_reg = 0x6832c,
3927         .clkr = {
3928                 .enable_reg = 0x6832c,
3929                 .enable_mask = BIT(0),
3930                 .hw.init = &(struct clk_init_data){
3931                         .name = "gcc_port4_mac_clk",
3932                         .parent_names = (const char *[]){
3933                                 "nss_ppe_clk_src"
3934                         },
3935                         .num_parents = 1,
3936                         .flags = CLK_SET_RATE_PARENT,
3937                         .ops = &clk_branch2_ops,
3938                 },
3939         },
3940 };
3941
3942 static struct clk_branch gcc_port5_mac_clk = {
3943         .halt_reg = 0x68330,
3944         .clkr = {
3945                 .enable_reg = 0x68330,
3946                 .enable_mask = BIT(0),
3947                 .hw.init = &(struct clk_init_data){
3948                         .name = "gcc_port5_mac_clk",
3949                         .parent_names = (const char *[]){
3950                                 "nss_ppe_clk_src"
3951                         },
3952                         .num_parents = 1,
3953                         .flags = CLK_SET_RATE_PARENT,
3954                         .ops = &clk_branch2_ops,
3955                 },
3956         },
3957 };
3958
3959 static struct clk_branch gcc_port6_mac_clk = {
3960         .halt_reg = 0x68334,
3961         .clkr = {
3962                 .enable_reg = 0x68334,
3963                 .enable_mask = BIT(0),
3964                 .hw.init = &(struct clk_init_data){
3965                         .name = "gcc_port6_mac_clk",
3966                         .parent_names = (const char *[]){
3967                                 "nss_ppe_clk_src"
3968                         },
3969                         .num_parents = 1,
3970                         .flags = CLK_SET_RATE_PARENT,
3971                         .ops = &clk_branch2_ops,
3972                 },
3973         },
3974 };
3975
3976 static struct clk_branch gcc_uniphy0_port1_rx_clk = {
3977         .halt_reg = 0x56010,
3978         .clkr = {
3979                 .enable_reg = 0x56010,
3980                 .enable_mask = BIT(0),
3981                 .hw.init = &(struct clk_init_data){
3982                         .name = "gcc_uniphy0_port1_rx_clk",
3983                         .parent_names = (const char *[]){
3984                                 "nss_port1_rx_div_clk_src"
3985                         },
3986                         .num_parents = 1,
3987                         .flags = CLK_SET_RATE_PARENT,
3988                         .ops = &clk_branch2_ops,
3989                 },
3990         },
3991 };
3992
3993 static struct clk_branch gcc_uniphy0_port1_tx_clk = {
3994         .halt_reg = 0x56014,
3995         .clkr = {
3996                 .enable_reg = 0x56014,
3997                 .enable_mask = BIT(0),
3998                 .hw.init = &(struct clk_init_data){
3999                         .name = "gcc_uniphy0_port1_tx_clk",
4000                         .parent_names = (const char *[]){
4001                                 "nss_port1_tx_div_clk_src"
4002                         },
4003                         .num_parents = 1,
4004                         .flags = CLK_SET_RATE_PARENT,
4005                         .ops = &clk_branch2_ops,
4006                 },
4007         },
4008 };
4009
4010 static struct clk_branch gcc_uniphy0_port2_rx_clk = {
4011         .halt_reg = 0x56018,
4012         .clkr = {
4013                 .enable_reg = 0x56018,
4014                 .enable_mask = BIT(0),
4015                 .hw.init = &(struct clk_init_data){
4016                         .name = "gcc_uniphy0_port2_rx_clk",
4017                         .parent_names = (const char *[]){
4018                                 "nss_port2_rx_div_clk_src"
4019                         },
4020                         .num_parents = 1,
4021                         .flags = CLK_SET_RATE_PARENT,
4022                         .ops = &clk_branch2_ops,
4023                 },
4024         },
4025 };
4026
4027 static struct clk_branch gcc_uniphy0_port2_tx_clk = {
4028         .halt_reg = 0x5601c,
4029         .clkr = {
4030                 .enable_reg = 0x5601c,
4031                 .enable_mask = BIT(0),
4032                 .hw.init = &(struct clk_init_data){
4033                         .name = "gcc_uniphy0_port2_tx_clk",
4034                         .parent_names = (const char *[]){
4035                                 "nss_port2_tx_div_clk_src"
4036                         },
4037                         .num_parents = 1,
4038                         .flags = CLK_SET_RATE_PARENT,
4039                         .ops = &clk_branch2_ops,
4040                 },
4041         },
4042 };
4043
4044 static struct clk_branch gcc_uniphy0_port3_rx_clk = {
4045         .halt_reg = 0x56020,
4046         .clkr = {
4047                 .enable_reg = 0x56020,
4048                 .enable_mask = BIT(0),
4049                 .hw.init = &(struct clk_init_data){
4050                         .name = "gcc_uniphy0_port3_rx_clk",
4051                         .parent_names = (const char *[]){
4052                                 "nss_port3_rx_div_clk_src"
4053                         },
4054                         .num_parents = 1,
4055                         .flags = CLK_SET_RATE_PARENT,
4056                         .ops = &clk_branch2_ops,
4057                 },
4058         },
4059 };
4060
4061 static struct clk_branch gcc_uniphy0_port3_tx_clk = {
4062         .halt_reg = 0x56024,
4063         .clkr = {
4064                 .enable_reg = 0x56024,
4065                 .enable_mask = BIT(0),
4066                 .hw.init = &(struct clk_init_data){
4067                         .name = "gcc_uniphy0_port3_tx_clk",
4068                         .parent_names = (const char *[]){
4069                                 "nss_port3_tx_div_clk_src"
4070                         },
4071                         .num_parents = 1,
4072                         .flags = CLK_SET_RATE_PARENT,
4073                         .ops = &clk_branch2_ops,
4074                 },
4075         },
4076 };
4077
4078 static struct clk_branch gcc_uniphy0_port4_rx_clk = {
4079         .halt_reg = 0x56028,
4080         .clkr = {
4081                 .enable_reg = 0x56028,
4082                 .enable_mask = BIT(0),
4083                 .hw.init = &(struct clk_init_data){
4084                         .name = "gcc_uniphy0_port4_rx_clk",
4085                         .parent_names = (const char *[]){
4086                                 "nss_port4_rx_div_clk_src"
4087                         },
4088                         .num_parents = 1,
4089                         .flags = CLK_SET_RATE_PARENT,
4090                         .ops = &clk_branch2_ops,
4091                 },
4092         },
4093 };
4094
4095 static struct clk_branch gcc_uniphy0_port4_tx_clk = {
4096         .halt_reg = 0x5602c,
4097         .clkr = {
4098                 .enable_reg = 0x5602c,
4099                 .enable_mask = BIT(0),
4100                 .hw.init = &(struct clk_init_data){
4101                         .name = "gcc_uniphy0_port4_tx_clk",
4102                         .parent_names = (const char *[]){
4103                                 "nss_port4_tx_div_clk_src"
4104                         },
4105                         .num_parents = 1,
4106                         .flags = CLK_SET_RATE_PARENT,
4107                         .ops = &clk_branch2_ops,
4108                 },
4109         },
4110 };
4111
4112 static struct clk_branch gcc_uniphy0_port5_rx_clk = {
4113         .halt_reg = 0x56030,
4114         .clkr = {
4115                 .enable_reg = 0x56030,
4116                 .enable_mask = BIT(0),
4117                 .hw.init = &(struct clk_init_data){
4118                         .name = "gcc_uniphy0_port5_rx_clk",
4119                         .parent_names = (const char *[]){
4120                                 "nss_port5_rx_div_clk_src"
4121                         },
4122                         .num_parents = 1,
4123                         .flags = CLK_SET_RATE_PARENT,
4124                         .ops = &clk_branch2_ops,
4125                 },
4126         },
4127 };
4128
4129 static struct clk_branch gcc_uniphy0_port5_tx_clk = {
4130         .halt_reg = 0x56034,
4131         .clkr = {
4132                 .enable_reg = 0x56034,
4133                 .enable_mask = BIT(0),
4134                 .hw.init = &(struct clk_init_data){
4135                         .name = "gcc_uniphy0_port5_tx_clk",
4136                         .parent_names = (const char *[]){
4137                                 "nss_port5_tx_div_clk_src"
4138                         },
4139                         .num_parents = 1,
4140                         .flags = CLK_SET_RATE_PARENT,
4141                         .ops = &clk_branch2_ops,
4142                 },
4143         },
4144 };
4145
4146 static struct clk_branch gcc_uniphy1_port5_rx_clk = {
4147         .halt_reg = 0x56110,
4148         .clkr = {
4149                 .enable_reg = 0x56110,
4150                 .enable_mask = BIT(0),
4151                 .hw.init = &(struct clk_init_data){
4152                         .name = "gcc_uniphy1_port5_rx_clk",
4153                         .parent_names = (const char *[]){
4154                                 "nss_port5_rx_div_clk_src"
4155                         },
4156                         .num_parents = 1,
4157                         .flags = CLK_SET_RATE_PARENT,
4158                         .ops = &clk_branch2_ops,
4159                 },
4160         },
4161 };
4162
4163 static struct clk_branch gcc_uniphy1_port5_tx_clk = {
4164         .halt_reg = 0x56114,
4165         .clkr = {
4166                 .enable_reg = 0x56114,
4167                 .enable_mask = BIT(0),
4168                 .hw.init = &(struct clk_init_data){
4169                         .name = "gcc_uniphy1_port5_tx_clk",
4170                         .parent_names = (const char *[]){
4171                                 "nss_port5_tx_div_clk_src"
4172                         },
4173                         .num_parents = 1,
4174                         .flags = CLK_SET_RATE_PARENT,
4175                         .ops = &clk_branch2_ops,
4176                 },
4177         },
4178 };
4179
4180 static struct clk_branch gcc_uniphy2_port6_rx_clk = {
4181         .halt_reg = 0x56210,
4182         .clkr = {
4183                 .enable_reg = 0x56210,
4184                 .enable_mask = BIT(0),
4185                 .hw.init = &(struct clk_init_data){
4186                         .name = "gcc_uniphy2_port6_rx_clk",
4187                         .parent_names = (const char *[]){
4188                                 "nss_port6_rx_div_clk_src"
4189                         },
4190                         .num_parents = 1,
4191                         .flags = CLK_SET_RATE_PARENT,
4192                         .ops = &clk_branch2_ops,
4193                 },
4194         },
4195 };
4196
4197 static struct clk_branch gcc_uniphy2_port6_tx_clk = {
4198         .halt_reg = 0x56214,
4199         .clkr = {
4200                 .enable_reg = 0x56214,
4201                 .enable_mask = BIT(0),
4202                 .hw.init = &(struct clk_init_data){
4203                         .name = "gcc_uniphy2_port6_tx_clk",
4204                         .parent_names = (const char *[]){
4205                                 "nss_port6_tx_div_clk_src"
4206                         },
4207                         .num_parents = 1,
4208                         .flags = CLK_SET_RATE_PARENT,
4209                         .ops = &clk_branch2_ops,
4210                 },
4211         },
4212 };
4213
4214 static struct clk_branch gcc_crypto_ahb_clk = {
4215         .halt_reg = 0x16024,
4216         .halt_check = BRANCH_HALT_VOTED,
4217         .clkr = {
4218                 .enable_reg = 0x0b004,
4219                 .enable_mask = BIT(0),
4220                 .hw.init = &(struct clk_init_data){
4221                         .name = "gcc_crypto_ahb_clk",
4222                         .parent_names = (const char *[]){
4223                                 "pcnoc_clk_src"
4224                         },
4225                         .num_parents = 1,
4226                         .flags = CLK_SET_RATE_PARENT,
4227                         .ops = &clk_branch2_ops,
4228                 },
4229         },
4230 };
4231
4232 static struct clk_branch gcc_crypto_axi_clk = {
4233         .halt_reg = 0x16020,
4234         .halt_check = BRANCH_HALT_VOTED,
4235         .clkr = {
4236                 .enable_reg = 0x0b004,
4237                 .enable_mask = BIT(1),
4238                 .hw.init = &(struct clk_init_data){
4239                         .name = "gcc_crypto_axi_clk",
4240                         .parent_names = (const char *[]){
4241                                 "pcnoc_clk_src"
4242                         },
4243                         .num_parents = 1,
4244                         .flags = CLK_SET_RATE_PARENT,
4245                         .ops = &clk_branch2_ops,
4246                 },
4247         },
4248 };
4249
4250 static struct clk_branch gcc_crypto_clk = {
4251         .halt_reg = 0x1601c,
4252         .halt_check = BRANCH_HALT_VOTED,
4253         .clkr = {
4254                 .enable_reg = 0x0b004,
4255                 .enable_mask = BIT(2),
4256                 .hw.init = &(struct clk_init_data){
4257                         .name = "gcc_crypto_clk",
4258                         .parent_names = (const char *[]){
4259                                 "crypto_clk_src"
4260                         },
4261                         .num_parents = 1,
4262                         .flags = CLK_SET_RATE_PARENT,
4263                         .ops = &clk_branch2_ops,
4264                 },
4265         },
4266 };
4267
4268 static struct clk_branch gcc_gp1_clk = {
4269         .halt_reg = 0x08000,
4270         .clkr = {
4271                 .enable_reg = 0x08000,
4272                 .enable_mask = BIT(0),
4273                 .hw.init = &(struct clk_init_data){
4274                         .name = "gcc_gp1_clk",
4275                         .parent_names = (const char *[]){
4276                                 "gp1_clk_src"
4277                         },
4278                         .num_parents = 1,
4279                         .flags = CLK_SET_RATE_PARENT,
4280                         .ops = &clk_branch2_ops,
4281                 },
4282         },
4283 };
4284
4285 static struct clk_branch gcc_gp2_clk = {
4286         .halt_reg = 0x09000,
4287         .clkr = {
4288                 .enable_reg = 0x09000,
4289                 .enable_mask = BIT(0),
4290                 .hw.init = &(struct clk_init_data){
4291                         .name = "gcc_gp2_clk",
4292                         .parent_names = (const char *[]){
4293                                 "gp2_clk_src"
4294                         },
4295                         .num_parents = 1,
4296                         .flags = CLK_SET_RATE_PARENT,
4297                         .ops = &clk_branch2_ops,
4298                 },
4299         },
4300 };
4301
4302 static struct clk_branch gcc_gp3_clk = {
4303         .halt_reg = 0x0a000,
4304         .clkr = {
4305                 .enable_reg = 0x0a000,
4306                 .enable_mask = BIT(0),
4307                 .hw.init = &(struct clk_init_data){
4308                         .name = "gcc_gp3_clk",
4309                         .parent_names = (const char *[]){
4310                                 "gp3_clk_src"
4311                         },
4312                         .num_parents = 1,
4313                         .flags = CLK_SET_RATE_PARENT,
4314                         .ops = &clk_branch2_ops,
4315                 },
4316         },
4317 };
4318
4319 static struct clk_hw *gcc_ipq8074_hws[] = {
4320         &gpll0_out_main_div2.hw,
4321         &gpll6_out_main_div2.hw,
4322         &pcnoc_clk_src.hw,
4323         &system_noc_clk_src.hw,
4324         &gcc_xo_div4_clk_src.hw,
4325         &nss_noc_clk_src.hw,
4326         &nss_ppe_cdiv_clk_src.hw,
4327 };
4328
4329 static struct clk_regmap *gcc_ipq8074_clks[] = {
4330         [GPLL0_MAIN] = &gpll0_main.clkr,
4331         [GPLL0] = &gpll0.clkr,
4332         [GPLL2_MAIN] = &gpll2_main.clkr,
4333         [GPLL2] = &gpll2.clkr,
4334         [GPLL4_MAIN] = &gpll4_main.clkr,
4335         [GPLL4] = &gpll4.clkr,
4336         [GPLL6_MAIN] = &gpll6_main.clkr,
4337         [GPLL6] = &gpll6.clkr,
4338         [UBI32_PLL_MAIN] = &ubi32_pll_main.clkr,
4339         [UBI32_PLL] = &ubi32_pll.clkr,
4340         [NSS_CRYPTO_PLL_MAIN] = &nss_crypto_pll_main.clkr,
4341         [NSS_CRYPTO_PLL] = &nss_crypto_pll.clkr,
4342         [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
4343         [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
4344         [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
4345         [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
4346         [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
4347         [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
4348         [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
4349         [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
4350         [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
4351         [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
4352         [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
4353         [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
4354         [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
4355         [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
4356         [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
4357         [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
4358         [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
4359         [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
4360         [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
4361         [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
4362         [PCIE0_AXI_CLK_SRC] = &pcie0_axi_clk_src.clkr,
4363         [PCIE0_AUX_CLK_SRC] = &pcie0_aux_clk_src.clkr,
4364         [PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
4365         [PCIE1_AXI_CLK_SRC] = &pcie1_axi_clk_src.clkr,
4366         [PCIE1_AUX_CLK_SRC] = &pcie1_aux_clk_src.clkr,
4367         [PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr,
4368         [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
4369         [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
4370         [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
4371         [USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr,
4372         [USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr,
4373         [USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr,
4374         [USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
4375         [USB1_MASTER_CLK_SRC] = &usb1_master_clk_src.clkr,
4376         [USB1_AUX_CLK_SRC] = &usb1_aux_clk_src.clkr,
4377         [USB1_MOCK_UTMI_CLK_SRC] = &usb1_mock_utmi_clk_src.clkr,
4378         [USB1_PIPE_CLK_SRC] = &usb1_pipe_clk_src.clkr,
4379         [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
4380         [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
4381         [NSS_CE_CLK_SRC] = &nss_ce_clk_src.clkr,
4382         [NSS_NOC_BFDCD_CLK_SRC] = &nss_noc_bfdcd_clk_src.clkr,
4383         [NSS_CRYPTO_CLK_SRC] = &nss_crypto_clk_src.clkr,
4384         [NSS_UBI0_CLK_SRC] = &nss_ubi0_clk_src.clkr,
4385         [NSS_UBI0_DIV_CLK_SRC] = &nss_ubi0_div_clk_src.clkr,
4386         [NSS_UBI1_CLK_SRC] = &nss_ubi1_clk_src.clkr,
4387         [NSS_UBI1_DIV_CLK_SRC] = &nss_ubi1_div_clk_src.clkr,
4388         [UBI_MPT_CLK_SRC] = &ubi_mpt_clk_src.clkr,
4389         [NSS_IMEM_CLK_SRC] = &nss_imem_clk_src.clkr,
4390         [NSS_PPE_CLK_SRC] = &nss_ppe_clk_src.clkr,
4391         [NSS_PORT1_RX_CLK_SRC] = &nss_port1_rx_clk_src.clkr,
4392         [NSS_PORT1_RX_DIV_CLK_SRC] = &nss_port1_rx_div_clk_src.clkr,
4393         [NSS_PORT1_TX_CLK_SRC] = &nss_port1_tx_clk_src.clkr,
4394         [NSS_PORT1_TX_DIV_CLK_SRC] = &nss_port1_tx_div_clk_src.clkr,
4395         [NSS_PORT2_RX_CLK_SRC] = &nss_port2_rx_clk_src.clkr,
4396         [NSS_PORT2_RX_DIV_CLK_SRC] = &nss_port2_rx_div_clk_src.clkr,
4397         [NSS_PORT2_TX_CLK_SRC] = &nss_port2_tx_clk_src.clkr,
4398         [NSS_PORT2_TX_DIV_CLK_SRC] = &nss_port2_tx_div_clk_src.clkr,
4399         [NSS_PORT3_RX_CLK_SRC] = &nss_port3_rx_clk_src.clkr,
4400         [NSS_PORT3_RX_DIV_CLK_SRC] = &nss_port3_rx_div_clk_src.clkr,
4401         [NSS_PORT3_TX_CLK_SRC] = &nss_port3_tx_clk_src.clkr,
4402         [NSS_PORT3_TX_DIV_CLK_SRC] = &nss_port3_tx_div_clk_src.clkr,
4403         [NSS_PORT4_RX_CLK_SRC] = &nss_port4_rx_clk_src.clkr,
4404         [NSS_PORT4_RX_DIV_CLK_SRC] = &nss_port4_rx_div_clk_src.clkr,
4405         [NSS_PORT4_TX_CLK_SRC] = &nss_port4_tx_clk_src.clkr,
4406         [NSS_PORT4_TX_DIV_CLK_SRC] = &nss_port4_tx_div_clk_src.clkr,
4407         [NSS_PORT5_RX_CLK_SRC] = &nss_port5_rx_clk_src.clkr,
4408         [NSS_PORT5_RX_DIV_CLK_SRC] = &nss_port5_rx_div_clk_src.clkr,
4409         [NSS_PORT5_TX_CLK_SRC] = &nss_port5_tx_clk_src.clkr,
4410         [NSS_PORT5_TX_DIV_CLK_SRC] = &nss_port5_tx_div_clk_src.clkr,
4411         [NSS_PORT6_RX_CLK_SRC] = &nss_port6_rx_clk_src.clkr,
4412         [NSS_PORT6_RX_DIV_CLK_SRC] = &nss_port6_rx_div_clk_src.clkr,
4413         [NSS_PORT6_TX_CLK_SRC] = &nss_port6_tx_clk_src.clkr,
4414         [NSS_PORT6_TX_DIV_CLK_SRC] = &nss_port6_tx_div_clk_src.clkr,
4415         [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
4416         [GP1_CLK_SRC] = &gp1_clk_src.clkr,
4417         [GP2_CLK_SRC] = &gp2_clk_src.clkr,
4418         [GP3_CLK_SRC] = &gp3_clk_src.clkr,
4419         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
4420         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
4421         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
4422         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
4423         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
4424         [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
4425         [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
4426         [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
4427         [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
4428         [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
4429         [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
4430         [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
4431         [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
4432         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
4433         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
4434         [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
4435         [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
4436         [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
4437         [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
4438         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
4439         [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
4440         [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
4441         [GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
4442         [GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
4443         [GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
4444         [GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
4445         [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
4446         [GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr,
4447         [GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr,
4448         [GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,
4449         [GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr,
4450         [GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr,
4451         [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
4452         [GCC_SYS_NOC_PCIE1_AXI_CLK] = &gcc_sys_noc_pcie1_axi_clk.clkr,
4453         [GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
4454         [GCC_SYS_NOC_USB0_AXI_CLK] = &gcc_sys_noc_usb0_axi_clk.clkr,
4455         [GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
4456         [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
4457         [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
4458         [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
4459         [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
4460         [GCC_USB1_AUX_CLK] = &gcc_usb1_aux_clk.clkr,
4461         [GCC_SYS_NOC_USB1_AXI_CLK] = &gcc_sys_noc_usb1_axi_clk.clkr,
4462         [GCC_USB1_MASTER_CLK] = &gcc_usb1_master_clk.clkr,
4463         [GCC_USB1_MOCK_UTMI_CLK] = &gcc_usb1_mock_utmi_clk.clkr,
4464         [GCC_USB1_PHY_CFG_AHB_CLK] = &gcc_usb1_phy_cfg_ahb_clk.clkr,
4465         [GCC_USB1_PIPE_CLK] = &gcc_usb1_pipe_clk.clkr,
4466         [GCC_USB1_SLEEP_CLK] = &gcc_usb1_sleep_clk.clkr,
4467         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
4468         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
4469         [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
4470         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
4471         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
4472         [GCC_MEM_NOC_NSS_AXI_CLK] = &gcc_mem_noc_nss_axi_clk.clkr,
4473         [GCC_NSS_CE_APB_CLK] = &gcc_nss_ce_apb_clk.clkr,
4474         [GCC_NSS_CE_AXI_CLK] = &gcc_nss_ce_axi_clk.clkr,
4475         [GCC_NSS_CFG_CLK] = &gcc_nss_cfg_clk.clkr,
4476         [GCC_NSS_CRYPTO_CLK] = &gcc_nss_crypto_clk.clkr,
4477         [GCC_NSS_CSR_CLK] = &gcc_nss_csr_clk.clkr,
4478         [GCC_NSS_EDMA_CFG_CLK] = &gcc_nss_edma_cfg_clk.clkr,
4479         [GCC_NSS_EDMA_CLK] = &gcc_nss_edma_clk.clkr,
4480         [GCC_NSS_IMEM_CLK] = &gcc_nss_imem_clk.clkr,
4481         [GCC_NSS_NOC_CLK] = &gcc_nss_noc_clk.clkr,
4482         [GCC_NSS_PPE_BTQ_CLK] = &gcc_nss_ppe_btq_clk.clkr,
4483         [GCC_NSS_PPE_CFG_CLK] = &gcc_nss_ppe_cfg_clk.clkr,
4484         [GCC_NSS_PPE_CLK] = &gcc_nss_ppe_clk.clkr,
4485         [GCC_NSS_PPE_IPE_CLK] = &gcc_nss_ppe_ipe_clk.clkr,
4486         [GCC_NSS_PTP_REF_CLK] = &gcc_nss_ptp_ref_clk.clkr,
4487         [GCC_NSSNOC_CE_APB_CLK] = &gcc_nssnoc_ce_apb_clk.clkr,
4488         [GCC_NSSNOC_CE_AXI_CLK] = &gcc_nssnoc_ce_axi_clk.clkr,
4489         [GCC_NSSNOC_CRYPTO_CLK] = &gcc_nssnoc_crypto_clk.clkr,
4490         [GCC_NSSNOC_PPE_CFG_CLK] = &gcc_nssnoc_ppe_cfg_clk.clkr,
4491         [GCC_NSSNOC_PPE_CLK] = &gcc_nssnoc_ppe_clk.clkr,
4492         [GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
4493         [GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
4494         [GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,
4495         [GCC_NSSNOC_UBI0_AHB_CLK] = &gcc_nssnoc_ubi0_ahb_clk.clkr,
4496         [GCC_NSSNOC_UBI1_AHB_CLK] = &gcc_nssnoc_ubi1_ahb_clk.clkr,
4497         [GCC_UBI0_AHB_CLK] = &gcc_ubi0_ahb_clk.clkr,
4498         [GCC_UBI0_AXI_CLK] = &gcc_ubi0_axi_clk.clkr,
4499         [GCC_UBI0_NC_AXI_CLK] = &gcc_ubi0_nc_axi_clk.clkr,
4500         [GCC_UBI0_CORE_CLK] = &gcc_ubi0_core_clk.clkr,
4501         [GCC_UBI0_MPT_CLK] = &gcc_ubi0_mpt_clk.clkr,
4502         [GCC_UBI1_AHB_CLK] = &gcc_ubi1_ahb_clk.clkr,
4503         [GCC_UBI1_AXI_CLK] = &gcc_ubi1_axi_clk.clkr,
4504         [GCC_UBI1_NC_AXI_CLK] = &gcc_ubi1_nc_axi_clk.clkr,
4505         [GCC_UBI1_CORE_CLK] = &gcc_ubi1_core_clk.clkr,
4506         [GCC_UBI1_MPT_CLK] = &gcc_ubi1_mpt_clk.clkr,
4507         [GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
4508         [GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
4509         [GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
4510         [GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
4511         [GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
4512         [GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
4513         [GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,
4514         [GCC_UNIPHY2_AHB_CLK] = &gcc_uniphy2_ahb_clk.clkr,
4515         [GCC_UNIPHY2_SYS_CLK] = &gcc_uniphy2_sys_clk.clkr,
4516         [GCC_NSS_PORT1_RX_CLK] = &gcc_nss_port1_rx_clk.clkr,
4517         [GCC_NSS_PORT1_TX_CLK] = &gcc_nss_port1_tx_clk.clkr,
4518         [GCC_NSS_PORT2_RX_CLK] = &gcc_nss_port2_rx_clk.clkr,
4519         [GCC_NSS_PORT2_TX_CLK] = &gcc_nss_port2_tx_clk.clkr,
4520         [GCC_NSS_PORT3_RX_CLK] = &gcc_nss_port3_rx_clk.clkr,
4521         [GCC_NSS_PORT3_TX_CLK] = &gcc_nss_port3_tx_clk.clkr,
4522         [GCC_NSS_PORT4_RX_CLK] = &gcc_nss_port4_rx_clk.clkr,
4523         [GCC_NSS_PORT4_TX_CLK] = &gcc_nss_port4_tx_clk.clkr,
4524         [GCC_NSS_PORT5_RX_CLK] = &gcc_nss_port5_rx_clk.clkr,
4525         [GCC_NSS_PORT5_TX_CLK] = &gcc_nss_port5_tx_clk.clkr,
4526         [GCC_NSS_PORT6_RX_CLK] = &gcc_nss_port6_rx_clk.clkr,
4527         [GCC_NSS_PORT6_TX_CLK] = &gcc_nss_port6_tx_clk.clkr,
4528         [GCC_PORT1_MAC_CLK] = &gcc_port1_mac_clk.clkr,
4529         [GCC_PORT2_MAC_CLK] = &gcc_port2_mac_clk.clkr,
4530         [GCC_PORT3_MAC_CLK] = &gcc_port3_mac_clk.clkr,
4531         [GCC_PORT4_MAC_CLK] = &gcc_port4_mac_clk.clkr,
4532         [GCC_PORT5_MAC_CLK] = &gcc_port5_mac_clk.clkr,
4533         [GCC_PORT6_MAC_CLK] = &gcc_port6_mac_clk.clkr,
4534         [GCC_UNIPHY0_PORT1_RX_CLK] = &gcc_uniphy0_port1_rx_clk.clkr,
4535         [GCC_UNIPHY0_PORT1_TX_CLK] = &gcc_uniphy0_port1_tx_clk.clkr,
4536         [GCC_UNIPHY0_PORT2_RX_CLK] = &gcc_uniphy0_port2_rx_clk.clkr,
4537         [GCC_UNIPHY0_PORT2_TX_CLK] = &gcc_uniphy0_port2_tx_clk.clkr,
4538         [GCC_UNIPHY0_PORT3_RX_CLK] = &gcc_uniphy0_port3_rx_clk.clkr,
4539         [GCC_UNIPHY0_PORT3_TX_CLK] = &gcc_uniphy0_port3_tx_clk.clkr,
4540         [GCC_UNIPHY0_PORT4_RX_CLK] = &gcc_uniphy0_port4_rx_clk.clkr,
4541         [GCC_UNIPHY0_PORT4_TX_CLK] = &gcc_uniphy0_port4_tx_clk.clkr,
4542         [GCC_UNIPHY0_PORT5_RX_CLK] = &gcc_uniphy0_port5_rx_clk.clkr,
4543         [GCC_UNIPHY0_PORT5_TX_CLK] = &gcc_uniphy0_port5_tx_clk.clkr,
4544         [GCC_UNIPHY1_PORT5_RX_CLK] = &gcc_uniphy1_port5_rx_clk.clkr,
4545         [GCC_UNIPHY1_PORT5_TX_CLK] = &gcc_uniphy1_port5_tx_clk.clkr,
4546         [GCC_UNIPHY2_PORT6_RX_CLK] = &gcc_uniphy2_port6_rx_clk.clkr,
4547         [GCC_UNIPHY2_PORT6_TX_CLK] = &gcc_uniphy2_port6_tx_clk.clkr,
4548         [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
4549         [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
4550         [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
4551         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
4552         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
4553         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
4554 };
4555
4556 static const struct qcom_reset_map gcc_ipq8074_resets[] = {
4557         [GCC_BLSP1_BCR] = { 0x01000, 0 },
4558         [GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
4559         [GCC_BLSP1_UART1_BCR] = { 0x02038, 0 },
4560         [GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 },
4561         [GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
4562         [GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 },
4563         [GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
4564         [GCC_BLSP1_QUP4_BCR] = { 0x05008, 0 },
4565         [GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
4566         [GCC_BLSP1_QUP5_BCR] = { 0x06008, 0 },
4567         [GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
4568         [GCC_BLSP1_QUP6_BCR] = { 0x07008, 0 },
4569         [GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
4570         [GCC_IMEM_BCR] = { 0x0e000, 0 },
4571         [GCC_SMMU_BCR] = { 0x12000, 0 },
4572         [GCC_APSS_TCU_BCR] = { 0x12050, 0 },
4573         [GCC_SMMU_XPU_BCR] = { 0x12054, 0 },
4574         [GCC_PCNOC_TBU_BCR] = { 0x12058, 0 },
4575         [GCC_SMMU_CFG_BCR] = { 0x1208c, 0 },
4576         [GCC_PRNG_BCR] = { 0x13000, 0 },
4577         [GCC_BOOT_ROM_BCR] = { 0x13008, 0 },
4578         [GCC_CRYPTO_BCR] = { 0x16000, 0 },
4579         [GCC_WCSS_BCR] = { 0x18000, 0 },
4580         [GCC_WCSS_Q6_BCR] = { 0x18100, 0 },
4581         [GCC_NSS_BCR] = { 0x19000, 0 },
4582         [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
4583         [GCC_ADSS_BCR] = { 0x1c000, 0 },
4584         [GCC_DDRSS_BCR] = { 0x1e000, 0 },
4585         [GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 },
4586         [GCC_PCNOC_BCR] = { 0x27018, 0 },
4587         [GCC_TCSR_BCR] = { 0x28000, 0 },
4588         [GCC_QDSS_BCR] = { 0x29000, 0 },
4589         [GCC_DCD_BCR] = { 0x2a000, 0 },
4590         [GCC_MSG_RAM_BCR] = { 0x2b000, 0 },
4591         [GCC_MPM_BCR] = { 0x2c000, 0 },
4592         [GCC_SPMI_BCR] = { 0x2e000, 0 },
4593         [GCC_SPDM_BCR] = { 0x2f000, 0 },
4594         [GCC_RBCPR_BCR] = { 0x33000, 0 },
4595         [GCC_RBCPR_MX_BCR] = { 0x33014, 0 },
4596         [GCC_TLMM_BCR] = { 0x34000, 0 },
4597         [GCC_RBCPR_WCSS_BCR] = { 0x3a000, 0 },
4598         [GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
4599         [GCC_USB3PHY_0_PHY_BCR] = { 0x3e03c, 0 },
4600         [GCC_USB0_BCR] = { 0x3e070, 0 },
4601         [GCC_USB1_PHY_BCR] = { 0x3f034, 0 },
4602         [GCC_USB3PHY_1_PHY_BCR] = { 0x3f03c, 0 },
4603         [GCC_USB1_BCR] = { 0x3f070, 0 },
4604         [GCC_QUSB2_0_PHY_BCR] = { 0x4103c, 0 },
4605         [GCC_QUSB2_1_PHY_BCR] = { 0x41040, 0 },
4606         [GCC_SDCC1_BCR] = { 0x42000, 0 },
4607         [GCC_SDCC2_BCR] = { 0x43000, 0 },
4608         [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000, 0 },
4609         [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x47008, 0 },
4610         [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x47010, 0 },
4611         [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 },
4612         [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 },
4613         [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 },
4614         [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 },
4615         [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 },
4616         [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 },
4617         [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 },
4618         [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 },
4619         [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 },
4620         [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 },
4621         [GCC_UNIPHY0_BCR] = { 0x56000, 0 },
4622         [GCC_UNIPHY1_BCR] = { 0x56100, 0 },
4623         [GCC_UNIPHY2_BCR] = { 0x56200, 0 },
4624         [GCC_CMN_12GPLL_BCR] = { 0x56300, 0 },
4625         [GCC_QPIC_BCR] = { 0x57018, 0 },
4626         [GCC_MDIO_BCR] = { 0x58000, 0 },
4627         [GCC_PCIE1_TBU_BCR] = { 0x65000, 0 },
4628         [GCC_WCSS_CORE_TBU_BCR] = { 0x66000, 0 },
4629         [GCC_WCSS_Q6_TBU_BCR] = { 0x67000, 0 },
4630         [GCC_USB0_TBU_BCR] = { 0x6a000, 0 },
4631         [GCC_USB1_TBU_BCR] = { 0x6a004, 0 },
4632         [GCC_PCIE0_TBU_BCR] = { 0x6b000, 0 },
4633         [GCC_NSS_NOC_TBU_BCR] = { 0x6e000, 0 },
4634         [GCC_PCIE0_BCR] = { 0x75004, 0 },
4635         [GCC_PCIE0_PHY_BCR] = { 0x75038, 0 },
4636         [GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 },
4637         [GCC_PCIE0_LINK_DOWN_BCR] = { 0x75044, 0 },
4638         [GCC_PCIE1_BCR] = { 0x76004, 0 },
4639         [GCC_PCIE1_PHY_BCR] = { 0x76038, 0 },
4640         [GCC_PCIE1PHY_PHY_BCR] = { 0x7603c, 0 },
4641         [GCC_PCIE1_LINK_DOWN_BCR] = { 0x76044, 0 },
4642         [GCC_DCC_BCR] = { 0x77000, 0 },
4643         [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },
4644         [GCC_APC1_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x79000, 0 },
4645         [GCC_SMMU_CATS_BCR] = { 0x7c000, 0 },
4646         [GCC_UBI0_AXI_ARES] = { 0x68010, 0 },
4647         [GCC_UBI0_AHB_ARES] = { 0x68010, 1 },
4648         [GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 },
4649         [GCC_UBI0_DBG_ARES] = { 0x68010, 3 },
4650         [GCC_UBI0_CORE_CLAMP_ENABLE] = { 0x68010, 4 },
4651         [GCC_UBI0_CLKRST_CLAMP_ENABLE] = { 0x68010, 5 },
4652         [GCC_UBI1_AXI_ARES] = { 0x68010, 8 },
4653         [GCC_UBI1_AHB_ARES] = { 0x68010, 9 },
4654         [GCC_UBI1_NC_AXI_ARES] = { 0x68010, 10 },
4655         [GCC_UBI1_DBG_ARES] = { 0x68010, 11 },
4656         [GCC_UBI1_CORE_CLAMP_ENABLE] = { 0x68010, 12 },
4657         [GCC_UBI1_CLKRST_CLAMP_ENABLE] = { 0x68010, 13 },
4658         [GCC_NSS_CFG_ARES] = { 0x68010, 16 },
4659         [GCC_NSS_IMEM_ARES] = { 0x68010, 17 },
4660         [GCC_NSS_NOC_ARES] = { 0x68010, 18 },
4661         [GCC_NSS_CRYPTO_ARES] = { 0x68010, 19 },
4662         [GCC_NSS_CSR_ARES] = { 0x68010, 20 },
4663         [GCC_NSS_CE_APB_ARES] = { 0x68010, 21 },
4664         [GCC_NSS_CE_AXI_ARES] = { 0x68010, 22 },
4665         [GCC_NSSNOC_CE_APB_ARES] = { 0x68010, 23 },
4666         [GCC_NSSNOC_CE_AXI_ARES] = { 0x68010, 24 },
4667         [GCC_NSSNOC_UBI0_AHB_ARES] = { 0x68010, 25 },
4668         [GCC_NSSNOC_UBI1_AHB_ARES] = { 0x68010, 26 },
4669         [GCC_NSSNOC_SNOC_ARES] = { 0x68010, 27 },
4670         [GCC_NSSNOC_CRYPTO_ARES] = { 0x68010, 28 },
4671         [GCC_NSSNOC_ATB_ARES] = { 0x68010, 29 },
4672         [GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x68010, 30 },
4673         [GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x68010, 31 },
4674         [GCC_PCIE0_PIPE_ARES] = { 0x75040, 0 },
4675         [GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 },
4676         [GCC_PCIE0_CORE_STICKY_ARES] = { 0x75040, 2 },
4677         [GCC_PCIE0_AXI_MASTER_ARES] = { 0x75040, 3 },
4678         [GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },
4679         [GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
4680         [GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
4681         [GCC_PCIE1_PIPE_ARES] = { 0x76040, 0 },
4682         [GCC_PCIE1_SLEEP_ARES] = { 0x76040, 1 },
4683         [GCC_PCIE1_CORE_STICKY_ARES] = { 0x76040, 2 },
4684         [GCC_PCIE1_AXI_MASTER_ARES] = { 0x76040, 3 },
4685         [GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 },
4686         [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
4687         [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
4688 };
4689
4690 static const struct of_device_id gcc_ipq8074_match_table[] = {
4691         { .compatible = "qcom,gcc-ipq8074" },
4692         { }
4693 };
4694 MODULE_DEVICE_TABLE(of, gcc_ipq8074_match_table);
4695
4696 static const struct regmap_config gcc_ipq8074_regmap_config = {
4697         .reg_bits       = 32,
4698         .reg_stride     = 4,
4699         .val_bits       = 32,
4700         .max_register   = 0x7fffc,
4701         .fast_io        = true,
4702 };
4703
4704 static const struct qcom_cc_desc gcc_ipq8074_desc = {
4705         .config = &gcc_ipq8074_regmap_config,
4706         .clks = gcc_ipq8074_clks,
4707         .num_clks = ARRAY_SIZE(gcc_ipq8074_clks),
4708         .resets = gcc_ipq8074_resets,
4709         .num_resets = ARRAY_SIZE(gcc_ipq8074_resets),
4710         .clk_hws = gcc_ipq8074_hws,
4711         .num_clk_hws = ARRAY_SIZE(gcc_ipq8074_hws),
4712 };
4713
4714 static int gcc_ipq8074_probe(struct platform_device *pdev)
4715 {
4716         return qcom_cc_probe(pdev, &gcc_ipq8074_desc);
4717 }
4718
4719 static struct platform_driver gcc_ipq8074_driver = {
4720         .probe = gcc_ipq8074_probe,
4721         .driver = {
4722                 .name   = "qcom,gcc-ipq8074",
4723                 .of_match_table = gcc_ipq8074_match_table,
4724         },
4725 };
4726
4727 static int __init gcc_ipq8074_init(void)
4728 {
4729         return platform_driver_register(&gcc_ipq8074_driver);
4730 }
4731 core_initcall(gcc_ipq8074_init);
4732
4733 static void __exit gcc_ipq8074_exit(void)
4734 {
4735         platform_driver_unregister(&gcc_ipq8074_driver);
4736 }
4737 module_exit(gcc_ipq8074_exit);
4738
4739 MODULE_DESCRIPTION("QCOM GCC IPQ8074 Driver");
4740 MODULE_LICENSE("GPL v2");
4741 MODULE_ALIAS("platform:gcc-ipq8074");