1 // SPDX-License-Identifier: GPL-2.0+
3 * Actions Semi S900 clock driver
5 * Copyright (C) 2015 Actions Semi Co., Ltd.
6 * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11 #include <asm/arch-owl/clk_s900.h>
12 #include <asm/arch-owl/regs_s900.h>
15 #include <dt-bindings/clock/s900_cmu.h>
17 void owl_clk_init(struct owl_clk_priv *priv)
19 u32 bus_clk = 0, core_pll, dev_pll;
21 /* Enable ASSIST_PLL */
22 setbits_le32(priv->base + CMU_ASSISTPLL, BIT(0));
24 udelay(PLL_STABILITY_WAIT_US);
26 /* Source HOSC to DEV_CLK */
27 clrbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
29 /* Configure BUS_CLK */
30 bus_clk |= (CMU_PDBGDIV_DIV | CMU_PERDIV_DIV | CMU_NOCDIV_DIV |
31 CMU_DMMCLK_SRC | CMU_APBCLK_DIV | CMU_AHBCLK_DIV |
32 CMU_NOCCLK_SRC | CMU_CORECLK_HOSC);
33 writel(bus_clk, priv->base + CMU_BUSCLK);
35 udelay(PLL_STABILITY_WAIT_US);
37 /* Configure CORE_PLL */
38 core_pll = readl(priv->base + CMU_COREPLL);
39 core_pll |= (CMU_COREPLL_EN | CMU_COREPLL_HOSC_EN | CMU_COREPLL_OUT);
40 writel(core_pll, priv->base + CMU_COREPLL);
42 udelay(PLL_STABILITY_WAIT_US);
44 /* Configure DEV_PLL */
45 dev_pll = readl(priv->base + CMU_DEVPLL);
46 dev_pll |= (CMU_DEVPLL_EN | CMU_DEVPLL_OUT);
47 writel(dev_pll, priv->base + CMU_DEVPLL);
49 udelay(PLL_STABILITY_WAIT_US);
51 /* Source CORE_PLL for CORE_CLK */
52 clrsetbits_le32(priv->base + CMU_BUSCLK, CMU_CORECLK_MASK,
55 /* Source DEV_PLL for DEV_CLK */
56 setbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
58 udelay(PLL_STABILITY_WAIT_US);
61 void owl_uart_clk_enable(struct owl_clk_priv *priv)
63 /* Source HOSC for UART5 interface */
64 clrbits_le32(priv->base + CMU_UART5CLK, CMU_UARTCLK_SRC_DEVPLL);
66 /* Enable UART5 interface clock */
67 setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);
70 void owl_uart_clk_disable(struct owl_clk_priv *priv)
72 /* Disable UART5 interface clock */
73 clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);
76 int owl_clk_enable(struct clk *clk)
78 struct owl_clk_priv *priv = dev_get_priv(clk->dev);
82 owl_uart_clk_enable(priv);
91 int owl_clk_disable(struct clk *clk)
93 struct owl_clk_priv *priv = dev_get_priv(clk->dev);
97 owl_uart_clk_disable(priv);
106 static int owl_clk_probe(struct udevice *dev)
108 struct owl_clk_priv *priv = dev_get_priv(dev);
110 priv->base = dev_read_addr(dev);
111 if (priv->base == FDT_ADDR_T_NONE)
114 /* setup necessary clocks */
120 static struct clk_ops owl_clk_ops = {
121 .enable = owl_clk_enable,
122 .disable = owl_clk_disable,
125 static const struct udevice_id owl_clk_ids[] = {
126 { .compatible = "actions,s900-cmu" },
130 U_BOOT_DRIVER(clk_owl) = {
133 .of_match = owl_clk_ids,
135 .priv_auto_alloc_size = sizeof(struct owl_clk_priv),
136 .probe = owl_clk_probe,
137 .flags = DM_FLAG_PRE_RELOC,