1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Actions Semi SoCs Clock Definitions
5 * Copyright (C) 2015 Actions Semi Co., Ltd.
6 * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
13 #include <clk-uclass.h>
24 /* BUSCLK register definitions */
25 #define CMU_PDBGDIV_8 7
26 #define CMU_PDBGDIV_SHIFT 26
27 #define CMU_PDBGDIV_DIV (CMU_PDBGDIV_8 << CMU_PDBGDIV_SHIFT)
28 #define CMU_PERDIV_8 7
29 #define CMU_PERDIV_SHIFT 20
30 #define CMU_PERDIV_DIV (CMU_PERDIV_8 << CMU_PERDIV_SHIFT)
31 #define CMU_NOCDIV_2 1
32 #define CMU_NOCDIV_SHIFT 19
33 #define CMU_NOCDIV_DIV (CMU_NOCDIV_2 << CMU_NOCDIV_SHIFT)
34 #define CMU_DMMCLK_SRC_APLL 2
35 #define CMU_DMMCLK_SRC_SHIFT 10
36 #define CMU_DMMCLK_SRC (CMU_DMMCLK_SRC_APLL << CMU_DMMCLK_SRC_SHIFT)
37 #define CMU_APBCLK_DIV BIT(8)
38 #define CMU_NOCCLK_SRC BIT(7)
39 #define CMU_AHBCLK_DIV BIT(4)
40 #define CMU_CORECLK_MASK 3
41 #define CMU_CORECLK_CPLL BIT(1)
42 #define CMU_CORECLK_HOSC BIT(0)
44 /* COREPLL register definitions */
45 #define CMU_COREPLL_EN BIT(9)
46 #define CMU_COREPLL_HOSC_EN BIT(8)
47 #define CMU_COREPLL_OUT (1104 / 24)
49 /* DEVPLL register definitions */
50 #define CMU_DEVPLL_CLK BIT(12)
51 #define CMU_DEVPLL_EN BIT(8)
52 #define CMU_DEVPLL_OUT (660 / 6)
54 /* UARTCLK register definitions */
55 #define CMU_UARTCLK_SRC_DEVPLL BIT(16)
57 #define PLL_STABILITY_WAIT_US 50
59 #define CMU_DEVCLKEN1_UART5 BIT(21)
60 #define CMU_DEVCLKEN1_UART3 BIT(11)
62 #define CMU_DEVCLKEN1_ETH_S700 BIT(23)