1 // SPDX-License-Identifier: GPL-2.0+
3 * Marvell Armada 37xx SoC Peripheral clocks
5 * Marek Behun <marek.behun@nic.cz>
7 * Based on Linux driver by:
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
13 #include <clk-uclass.h>
17 #include <asm/arch/cpu.h>
18 #include <dm/device_compat.h>
27 enum a37xx_periph_parent {
39 enum a37xx_periph_parent parent;
40 } a37xx_periph_parent_names[] = {
41 { "TBG-A-P", TBG_A_P },
42 { "TBG-B-P", TBG_B_P },
43 { "TBG-A-S", TBG_A_S },
44 { "TBG-B-S", TBG_B_S },
50 struct a37xx_periphclk {
53 ulong parents[MAX_PARENTS];
55 const struct clk_periph *clks;
56 bool clk_has_periph_parent[16];
62 struct clk_div_table {
70 const char *parent_name;
75 const struct clk_div_table *div_table[2];
80 unsigned can_gate : 1;
82 unsigned dividers : 2;
85 static const struct clk_div_table div_table1[] = {
91 static const struct clk_div_table div_table2[] = {
97 static const struct clk_div_table div_table6[] = {
107 #define CLK_FULL_DD(_n, _d, _mux, _r0, _r1, _s0, _s1) \
110 .disable_bit = BIT(_d), \
112 .div_table[0] = div_table6, \
113 .div_table[1] = div_table6, \
114 .div_reg_off[0] = _r0, \
115 .div_reg_off[1] = _r1, \
116 .div_shift[0] = _s0, \
117 .div_shift[1] = _s1, \
125 #define CLK_FULL(_n, _d, _mux, _r, _s, _m, _t) \
128 .disable_bit = BIT(_d), \
130 .div_table[0] = _t, \
131 .div_reg_off[0] = _r, \
132 .div_shift[0] = _s, \
139 #define CLK_GATE_DIV(_n, _d, _r, _s, _m, _t, _p) \
143 .disable_bit = BIT(_d), \
144 .div_table[0] = _t, \
145 .div_reg_off[0] = _r, \
146 .div_shift[0] = _s, \
152 #define CLK_GATE(_n, _d, _p) \
156 .disable_bit = BIT(_d), \
160 #define CLK_MUX_DIV(_n, _mux, _r, _s, _m, _t) \
164 .div_table[0] = _t, \
165 .div_reg_off[0] = _r, \
166 .div_shift[0] = _s, \
172 #define CLK_MUX_DD(_n, _mux, _r0, _r1, _s0, _s1) \
176 .div_table[0] = div_table6, \
177 .div_table[1] = div_table6, \
178 .div_reg_off[0] = _r0, \
179 .div_reg_off[1] = _r1, \
180 .div_shift[0] = _s0, \
181 .div_shift[1] = _s1, \
188 /* NB periph clocks */
189 static const struct clk_periph clks_nb[] = {
190 CLK_FULL_DD(mmc, 2, 0, DIV_SEL2, DIV_SEL2, 16, 13),
191 CLK_FULL_DD(sata_host, 3, 2, DIV_SEL2, DIV_SEL2, 10, 7),
192 CLK_FULL_DD(sec_at, 6, 4, DIV_SEL1, DIV_SEL1, 3, 0),
193 CLK_FULL_DD(sec_dap, 7, 6, DIV_SEL1, DIV_SEL1, 9, 6),
194 CLK_FULL_DD(tscem, 8, 8, DIV_SEL1, DIV_SEL1, 15, 12),
195 CLK_FULL(tscem_tmx, 10, 10, DIV_SEL1, 18, 7, div_table6),
196 CLK_GATE(avs, 11, "xtal"),
197 CLK_FULL_DD(sqf, 12, 12, DIV_SEL1, DIV_SEL1, 27, 24),
198 CLK_FULL_DD(pwm, 13, 14, DIV_SEL0, DIV_SEL0, 3, 0),
199 CLK_GATE(i2c_2, 16, "xtal"),
200 CLK_GATE(i2c_1, 17, "xtal"),
201 CLK_GATE_DIV(ddr_phy, 19, DIV_SEL0, 18, 1, div_table2, "TBG-A-S"),
202 CLK_FULL_DD(ddr_fclk, 21, 16, DIV_SEL0, DIV_SEL0, 15, 12),
203 CLK_FULL(trace, 22, 18, DIV_SEL0, 20, 7, div_table6),
204 CLK_FULL(counter, 23, 20, DIV_SEL0, 23, 7, div_table6),
205 CLK_FULL_DD(eip97, 24, 24, DIV_SEL2, DIV_SEL2, 22, 19),
206 CLK_MUX_DIV(cpu, 22, DIV_SEL0, 28, 7, div_table6),
210 /* SB periph clocks */
211 static const struct clk_periph clks_sb[] = {
212 CLK_MUX_DD(gbe_50, 6, DIV_SEL2, DIV_SEL2, 6, 9),
213 CLK_MUX_DD(gbe_core, 8, DIV_SEL1, DIV_SEL1, 18, 21),
214 CLK_MUX_DD(gbe_125, 10, DIV_SEL1, DIV_SEL1, 6, 9),
215 CLK_GATE(gbe1_50, 0, "gbe_50"),
216 CLK_GATE(gbe0_50, 1, "gbe_50"),
217 CLK_GATE(gbe1_125, 2, "gbe_125"),
218 CLK_GATE(gbe0_125, 3, "gbe_125"),
219 CLK_GATE_DIV(gbe1_core, 4, DIV_SEL1, 13, 1, div_table1, "gbe_core"),
220 CLK_GATE_DIV(gbe0_core, 5, DIV_SEL1, 14, 1, div_table1, "gbe_core"),
221 CLK_GATE_DIV(gbe_bm, 12, DIV_SEL1, 0, 1, div_table1, "gbe_core"),
222 CLK_FULL_DD(sdio, 11, 14, DIV_SEL0, DIV_SEL0, 3, 6),
223 CLK_FULL_DD(usb32_usb2_sys, 16, 16, DIV_SEL0, DIV_SEL0, 9, 12),
224 CLK_FULL_DD(usb32_ss_sys, 17, 18, DIV_SEL0, DIV_SEL0, 15, 18),
228 static int get_mux(struct a37xx_periphclk *priv, int shift)
230 return (readl(priv->reg + TBG_SEL) >> shift) & 3;
233 static void set_mux(struct a37xx_periphclk *priv, int shift, int val)
237 reg = readl(priv->reg + TBG_SEL);
238 reg &= ~(3 << shift);
239 reg |= (val & 3) << shift;
240 writel(reg, priv->reg + TBG_SEL);
243 static ulong periph_clk_get_rate(struct a37xx_periphclk *priv, int id);
245 static ulong get_parent_rate(struct a37xx_periphclk *priv, int id)
247 const struct clk_periph *clk = &priv->clks[id];
251 /* parent is one of TBG clocks */
252 int tbg = get_mux(priv, clk->mux_shift);
254 res = priv->parents[tbg];
255 } else if (priv->clk_has_periph_parent[id]) {
256 /* parent is one of other periph clocks */
258 if (priv->clk_parent[id] >= priv->count)
261 res = periph_clk_get_rate(priv, priv->clk_parent[id]);
263 /* otherwise parent is one of TBGs or XTAL */
265 if (priv->clk_parent[id] >= MAX_PARENTS)
268 res = priv->parents[priv->clk_parent[id]];
274 static ulong get_div(struct a37xx_periphclk *priv,
275 const struct clk_periph *clk, int idx)
277 const struct clk_div_table *i;
280 reg = readl(priv->reg + clk->div_reg_off[idx]);
281 reg = (reg >> clk->div_shift[idx]) & clk->div_mask[idx];
283 /* find divisor for register value val */
284 for (i = clk->div_table[idx]; i && i->div != 0; ++i)
291 static void set_div_val(struct a37xx_periphclk *priv,
292 const struct clk_periph *clk, int idx, int val)
296 reg = readl(priv->reg + clk->div_reg_off[idx]);
297 reg &= ~(clk->div_mask[idx] << clk->div_shift[idx]);
298 reg |= (val & clk->div_mask[idx]) << clk->div_shift[idx];
299 writel(reg, priv->reg + clk->div_reg_off[idx]);
302 static ulong periph_clk_get_rate(struct a37xx_periphclk *priv, int id)
304 const struct clk_periph *clk = &priv->clks[id];
308 rate = get_parent_rate(priv, id);
312 /* divide the parent rate by dividers */
314 for (i = 0; i < clk->dividers; ++i)
315 div *= get_div(priv, clk, i);
320 return DIV_ROUND_UP(rate, div);
323 static ulong armada_37xx_periph_clk_get_rate(struct clk *clk)
325 struct a37xx_periphclk *priv = dev_get_priv(clk->dev);
327 if (clk->id >= priv->count)
330 return periph_clk_get_rate(priv, clk->id);
333 static int periph_clk_enable(struct clk *clk, int enable)
335 struct a37xx_periphclk *priv = dev_get_priv(clk->dev);
336 const struct clk_periph *periph_clk = &priv->clks[clk->id];
338 if (clk->id >= priv->count)
341 if (!periph_clk->can_gate)
345 clrbits_le32(priv->reg + CLK_DIS, periph_clk->disable_bit);
347 setbits_le32(priv->reg + CLK_DIS, periph_clk->disable_bit);
352 static int armada_37xx_periph_clk_enable(struct clk *clk)
354 return periph_clk_enable(clk, 1);
357 static int armada_37xx_periph_clk_disable(struct clk *clk)
359 return periph_clk_enable(clk, 0);
362 #define diff(a, b) abs((long)(a) - (long)(b))
364 static ulong find_best_div(const struct clk_div_table *t0,
365 const struct clk_div_table *t1, ulong parent_rate,
366 ulong req_rate, int *v0, int *v1)
368 const struct clk_div_table *i, *j;
369 ulong rate, best_rate = 0;
371 for (i = t0; i && i->div; ++i) {
372 for (j = t1; j && j->div; ++j) {
373 rate = DIV_ROUND_UP(parent_rate, i->div * j->div);
376 diff(rate, req_rate) < diff(best_rate, req_rate)) {
387 static ulong armada_37xx_periph_clk_set_rate(struct clk *clk, ulong req_rate)
389 struct a37xx_periphclk *priv = dev_get_priv(clk->dev);
390 const struct clk_periph *periph_clk = &priv->clks[clk->id];
391 ulong rate, old_rate, parent_rate;
392 int div_val0 = 0, div_val1 = 0;
393 const struct clk_div_table *t1;
394 static const struct clk_div_table empty_table[2] = {
399 if (clk->id > priv->count)
402 old_rate = periph_clk_get_rate(priv, clk->id);
403 if (old_rate == -EINVAL)
406 if (old_rate == req_rate)
409 if (!periph_clk->can_gate || !periph_clk->dividers)
412 parent_rate = get_parent_rate(priv, clk->id);
413 if (parent_rate == -EINVAL)
417 if (periph_clk->dividers > 1)
418 t1 = periph_clk->div_table[1];
420 rate = find_best_div(periph_clk->div_table[0], t1, parent_rate,
421 req_rate, &div_val0, &div_val1);
423 periph_clk_enable(clk, 0);
425 set_div_val(priv, periph_clk, 0, div_val0);
426 if (periph_clk->dividers > 1)
427 set_div_val(priv, periph_clk, 1, div_val1);
429 periph_clk_enable(clk, 1);
434 static int armada_37xx_periph_clk_set_parent(struct clk *clk,
437 struct a37xx_periphclk *priv = dev_get_priv(clk->dev);
438 const struct clk_periph *periph_clk = &priv->clks[clk->id];
439 struct clk check_parent;
442 /* We also check if parent is our TBG clock */
443 if (clk->id > priv->count || parent->id >= MAX_TBG_PARENTS)
446 if (!periph_clk->can_mux || !periph_clk->can_gate)
449 ret = clk_get_by_index(clk->dev, 0, &check_parent);
453 if (parent->dev != check_parent.dev)
456 clk_free(&check_parent);
460 periph_clk_enable(clk, 0);
461 set_mux(priv, periph_clk->mux_shift, parent->id);
462 periph_clk_enable(clk, 1);
467 #if defined(CONFIG_CMD_CLK) && defined(CONFIG_CLK_ARMADA_3720)
468 static int armada_37xx_periph_clk_dump(struct udevice *dev)
470 struct a37xx_periphclk *priv = dev_get_priv(dev);
471 const struct clk_periph *clks;
479 for (i = 0; i < priv->count; ++i)
480 printf(" %s at %lu Hz\n", clks[i].name,
481 periph_clk_get_rate(priv, i));
487 static int clk_dump(const char *name, int (*func)(struct udevice *))
491 if (uclass_get_device_by_name(UCLASS_CLK, name, &dev)) {
492 printf("Cannot find device %s\n", name);
499 int armada_37xx_tbg_clk_dump(struct udevice *);
501 int soc_clk_dump(void)
503 printf(" xtal at %u000000 Hz\n\n", get_ref_clk());
505 if (clk_dump("tbg@13200", armada_37xx_tbg_clk_dump))
508 if (clk_dump("nb-periph-clk@13000",
509 armada_37xx_periph_clk_dump))
512 if (clk_dump("sb-periph-clk@18000",
513 armada_37xx_periph_clk_dump))
520 static int armada_37xx_periph_clk_probe(struct udevice *dev)
522 struct a37xx_periphclk *priv = dev_get_priv(dev);
523 const struct clk_periph *clks;
526 clks = (const struct clk_periph *)dev_get_driver_data(dev);
530 priv->reg = dev_read_addr_ptr(dev);
532 dev_err(dev, "no io address\n");
536 /* count clk_periph nodes */
538 while (clks[priv->count].name)
543 /* assign parent IDs to nodes which have non-NULL parent_name */
544 for (i = 0; i < priv->count; ++i) {
547 if (!clks[i].parent_name)
550 /* first try if parent_name is one of TBGs or XTAL */
551 for (j = 0; j < MAX_PARENTS; ++j)
552 if (!strcmp(clks[i].parent_name,
553 a37xx_periph_parent_names[j].name))
556 if (j < MAX_PARENTS) {
557 priv->clk_has_periph_parent[i] = false;
558 priv->clk_parent[i] =
559 a37xx_periph_parent_names[j].parent;
563 /* else parent_name should be one of other periph clocks */
564 for (j = 0; j < priv->count; ++j) {
565 if (!strcmp(clks[i].parent_name, clks[j].name))
569 if (j < priv->count) {
570 priv->clk_has_periph_parent[i] = true;
571 priv->clk_parent[i] = j;
575 dev_err(dev, "undefined parent %s\n", clks[i].parent_name);
579 for (i = 0; i < MAX_PARENTS; ++i) {
583 priv->parents[i] = get_ref_clk() * 1000000;
587 ret = clk_get_by_index(dev, i, &clk);
589 dev_err(dev, "one of parent clocks (%i) missing: %i\n",
594 priv->parents[i] = clk_get_rate(&clk);
601 static const struct clk_ops armada_37xx_periph_clk_ops = {
602 .get_rate = armada_37xx_periph_clk_get_rate,
603 .set_rate = armada_37xx_periph_clk_set_rate,
604 .set_parent = armada_37xx_periph_clk_set_parent,
605 .enable = armada_37xx_periph_clk_enable,
606 .disable = armada_37xx_periph_clk_disable,
609 static const struct udevice_id armada_37xx_periph_clk_ids[] = {
611 .compatible = "marvell,armada-3700-periph-clock-nb",
612 .data = (ulong)clks_nb,
615 .compatible = "marvell,armada-3700-periph-clock-sb",
616 .data = (ulong)clks_sb,
621 U_BOOT_DRIVER(armada_37xx_periph_clk) = {
622 .name = "armada_37xx_periph_clk",
624 .of_match = armada_37xx_periph_clk_ids,
625 .ops = &armada_37xx_periph_clk_ops,
626 .priv_auto_alloc_size = sizeof(struct a37xx_periphclk),
627 .probe = armada_37xx_periph_clk_probe,