1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com>
4 * (C) Copyright 2018 - BayLibre, SAS
5 * Author: Neil Armstrong <narmstrong@baylibre.com>
9 #include <asm/arch/clock-gx.h>
11 #include <clk-uclass.h>
16 #include <dt-bindings/clock/gxbb-clkc.h>
17 #include "clk_meson.h"
18 #include <linux/err.h>
20 /* This driver support only basic clock tree operations :
21 * - Can calculate clock frequency on a limited tree
22 * - Can Read muxes and basic dividers (0-based only)
23 * - Can enable/disable gates with limited propagation
24 * - Can reparent without propagation, only on muxes
25 * - Can set rates without reparenting
26 * This driver is adapted to what is actually supported by U-Boot
29 /* Only the clocks ids we don't want to expose, such as the internal muxes
30 * and dividers of composite clocks, will remain defined here.
32 #define CLKID_MPEG_SEL 10
33 #define CLKID_MPEG_DIV 11
34 #define CLKID_SAR_ADC_DIV 99
35 #define CLKID_MALI_0_DIV 101
36 #define CLKID_MALI_1_DIV 104
37 #define CLKID_CTS_AMCLK_SEL 108
38 #define CLKID_CTS_AMCLK_DIV 109
39 #define CLKID_CTS_MCLK_I958_SEL 111
40 #define CLKID_CTS_MCLK_I958_DIV 112
41 #define CLKID_32K_CLK_SEL 115
42 #define CLKID_32K_CLK_DIV 116
43 #define CLKID_SD_EMMC_A_CLK0_SEL 117
44 #define CLKID_SD_EMMC_A_CLK0_DIV 118
45 #define CLKID_SD_EMMC_B_CLK0_SEL 120
46 #define CLKID_SD_EMMC_B_CLK0_DIV 121
47 #define CLKID_SD_EMMC_C_CLK0_SEL 123
48 #define CLKID_SD_EMMC_C_CLK0_DIV 124
49 #define CLKID_VPU_0_DIV 127
50 #define CLKID_VPU_1_DIV 130
51 #define CLKID_VAPB_0_DIV 134
52 #define CLKID_VAPB_1_DIV 137
53 #define CLKID_HDMI_PLL_PRE_MULT 141
54 #define CLKID_MPLL0_DIV 142
55 #define CLKID_MPLL1_DIV 143
56 #define CLKID_MPLL2_DIV 144
57 #define CLKID_MPLL_PREDIV 145
58 #define CLKID_FCLK_DIV2_DIV 146
59 #define CLKID_FCLK_DIV3_DIV 147
60 #define CLKID_FCLK_DIV4_DIV 148
61 #define CLKID_FCLK_DIV5_DIV 149
62 #define CLKID_FCLK_DIV7_DIV 150
63 #define CLKID_VDEC_1_SEL 151
64 #define CLKID_VDEC_1_DIV 152
65 #define CLKID_VDEC_HEVC_SEL 154
66 #define CLKID_VDEC_HEVC_DIV 155
68 #define XTAL_RATE 24000000
74 static ulong meson_div_get_rate(struct clk *clk, unsigned long id);
75 static ulong meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate,
77 static ulong meson_mux_set_parent(struct clk *clk, unsigned long id,
78 unsigned long parent_id);
79 static ulong meson_mux_get_rate(struct clk *clk, unsigned long id);
80 static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned long id,
81 ulong rate, ulong current_rate);
82 static ulong meson_mux_get_parent(struct clk *clk, unsigned long id);
83 static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id);
85 static struct meson_gate gates[] = {
86 /* Everything Else (EE) domain gates */
87 MESON_GATE(CLKID_DDR, HHI_GCLK_MPEG0, 0),
88 MESON_GATE(CLKID_DOS, HHI_GCLK_MPEG0, 1),
89 MESON_GATE(CLKID_ISA, HHI_GCLK_MPEG0, 5),
90 MESON_GATE(CLKID_PL301, HHI_GCLK_MPEG0, 6),
91 MESON_GATE(CLKID_PERIPHS, HHI_GCLK_MPEG0, 7),
92 MESON_GATE(CLKID_SPICC, HHI_GCLK_MPEG0, 8),
93 MESON_GATE(CLKID_I2C, HHI_GCLK_MPEG0, 9),
94 MESON_GATE(CLKID_SAR_ADC, HHI_GCLK_MPEG0, 10),
95 MESON_GATE(CLKID_SMART_CARD, HHI_GCLK_MPEG0, 11),
96 MESON_GATE(CLKID_RNG0, HHI_GCLK_MPEG0, 12),
97 MESON_GATE(CLKID_UART0, HHI_GCLK_MPEG0, 13),
98 MESON_GATE(CLKID_SDHC, HHI_GCLK_MPEG0, 14),
99 MESON_GATE(CLKID_STREAM, HHI_GCLK_MPEG0, 15),
100 MESON_GATE(CLKID_ASYNC_FIFO, HHI_GCLK_MPEG0, 16),
101 MESON_GATE(CLKID_SDIO, HHI_GCLK_MPEG0, 17),
102 MESON_GATE(CLKID_ABUF, HHI_GCLK_MPEG0, 18),
103 MESON_GATE(CLKID_HIU_IFACE, HHI_GCLK_MPEG0, 19),
104 MESON_GATE(CLKID_ASSIST_MISC, HHI_GCLK_MPEG0, 23),
105 MESON_GATE(CLKID_SD_EMMC_A, HHI_GCLK_MPEG0, 24),
106 MESON_GATE(CLKID_SD_EMMC_B, HHI_GCLK_MPEG0, 25),
107 MESON_GATE(CLKID_SD_EMMC_C, HHI_GCLK_MPEG0, 26),
108 MESON_GATE(CLKID_SPI, HHI_GCLK_MPEG0, 30),
110 MESON_GATE(CLKID_I2S_SPDIF, HHI_GCLK_MPEG1, 2),
111 MESON_GATE(CLKID_ETH, HHI_GCLK_MPEG1, 3),
112 MESON_GATE(CLKID_DEMUX, HHI_GCLK_MPEG1, 4),
113 MESON_GATE(CLKID_AIU_GLUE, HHI_GCLK_MPEG1, 6),
114 MESON_GATE(CLKID_IEC958, HHI_GCLK_MPEG1, 7),
115 MESON_GATE(CLKID_I2S_OUT, HHI_GCLK_MPEG1, 8),
116 MESON_GATE(CLKID_AMCLK, HHI_GCLK_MPEG1, 9),
117 MESON_GATE(CLKID_AIFIFO2, HHI_GCLK_MPEG1, 10),
118 MESON_GATE(CLKID_MIXER, HHI_GCLK_MPEG1, 11),
119 MESON_GATE(CLKID_MIXER_IFACE, HHI_GCLK_MPEG1, 12),
120 MESON_GATE(CLKID_ADC, HHI_GCLK_MPEG1, 13),
121 MESON_GATE(CLKID_BLKMV, HHI_GCLK_MPEG1, 14),
122 MESON_GATE(CLKID_AIU, HHI_GCLK_MPEG1, 15),
123 MESON_GATE(CLKID_UART1, HHI_GCLK_MPEG1, 16),
124 MESON_GATE(CLKID_G2D, HHI_GCLK_MPEG1, 20),
125 MESON_GATE(CLKID_USB0, HHI_GCLK_MPEG1, 21),
126 MESON_GATE(CLKID_USB1, HHI_GCLK_MPEG1, 22),
127 MESON_GATE(CLKID_RESET, HHI_GCLK_MPEG1, 23),
128 MESON_GATE(CLKID_NAND, HHI_GCLK_MPEG1, 24),
129 MESON_GATE(CLKID_DOS_PARSER, HHI_GCLK_MPEG1, 25),
130 MESON_GATE(CLKID_USB, HHI_GCLK_MPEG1, 26),
131 MESON_GATE(CLKID_VDIN1, HHI_GCLK_MPEG1, 28),
132 MESON_GATE(CLKID_AHB_ARB0, HHI_GCLK_MPEG1, 29),
133 MESON_GATE(CLKID_EFUSE, HHI_GCLK_MPEG1, 30),
134 MESON_GATE(CLKID_BOOT_ROM, HHI_GCLK_MPEG1, 31),
136 MESON_GATE(CLKID_AHB_DATA_BUS, HHI_GCLK_MPEG2, 1),
137 MESON_GATE(CLKID_AHB_CTRL_BUS, HHI_GCLK_MPEG2, 2),
138 MESON_GATE(CLKID_HDMI_INTR_SYNC, HHI_GCLK_MPEG2, 3),
139 MESON_GATE(CLKID_HDMI_PCLK, HHI_GCLK_MPEG2, 4),
140 MESON_GATE(CLKID_USB1_DDR_BRIDGE, HHI_GCLK_MPEG2, 8),
141 MESON_GATE(CLKID_USB0_DDR_BRIDGE, HHI_GCLK_MPEG2, 9),
142 MESON_GATE(CLKID_MMC_PCLK, HHI_GCLK_MPEG2, 11),
143 MESON_GATE(CLKID_DVIN, HHI_GCLK_MPEG2, 12),
144 MESON_GATE(CLKID_UART2, HHI_GCLK_MPEG2, 15),
145 MESON_GATE(CLKID_SANA, HHI_GCLK_MPEG2, 22),
146 MESON_GATE(CLKID_VPU_INTR, HHI_GCLK_MPEG2, 25),
147 MESON_GATE(CLKID_SEC_AHB_AHB3_BRIDGE, HHI_GCLK_MPEG2, 26),
148 MESON_GATE(CLKID_CLK81_A53, HHI_GCLK_MPEG2, 29),
150 MESON_GATE(CLKID_VCLK2_VENCI0, HHI_GCLK_OTHER, 1),
151 MESON_GATE(CLKID_VCLK2_VENCI1, HHI_GCLK_OTHER, 2),
152 MESON_GATE(CLKID_VCLK2_VENCP0, HHI_GCLK_OTHER, 3),
153 MESON_GATE(CLKID_VCLK2_VENCP1, HHI_GCLK_OTHER, 4),
154 MESON_GATE(CLKID_GCLK_VENCI_INT0, HHI_GCLK_OTHER, 8),
155 MESON_GATE(CLKID_DAC_CLK, HHI_GCLK_OTHER, 10),
156 MESON_GATE(CLKID_AOCLK_GATE, HHI_GCLK_OTHER, 14),
157 MESON_GATE(CLKID_IEC958_GATE, HHI_GCLK_OTHER, 16),
158 MESON_GATE(CLKID_ENC480P, HHI_GCLK_OTHER, 20),
159 MESON_GATE(CLKID_RNG1, HHI_GCLK_OTHER, 21),
160 MESON_GATE(CLKID_GCLK_VENCI_INT1, HHI_GCLK_OTHER, 22),
161 MESON_GATE(CLKID_VCLK2_VENCLMCC, HHI_GCLK_OTHER, 24),
162 MESON_GATE(CLKID_VCLK2_VENCL, HHI_GCLK_OTHER, 25),
163 MESON_GATE(CLKID_VCLK_OTHER, HHI_GCLK_OTHER, 26),
164 MESON_GATE(CLKID_EDP, HHI_GCLK_OTHER, 31),
166 /* Always On (AO) domain gates */
167 MESON_GATE(CLKID_AO_MEDIA_CPU, HHI_GCLK_AO, 0),
168 MESON_GATE(CLKID_AO_AHB_SRAM, HHI_GCLK_AO, 1),
169 MESON_GATE(CLKID_AO_AHB_BUS, HHI_GCLK_AO, 2),
170 MESON_GATE(CLKID_AO_IFACE, HHI_GCLK_AO, 3),
171 MESON_GATE(CLKID_AO_I2C, HHI_GCLK_AO, 4),
174 /* CLKID_FCLK_DIV2 is critical for the SCPI Processor */
175 MESON_GATE(CLKID_FCLK_DIV3, HHI_MPLL_CNTL6, 28),
176 MESON_GATE(CLKID_FCLK_DIV4, HHI_MPLL_CNTL6, 29),
177 MESON_GATE(CLKID_FCLK_DIV5, HHI_MPLL_CNTL6, 30),
178 MESON_GATE(CLKID_FCLK_DIV7, HHI_MPLL_CNTL6, 31),
179 MESON_GATE(CLKID_MPLL0, HHI_MPLL_CNTL7, 14),
180 MESON_GATE(CLKID_MPLL1, HHI_MPLL_CNTL8, 14),
181 MESON_GATE(CLKID_MPLL2, HHI_MPLL_CNTL9, 14),
182 /* CLKID_CLK81 is critical for the system */
184 /* Peripheral Gates */
185 MESON_GATE(CLKID_SAR_ADC_CLK, HHI_SAR_CLK_CNTL, 8),
186 MESON_GATE(CLKID_SD_EMMC_A_CLK0, HHI_SD_EMMC_CLK_CNTL, 7),
187 MESON_GATE(CLKID_SD_EMMC_B_CLK0, HHI_SD_EMMC_CLK_CNTL, 23),
188 MESON_GATE(CLKID_SD_EMMC_C_CLK0, HHI_NAND_CLK_CNTL, 7),
189 MESON_GATE(CLKID_VPU_0, HHI_VPU_CLK_CNTL, 8),
190 MESON_GATE(CLKID_VPU_1, HHI_VPU_CLK_CNTL, 24),
191 MESON_GATE(CLKID_VAPB_0, HHI_VAPBCLK_CNTL, 8),
192 MESON_GATE(CLKID_VAPB_1, HHI_VAPBCLK_CNTL, 24),
193 MESON_GATE(CLKID_VAPB, HHI_VAPBCLK_CNTL, 30),
196 static int meson_set_gate_by_id(struct clk *clk, unsigned long id, bool on)
198 struct meson_clk *priv = dev_get_priv(clk->dev);
199 struct meson_gate *gate;
201 debug("%s: %sabling %ld\n", __func__, on ? "en" : "dis", id);
203 /* Propagate through muxes */
206 return meson_set_gate_by_id(clk,
207 meson_mux_get_parent(clk, CLKID_VPU), on);
209 return meson_set_gate_by_id(clk,
210 meson_mux_get_parent(clk, CLKID_VAPB_SEL), on);
213 if (id >= ARRAY_SIZE(gates))
221 debug("%s: really %sabling %ld\n", __func__, on ? "en" : "dis", id);
223 regmap_update_bits(priv->map, gate->reg,
224 BIT(gate->bit), on ? BIT(gate->bit) : 0);
226 /* Propagate to next gate(s) */
229 return meson_set_gate_by_id(clk, CLKID_VAPB_SEL, on);
235 static int meson_clk_enable(struct clk *clk)
237 return meson_set_gate_by_id(clk, clk->id, true);
240 static int meson_clk_disable(struct clk *clk)
242 return meson_set_gate_by_id(clk, clk->id, false);
245 static struct parm meson_vpu_0_div_parm = {
246 HHI_VPU_CLK_CNTL, 0, 7,
249 int meson_vpu_0_div_parent = CLKID_VPU_0_SEL;
251 static struct parm meson_vpu_1_div_parm = {
252 HHI_VPU_CLK_CNTL, 16, 7,
255 int meson_vpu_1_div_parent = CLKID_VPU_1_SEL;
257 static struct parm meson_vapb_0_div_parm = {
258 HHI_VAPBCLK_CNTL, 0, 7,
261 int meson_vapb_0_div_parent = CLKID_VAPB_0_SEL;
263 static struct parm meson_vapb_1_div_parm = {
264 HHI_VAPBCLK_CNTL, 16, 7,
267 int meson_vapb_1_div_parent = CLKID_VAPB_1_SEL;
269 static ulong meson_div_get_rate(struct clk *clk, unsigned long id)
271 struct meson_clk *priv = dev_get_priv(clk->dev);
272 unsigned int rate, parent_rate;
278 case CLKID_VPU_0_DIV:
279 parm = &meson_vpu_0_div_parm;
280 parent = meson_vpu_0_div_parent;
282 case CLKID_VPU_1_DIV:
283 parm = &meson_vpu_1_div_parm;
284 parent = meson_vpu_1_div_parent;
286 case CLKID_VAPB_0_DIV:
287 parm = &meson_vapb_0_div_parm;
288 parent = meson_vapb_0_div_parent;
290 case CLKID_VAPB_1_DIV:
291 parm = &meson_vapb_1_div_parm;
292 parent = meson_vapb_1_div_parent;
298 regmap_read(priv->map, parm->reg_off, ®);
299 reg = PARM_GET(parm->width, parm->shift, reg);
301 debug("%s: div of %ld is %d\n", __func__, id, reg + 1);
303 parent_rate = meson_clk_get_rate_by_id(clk, parent);
304 if (IS_ERR_VALUE(parent_rate))
307 debug("%s: parent rate of %ld is %d\n", __func__, id, parent_rate);
309 rate = parent_rate / (reg + 1);
311 debug("%s: rate of %ld is %d\n", __func__, id, rate);
316 static ulong meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate,
319 struct meson_clk *priv = dev_get_priv(clk->dev);
320 unsigned int new_div = -EINVAL;
321 unsigned long parent_rate;
326 if (current_rate == rate)
329 debug("%s: setting rate of %ld from %ld to %ld\n",
330 __func__, id, current_rate, rate);
333 case CLKID_VPU_0_DIV:
334 parm = &meson_vpu_0_div_parm;
335 parent = meson_vpu_0_div_parent;
337 case CLKID_VPU_1_DIV:
338 parm = &meson_vpu_1_div_parm;
339 parent = meson_vpu_1_div_parent;
341 case CLKID_VAPB_0_DIV:
342 parm = &meson_vapb_0_div_parm;
343 parent = meson_vapb_0_div_parent;
345 case CLKID_VAPB_1_DIV:
346 parm = &meson_vapb_1_div_parm;
347 parent = meson_vapb_1_div_parent;
353 parent_rate = meson_clk_get_rate_by_id(clk, parent);
354 if (IS_ERR_VALUE(parent_rate))
357 debug("%s: parent rate of %ld is %ld\n", __func__, id, parent_rate);
359 /* If can't divide, set parent instead */
360 if (!parent_rate || rate > parent_rate)
361 return meson_clk_set_rate_by_id(clk, parent, rate,
364 new_div = DIV_ROUND_CLOSEST(parent_rate, rate);
366 debug("%s: new div of %ld is %d\n", __func__, id, new_div);
368 /* If overflow, try to set parent rate and retry */
369 if (!new_div || new_div > (1 << parm->width)) {
370 ret = meson_clk_set_rate_by_id(clk, parent, rate, current_rate);
371 if (IS_ERR_VALUE(ret))
374 parent_rate = meson_clk_get_rate_by_id(clk, parent);
375 if (IS_ERR_VALUE(parent_rate))
378 new_div = DIV_ROUND_CLOSEST(parent_rate, rate);
380 debug("%s: new new div of %ld is %d\n", __func__, id, new_div);
382 if (!new_div || new_div > (1 << parm->width))
386 debug("%s: setting div of %ld to %d\n", __func__, id, new_div);
388 regmap_update_bits(priv->map, parm->reg_off, SETPMASK(parm->width, parm->shift),
389 (new_div - 1) << parm->shift);
391 debug("%s: new rate of %ld is %ld\n",
392 __func__, id, meson_div_get_rate(clk, id));
397 static struct parm meson_vpu_mux_parm = {
398 HHI_VPU_CLK_CNTL, 31, 1,
401 int meson_vpu_mux_parents[] = {
406 static struct parm meson_vpu_0_mux_parm = {
407 HHI_VPU_CLK_CNTL, 9, 2,
410 static struct parm meson_vpu_1_mux_parm = {
411 HHI_VPU_CLK_CNTL, 25, 2,
414 static int meson_vpu_0_1_mux_parents[] = {
421 static struct parm meson_vapb_sel_mux_parm = {
422 HHI_VAPBCLK_CNTL, 31, 1,
425 int meson_vapb_sel_mux_parents[] = {
430 static struct parm meson_vapb_0_mux_parm = {
431 HHI_VAPBCLK_CNTL, 9, 2,
434 static struct parm meson_vapb_1_mux_parm = {
435 HHI_VAPBCLK_CNTL, 25, 2,
438 static int meson_vapb_0_1_mux_parents[] = {
445 static ulong meson_mux_get_parent(struct clk *clk, unsigned long id)
447 struct meson_clk *priv = dev_get_priv(clk->dev);
454 parm = &meson_vpu_mux_parm;
455 parents = meson_vpu_mux_parents;
457 case CLKID_VPU_0_SEL:
458 parm = &meson_vpu_0_mux_parm;
459 parents = meson_vpu_0_1_mux_parents;
461 case CLKID_VPU_1_SEL:
462 parm = &meson_vpu_1_mux_parm;
463 parents = meson_vpu_0_1_mux_parents;
466 parm = &meson_vapb_sel_mux_parm;
467 parents = meson_vapb_sel_mux_parents;
469 case CLKID_VAPB_0_SEL:
470 parm = &meson_vapb_0_mux_parm;
471 parents = meson_vapb_0_1_mux_parents;
473 case CLKID_VAPB_1_SEL:
474 parm = &meson_vapb_1_mux_parm;
475 parents = meson_vapb_0_1_mux_parents;
481 regmap_read(priv->map, parm->reg_off, ®);
482 reg = PARM_GET(parm->width, parm->shift, reg);
484 debug("%s: parent of %ld is %d (%d)\n",
485 __func__, id, parents[reg], reg);
490 static ulong meson_mux_set_parent(struct clk *clk, unsigned long id,
491 unsigned long parent_id)
493 unsigned long cur_parent = meson_mux_get_parent(clk, id);
494 struct meson_clk *priv = dev_get_priv(clk->dev);
495 unsigned int new_index = -EINVAL;
500 if (IS_ERR_VALUE(cur_parent))
503 debug("%s: setting parent of %ld from %ld to %ld\n",
504 __func__, id, cur_parent, parent_id);
506 if (cur_parent == parent_id)
511 parm = &meson_vpu_mux_parm;
512 parents = meson_vpu_mux_parents;
514 case CLKID_VPU_0_SEL:
515 parm = &meson_vpu_0_mux_parm;
516 parents = meson_vpu_0_1_mux_parents;
518 case CLKID_VPU_1_SEL:
519 parm = &meson_vpu_1_mux_parm;
520 parents = meson_vpu_0_1_mux_parents;
523 parm = &meson_vapb_sel_mux_parm;
524 parents = meson_vapb_sel_mux_parents;
526 case CLKID_VAPB_0_SEL:
527 parm = &meson_vapb_0_mux_parm;
528 parents = meson_vapb_0_1_mux_parents;
530 case CLKID_VAPB_1_SEL:
531 parm = &meson_vapb_1_mux_parm;
532 parents = meson_vapb_0_1_mux_parents;
539 for (i = 0 ; i < (1 << parm->width) ; ++i) {
540 if (parents[i] == parent_id)
544 if (IS_ERR_VALUE(new_index))
547 debug("%s: new index of %ld is %d\n", __func__, id, new_index);
549 regmap_update_bits(priv->map, parm->reg_off, SETPMASK(parm->width, parm->shift),
550 new_index << parm->shift);
552 debug("%s: new parent of %ld is %ld\n",
553 __func__, id, meson_mux_get_parent(clk, id));
558 static ulong meson_mux_get_rate(struct clk *clk, unsigned long id)
560 int parent = meson_mux_get_parent(clk, id);
562 if (IS_ERR_VALUE(parent))
565 return meson_clk_get_rate_by_id(clk, parent);
568 static unsigned long meson_clk81_get_rate(struct clk *clk)
570 struct meson_clk *priv = dev_get_priv(clk->dev);
571 unsigned long parent_rate;
585 regmap_read(priv->map, HHI_MPEG_CLK_CNTL, ®);
586 reg = (reg >> 12) & 7;
590 parent_rate = XTAL_RATE;
595 parent_rate = meson_clk_get_rate_by_id(clk, parents[reg]);
599 regmap_read(priv->map, HHI_MPEG_CLK_CNTL, ®);
600 reg = reg & ((1 << 7) - 1);
602 /* clk81 divider is zero based */
603 return parent_rate / (reg + 1);
606 static long mpll_rate_from_params(unsigned long parent_rate,
610 unsigned long divisor = (SDM_DEN * n2) + sdm;
615 return DIV_ROUND_UP_ULL((u64)parent_rate * SDM_DEN, divisor);
618 static struct parm meson_mpll0_parm[3] = {
619 {HHI_MPLL_CNTL7, 0, 14}, /* psdm */
620 {HHI_MPLL_CNTL7, 16, 9}, /* pn2 */
623 static struct parm meson_mpll1_parm[3] = {
624 {HHI_MPLL_CNTL8, 0, 14}, /* psdm */
625 {HHI_MPLL_CNTL8, 16, 9}, /* pn2 */
628 static struct parm meson_mpll2_parm[3] = {
629 {HHI_MPLL_CNTL9, 0, 14}, /* psdm */
630 {HHI_MPLL_CNTL9, 16, 9}, /* pn2 */
634 * MultiPhase Locked Loops are outputs from a PLL with additional frequency
635 * scaling capabilities. MPLL rates are calculated as:
637 * f(N2_integer, SDM_IN ) = 2.0G/(N2_integer + SDM_IN/16384)
639 static ulong meson_mpll_get_rate(struct clk *clk, unsigned long id)
641 struct meson_clk *priv = dev_get_priv(clk->dev);
642 struct parm *psdm, *pn2;
643 unsigned long sdm, n2;
644 unsigned long parent_rate;
649 psdm = &meson_mpll0_parm[0];
650 pn2 = &meson_mpll0_parm[1];
653 psdm = &meson_mpll1_parm[0];
654 pn2 = &meson_mpll1_parm[1];
657 psdm = &meson_mpll2_parm[0];
658 pn2 = &meson_mpll2_parm[1];
664 parent_rate = meson_clk_get_rate_by_id(clk, CLKID_FIXED_PLL);
665 if (IS_ERR_VALUE(parent_rate))
668 regmap_read(priv->map, psdm->reg_off, ®);
669 sdm = PARM_GET(psdm->width, psdm->shift, reg);
671 regmap_read(priv->map, pn2->reg_off, ®);
672 n2 = PARM_GET(pn2->width, pn2->shift, reg);
674 return mpll_rate_from_params(parent_rate, sdm, n2);
677 static struct parm meson_fixed_pll_parm[3] = {
678 {HHI_MPLL_CNTL, 0, 9}, /* pm */
679 {HHI_MPLL_CNTL, 9, 5}, /* pn */
680 {HHI_MPLL_CNTL, 16, 2}, /* pod */
683 static struct parm meson_sys_pll_parm[3] = {
684 {HHI_SYS_PLL_CNTL, 0, 9}, /* pm */
685 {HHI_SYS_PLL_CNTL, 9, 5}, /* pn */
686 {HHI_SYS_PLL_CNTL, 10, 2}, /* pod */
689 static ulong meson_pll_get_rate(struct clk *clk, unsigned long id)
691 struct meson_clk *priv = dev_get_priv(clk->dev);
692 struct parm *pm, *pn, *pod;
693 unsigned long parent_rate_mhz = XTAL_RATE / 1000000;
698 case CLKID_FIXED_PLL:
699 pm = &meson_fixed_pll_parm[0];
700 pn = &meson_fixed_pll_parm[1];
701 pod = &meson_fixed_pll_parm[2];
704 pm = &meson_sys_pll_parm[0];
705 pn = &meson_sys_pll_parm[1];
706 pod = &meson_sys_pll_parm[2];
712 regmap_read(priv->map, pn->reg_off, ®);
713 n = PARM_GET(pn->width, pn->shift, reg);
715 regmap_read(priv->map, pm->reg_off, ®);
716 m = PARM_GET(pm->width, pm->shift, reg);
718 regmap_read(priv->map, pod->reg_off, ®);
719 od = PARM_GET(pod->width, pod->shift, reg);
721 return ((parent_rate_mhz * m / n) >> od) * 1000000;
724 static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id)
729 case CLKID_FIXED_PLL:
731 rate = meson_pll_get_rate(clk, id);
733 case CLKID_FCLK_DIV2:
734 rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 2;
736 case CLKID_FCLK_DIV3:
737 rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 3;
739 case CLKID_FCLK_DIV4:
740 rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 4;
742 case CLKID_FCLK_DIV5:
743 rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 5;
745 case CLKID_FCLK_DIV7:
746 rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 7;
751 rate = meson_mpll_get_rate(clk, id);
754 rate = meson_clk81_get_rate(clk);
757 rate = meson_div_get_rate(clk, CLKID_VPU_0_DIV);
760 rate = meson_div_get_rate(clk, CLKID_VPU_1_DIV);
763 rate = meson_mux_get_rate(clk, CLKID_VAPB_SEL);
766 rate = meson_div_get_rate(clk, CLKID_VAPB_0_DIV);
769 rate = meson_div_get_rate(clk, CLKID_VAPB_1_DIV);
771 case CLKID_VPU_0_DIV:
772 case CLKID_VPU_1_DIV:
773 case CLKID_VAPB_0_DIV:
774 case CLKID_VAPB_1_DIV:
775 rate = meson_div_get_rate(clk, id);
778 case CLKID_VPU_0_SEL:
779 case CLKID_VPU_1_SEL:
781 case CLKID_VAPB_0_SEL:
782 case CLKID_VAPB_1_SEL:
783 rate = meson_mux_get_rate(clk, id);
786 if (gates[id].reg != 0) {
788 rate = meson_clk81_get_rate(clk);
794 debug("clock %lu has rate %lu\n", id, rate);
798 static ulong meson_clk_get_rate(struct clk *clk)
800 return meson_clk_get_rate_by_id(clk, clk->id);
803 static int meson_clk_set_parent(struct clk *clk, struct clk *parent)
805 return meson_mux_set_parent(clk, clk->id, parent->id);
808 static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned long id,
809 ulong rate, ulong current_rate)
811 if (current_rate == rate)
816 case CLKID_FIXED_PLL:
818 case CLKID_FCLK_DIV2:
819 case CLKID_FCLK_DIV3:
820 case CLKID_FCLK_DIV4:
821 case CLKID_FCLK_DIV5:
822 case CLKID_FCLK_DIV7:
829 return meson_clk_set_rate_by_id(clk,
830 meson_mux_get_parent(clk, CLKID_VPU), rate,
834 return meson_clk_set_rate_by_id(clk,
835 meson_mux_get_parent(clk, CLKID_VAPB_SEL),
838 return meson_div_set_rate(clk, CLKID_VPU_0_DIV, rate,
841 return meson_div_set_rate(clk, CLKID_VPU_1_DIV, rate,
844 return meson_div_set_rate(clk, CLKID_VAPB_0_DIV, rate,
847 return meson_div_set_rate(clk, CLKID_VAPB_1_DIV, rate,
849 case CLKID_VPU_0_DIV:
850 case CLKID_VPU_1_DIV:
851 case CLKID_VAPB_0_DIV:
852 case CLKID_VAPB_1_DIV:
853 return meson_div_set_rate(clk, id, rate, current_rate);
861 static ulong meson_clk_set_rate(struct clk *clk, ulong rate)
863 ulong current_rate = meson_clk_get_rate_by_id(clk, clk->id);
866 if (IS_ERR_VALUE(current_rate))
869 debug("%s: setting rate of %ld from %ld to %ld\n",
870 __func__, clk->id, current_rate, rate);
872 ret = meson_clk_set_rate_by_id(clk, clk->id, rate, current_rate);
873 if (IS_ERR_VALUE(ret))
876 debug("clock %lu has new rate %lu\n", clk->id,
877 meson_clk_get_rate_by_id(clk, clk->id));
882 static int meson_clk_probe(struct udevice *dev)
884 struct meson_clk *priv = dev_get_priv(dev);
886 priv->map = syscon_node_to_regmap(dev_get_parent(dev)->node);
887 if (IS_ERR(priv->map))
888 return PTR_ERR(priv->map);
891 * Depending on the boot src, the state of the MMC clock might
892 * be different. Reset it to make sure we won't get stuck
894 regmap_write(priv->map, HHI_NAND_CLK_CNTL, 0);
895 regmap_write(priv->map, HHI_SD_EMMC_CLK_CNTL, 0);
897 debug("meson-clk: probed\n");
902 static struct clk_ops meson_clk_ops = {
903 .disable = meson_clk_disable,
904 .enable = meson_clk_enable,
905 .get_rate = meson_clk_get_rate,
906 .set_parent = meson_clk_set_parent,
907 .set_rate = meson_clk_set_rate,
910 static const struct udevice_id meson_clk_ids[] = {
911 { .compatible = "amlogic,gxbb-clkc" },
912 { .compatible = "amlogic,gxl-clkc" },
916 U_BOOT_DRIVER(meson_clk) = {
919 .of_match = meson_clk_ids,
920 .priv_auto_alloc_size = sizeof(struct meson_clk),
921 .ops = &meson_clk_ops,
922 .probe = meson_clk_probe,