drivers/clk/mediatek/clk-mtk.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (C) 2018 MediaTek Inc.
   4  * Author: Ryder Lee <ryder.lee@mediatek.com>
   5  */
   6
   7 #ifndef __DRV_CLK_MTK_H
   8 #define __DRV_CLK_MTK_H
   9
  10 #define CLK_XTAL                        0
  11 #define MHZ                             (1000 * 1000)
  12
  13 #define HAVE_RST_BAR                    BIT(0)
  14 #define CLK_DOMAIN_SCPSYS               BIT(0)
  15 #define CLK_MUX_SETCLR_UPD              BIT(1)
  16
  17 #define CLK_GATE_SETCLR                 BIT(0)
  18 #define CLK_GATE_SETCLR_INV             BIT(1)
  19 #define CLK_GATE_NO_SETCLR              BIT(2)
  20 #define CLK_GATE_NO_SETCLR_INV          BIT(3)
  21 #define CLK_GATE_MASK                   GENMASK(3, 0)
  22
  23 #define CLK_PARENT_APMIXED              BIT(4)
  24 #define CLK_PARENT_TOPCKGEN             BIT(5)
  25 #define CLK_PARENT_MASK                 GENMASK(5, 4)
  26
  27 #define ETHSYS_HIFSYS_RST_CTRL_OFS      0x34
  28
  29 /* struct mtk_pll_data - hardware-specific PLLs data */
  30 struct mtk_pll_data {
  31         const int id;
  32         u32 reg;
  33         u32 pwr_reg;
  34         u32 en_mask;
  35         u32 pd_reg;
  36         int pd_shift;
  37         u32 flags;
  38         u32 rst_bar_mask;
  39         u64 fmax;
  40         u64 fmin;
  41         int pcwbits;
  42         int pcwibits;
  43         u32 pcw_reg;
  44         int pcw_shift;
  45         u32 pcw_chg_reg;
  46 };
  47
  48 /**
  49  * struct mtk_fixed_clk - fixed clocks
  50  *
  51  * @id:         index of clocks
  52  * @parent:     index of parnet clocks
  53  * @rate:       fixed rate
  54  */
  55 struct mtk_fixed_clk {
  56         const int id;
  57         const int parent;
  58         unsigned long rate;
  59 };
  60
  61 #define FIXED_CLK(_id, _parent, _rate) {                \
  62                 .id = _id,                              \
  63                 .parent = _parent,                      \
  64                 .rate = _rate,                          \
  65         }
  66
  67 /**
  68  * struct mtk_fixed_factor - fixed multiplier and divider clocks
  69  *
  70  * @id:         index of clocks
  71  * @parent:     index of parnet clocks
  72  * @mult:       multiplier
  73  * @div:        divider
  74  * @flag:       hardware-specific flags
  75  */
  76 struct mtk_fixed_factor {
  77         const int id;
  78         const int parent;
  79         u32 mult;
  80         u32 div;
  81         u32 flags;
  82 };
  83
  84 #define FACTOR(_id, _parent, _mult, _div, _flags) {     \
  85                 .id = _id,                              \
  86                 .parent = _parent,                      \
  87                 .mult = _mult,                          \
  88                 .div = _div,                            \
  89                 .flags = _flags,                        \
  90         }
  91
  92 /**
  93  * struct mtk_composite - aggregate clock of mux, divider and gate clocks
  94  *
  95  * @id:                 index of clocks
  96  * @parent:             index of parnet clocks
  97  * @mux_reg:            hardware-specific mux register
  98  * @gate_reg:           hardware-specific gate register
  99  * @mux_mask:           mask to the mux bit field
 100  * @mux_shift:          shift to the mux bit field
 101  * @gate_shift:         shift to the gate bit field
 102  * @num_parents:        number of parent clocks
 103  * @flags:              hardware-specific flags
 104  */
 105 struct mtk_composite {
 106         const int id;
 107         const int *parent;
 108         u32 mux_reg;
 109         u32 mux_set_reg;
 110         u32 mux_clr_reg;
 111         u32 upd_reg;
 112         u32 gate_reg;
 113         u32 mux_mask;
 114         signed char mux_shift;
 115         signed char upd_shift;
 116         signed char gate_shift;
 117         signed char num_parents;
 118         u16 flags;
 119 };
 120
 121 #define MUX_GATE_FLAGS(_id, _parents, _reg, _shift, _width, _gate,      \
 122                        _flags) {                                        \
 123                 .id = _id,                                              \
 124                 .mux_reg = _reg,                                        \
 125                 .mux_shift = _shift,                                    \
 126                 .mux_mask = BIT(_width) - 1,                            \
 127                 .gate_reg = _reg,                                       \
 128                 .gate_shift = _gate,                                    \
 129                 .parent = _parents,                                     \
 130                 .num_parents = ARRAY_SIZE(_parents),                    \
 131                 .flags = _flags,                                        \
 132         }
 133
 134 #define MUX_GATE(_id, _parents, _reg, _shift, _width, _gate)            \
 135         MUX_GATE_FLAGS(_id, _parents, _reg, _shift, _width, _gate, 0)
 136
 137 #define MUX(_id, _parents, _reg, _shift, _width) {                      \
 138                 .id = _id,                                              \
 139                 .mux_reg = _reg,                                        \
 140                 .mux_shift = _shift,                                    \
 141                 .mux_mask = BIT(_width) - 1,                            \
 142                 .gate_shift = -1,                                       \
 143                 .parent = _parents,                                     \
 144                 .num_parents = ARRAY_SIZE(_parents),                    \
 145                 .flags = 0,                                             \
 146         }
 147
 148 #define MUX_CLR_SET_UPD_FLAGS(_id, _parents, _mux_ofs, _mux_set_ofs,\
 149                         _mux_clr_ofs, _shift, _width, _gate,            \
 150                         _upd_ofs, _upd, _flags) {                       \
 151                 .id = _id,                                              \
 152                 .mux_reg = _mux_ofs,                                    \
 153                 .mux_set_reg = _mux_set_ofs,                    \
 154                 .mux_clr_reg = _mux_clr_ofs,                    \
 155                 .upd_reg = _upd_ofs,                                    \
 156                 .upd_shift = _upd,                                      \
 157                 .mux_shift = _shift,                                    \
 158                 .mux_mask = BIT(_width) - 1,                            \
 159                 .gate_reg = _mux_ofs,                                   \
 160                 .gate_shift = _gate,                                    \
 161                 .parent = _parents,                                     \
 162                 .num_parents = ARRAY_SIZE(_parents),                    \
 163                 .flags = _flags,                                        \
 164         }
 165
 166 struct mtk_gate_regs {
 167         u32 sta_ofs;
 168         u32 clr_ofs;
 169         u32 set_ofs;
 170 };
 171
 172 /**
 173  * struct mtk_gate - gate clocks
 174  *
 175  * @id:         index of gate clocks
 176  * @parent:     index of parnet clocks
 177  * @regs:       hardware-specific mux register
 178  * @shift:      shift to the gate bit field
 179  * @flags:      hardware-specific flags
 180  */
 181 struct mtk_gate {
 182         const int id;
 183         const int parent;
 184         const struct mtk_gate_regs *regs;
 185         int shift;
 186         u32 flags;
 187 };
 188
 189 /* struct mtk_clk_tree - clock tree */
 190 struct mtk_clk_tree {
 191         unsigned long xtal_rate;
 192         unsigned long xtal2_rate;
 193         const int fdivs_offs;
 194         const int muxes_offs;
 195         const struct mtk_pll_data *plls;
 196         const struct mtk_fixed_clk *fclks;
 197         const struct mtk_fixed_factor *fdivs;
 198         const struct mtk_composite *muxes;
 199 };
 200
 201 struct mtk_clk_priv {
 202         void __iomem *base;
 203         const struct mtk_clk_tree *tree;
 204 };
 205
 206 struct mtk_cg_priv {
 207         void __iomem *base;
 208         const struct mtk_clk_tree *tree;
 209         const struct mtk_gate *gates;
 210 };
 211
 212 extern const struct clk_ops mtk_clk_apmixedsys_ops;
 213 extern const struct clk_ops mtk_clk_topckgen_ops;
 214 extern const struct clk_ops mtk_clk_gate_ops;
 215
 216 int mtk_common_clk_init(struct udevice *dev,
 217                         const struct mtk_clk_tree *tree);
 218 int mtk_common_clk_gate_init(struct udevice *dev,
 219                              const struct mtk_clk_tree *tree,
 220                              const struct mtk_gate *gates);
 221
 222 #endif /* __DRV_CLK_MTK_H */