1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2018 MediaTek Inc.
4 * Author: Ryder Lee <ryder.lee@mediatek.com>
7 #ifndef __DRV_CLK_MTK_H
8 #define __DRV_CLK_MTK_H
10 #include <linux/bitops.h>
12 #define MHZ (1000 * 1000)
14 #define HAVE_RST_BAR BIT(0)
15 #define CLK_DOMAIN_SCPSYS BIT(0)
16 #define CLK_MUX_SETCLR_UPD BIT(1)
18 #define CLK_GATE_SETCLR BIT(0)
19 #define CLK_GATE_SETCLR_INV BIT(1)
20 #define CLK_GATE_NO_SETCLR BIT(2)
21 #define CLK_GATE_NO_SETCLR_INV BIT(3)
22 #define CLK_GATE_MASK GENMASK(3, 0)
24 #define CLK_PARENT_APMIXED BIT(4)
25 #define CLK_PARENT_TOPCKGEN BIT(5)
26 #define CLK_PARENT_MASK GENMASK(5, 4)
28 #define ETHSYS_HIFSYS_RST_CTRL_OFS 0x34
30 /* struct mtk_pll_data - hardware-specific PLLs data */
50 * struct mtk_fixed_clk - fixed clocks
52 * @id: index of clocks
53 * @parent: index of parnet clocks
56 struct mtk_fixed_clk {
62 #define FIXED_CLK(_id, _parent, _rate) { \
69 * struct mtk_fixed_factor - fixed multiplier and divider clocks
71 * @id: index of clocks
72 * @parent: index of parnet clocks
75 * @flag: hardware-specific flags
77 struct mtk_fixed_factor {
85 #define FACTOR(_id, _parent, _mult, _div, _flags) { \
94 * struct mtk_composite - aggregate clock of mux, divider and gate clocks
96 * @id: index of clocks
97 * @parent: index of parnet clocks
98 * @mux_reg: hardware-specific mux register
99 * @gate_reg: hardware-specific gate register
100 * @mux_mask: mask to the mux bit field
101 * @mux_shift: shift to the mux bit field
102 * @gate_shift: shift to the gate bit field
103 * @num_parents: number of parent clocks
104 * @flags: hardware-specific flags
106 struct mtk_composite {
115 signed char mux_shift;
116 signed char upd_shift;
117 signed char gate_shift;
118 signed char num_parents;
122 #define MUX_GATE_FLAGS(_id, _parents, _reg, _shift, _width, _gate, \
126 .mux_shift = _shift, \
127 .mux_mask = BIT(_width) - 1, \
129 .gate_shift = _gate, \
130 .parent = _parents, \
131 .num_parents = ARRAY_SIZE(_parents), \
135 #define MUX_GATE(_id, _parents, _reg, _shift, _width, _gate) \
136 MUX_GATE_FLAGS(_id, _parents, _reg, _shift, _width, _gate, 0)
138 #define MUX(_id, _parents, _reg, _shift, _width) { \
141 .mux_shift = _shift, \
142 .mux_mask = BIT(_width) - 1, \
144 .parent = _parents, \
145 .num_parents = ARRAY_SIZE(_parents), \
149 #define MUX_CLR_SET_UPD_FLAGS(_id, _parents, _mux_ofs, _mux_set_ofs,\
150 _mux_clr_ofs, _shift, _width, _gate, \
151 _upd_ofs, _upd, _flags) { \
153 .mux_reg = _mux_ofs, \
154 .mux_set_reg = _mux_set_ofs, \
155 .mux_clr_reg = _mux_clr_ofs, \
156 .upd_reg = _upd_ofs, \
158 .mux_shift = _shift, \
159 .mux_mask = BIT(_width) - 1, \
160 .gate_reg = _mux_ofs, \
161 .gate_shift = _gate, \
162 .parent = _parents, \
163 .num_parents = ARRAY_SIZE(_parents), \
167 struct mtk_gate_regs {
174 * struct mtk_gate - gate clocks
176 * @id: index of gate clocks
177 * @parent: index of parnet clocks
178 * @regs: hardware-specific mux register
179 * @shift: shift to the gate bit field
180 * @flags: hardware-specific flags
185 const struct mtk_gate_regs *regs;
190 /* struct mtk_clk_tree - clock tree */
191 struct mtk_clk_tree {
192 unsigned long xtal_rate;
193 unsigned long xtal2_rate;
194 const int fdivs_offs;
195 const int muxes_offs;
196 const struct mtk_pll_data *plls;
197 const struct mtk_fixed_clk *fclks;
198 const struct mtk_fixed_factor *fdivs;
199 const struct mtk_composite *muxes;
202 struct mtk_clk_priv {
204 const struct mtk_clk_tree *tree;
209 const struct mtk_clk_tree *tree;
210 const struct mtk_gate *gates;
213 extern const struct clk_ops mtk_clk_apmixedsys_ops;
214 extern const struct clk_ops mtk_clk_topckgen_ops;
215 extern const struct clk_ops mtk_clk_gate_ops;
217 int mtk_common_clk_init(struct udevice *dev,
218 const struct mtk_clk_tree *tree);
219 int mtk_common_clk_gate_init(struct udevice *dev,
220 const struct mtk_clk_tree *tree,
221 const struct mtk_gate *gates);
223 #endif /* __DRV_CLK_MTK_H */