1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2018 MediaTek Inc.
4 * Author: Ryder Lee <ryder.lee@mediatek.com>
7 #ifndef __DRV_CLK_MTK_H
8 #define __DRV_CLK_MTK_H
11 #define MHZ (1000 * 1000)
13 #define HAVE_RST_BAR BIT(0)
14 #define CLK_DOMAIN_SCPSYS BIT(0)
16 #define CLK_GATE_SETCLR BIT(0)
17 #define CLK_GATE_SETCLR_INV BIT(1)
18 #define CLK_GATE_NO_SETCLR BIT(2)
19 #define CLK_GATE_NO_SETCLR_INV BIT(3)
20 #define CLK_GATE_MASK GENMASK(3, 0)
22 #define CLK_PARENT_APMIXED BIT(4)
23 #define CLK_PARENT_TOPCKGEN BIT(5)
24 #define CLK_PARENT_MASK GENMASK(5, 4)
26 /* struct mtk_pll_data - hardware-specific PLLs data */
43 * struct mtk_fixed_clk - fixed clocks
45 * @id: index of clocks
46 * @parent: index of parnet clocks
49 struct mtk_fixed_clk {
55 #define FIXED_CLK(_id, _parent, _rate) { \
62 * struct mtk_fixed_factor - fixed multiplier and divider clocks
64 * @id: index of clocks
65 * @parent: index of parnet clocks
68 * @flag: hardware-specific flags
70 struct mtk_fixed_factor {
78 #define FACTOR(_id, _parent, _mult, _div, _flags) { \
87 * struct mtk_composite - aggregate clock of mux, divider and gate clocks
89 * @id: index of clocks
90 * @parent: index of parnet clocks
91 * @mux_reg: hardware-specific mux register
92 * @gate_reg: hardware-specific gate register
93 * @mux_mask: mask to the mux bit field
94 * @mux_shift: shift to the mux bit field
95 * @gate_shift: shift to the gate bit field
96 * @num_parents: number of parent clocks
97 * @flags: hardware-specific flags
99 struct mtk_composite {
105 signed char mux_shift;
106 signed char gate_shift;
107 signed char num_parents;
111 #define MUX_GATE_FLAGS(_id, _parents, _reg, _shift, _width, _gate, \
115 .mux_shift = _shift, \
116 .mux_mask = BIT(_width) - 1, \
118 .gate_shift = _gate, \
119 .parent = _parents, \
120 .num_parents = ARRAY_SIZE(_parents), \
124 #define MUX_GATE(_id, _parents, _reg, _shift, _width, _gate) \
125 MUX_GATE_FLAGS(_id, _parents, _reg, _shift, _width, _gate, 0)
127 #define MUX(_id, _parents, _reg, _shift, _width) { \
130 .mux_shift = _shift, \
131 .mux_mask = BIT(_width) - 1, \
133 .parent = _parents, \
134 .num_parents = ARRAY_SIZE(_parents), \
138 struct mtk_gate_regs {
145 * struct mtk_gate - gate clocks
147 * @id: index of gate clocks
148 * @parent: index of parnet clocks
149 * @regs: hardware-specific mux register
150 * @shift: shift to the gate bit field
151 * @flags: hardware-specific flags
156 const struct mtk_gate_regs *regs;
161 /* struct mtk_clk_tree - clock tree */
162 struct mtk_clk_tree {
163 unsigned long xtal_rate;
164 unsigned long xtal2_rate;
165 const int fdivs_offs;
166 const int muxes_offs;
167 const struct mtk_pll_data *plls;
168 const struct mtk_fixed_clk *fclks;
169 const struct mtk_fixed_factor *fdivs;
170 const struct mtk_composite *muxes;
173 struct mtk_clk_priv {
175 const struct mtk_clk_tree *tree;
180 const struct mtk_clk_tree *tree;
181 const struct mtk_gate *gates;
184 extern const struct clk_ops mtk_clk_apmixedsys_ops;
185 extern const struct clk_ops mtk_clk_topckgen_ops;
186 extern const struct clk_ops mtk_clk_gate_ops;
188 int mtk_common_clk_init(struct udevice *dev,
189 const struct mtk_clk_tree *tree);
190 int mtk_common_clk_gate_init(struct udevice *dev,
191 const struct mtk_clk_tree *tree,
192 const struct mtk_gate *gates);
194 #endif /* __DRV_CLK_MTK_H */