1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2018 MediaTek Inc.
4 * Author: Ryder Lee <ryder.lee@mediatek.com>
7 #ifndef __DRV_CLK_MTK_H
8 #define __DRV_CLK_MTK_H
11 #define MHZ (1000 * 1000)
13 #define HAVE_RST_BAR BIT(0)
14 #define CLK_DOMAIN_SCPSYS BIT(0)
15 #define CLK_MUX_SETCLR_UPD BIT(1)
17 #define CLK_GATE_SETCLR BIT(0)
18 #define CLK_GATE_SETCLR_INV BIT(1)
19 #define CLK_GATE_NO_SETCLR BIT(2)
20 #define CLK_GATE_NO_SETCLR_INV BIT(3)
21 #define CLK_GATE_MASK GENMASK(3, 0)
23 #define CLK_PARENT_APMIXED BIT(4)
24 #define CLK_PARENT_TOPCKGEN BIT(5)
25 #define CLK_PARENT_MASK GENMASK(5, 4)
27 #define ETHSYS_HIFSYS_RST_CTRL_OFS 0x34
29 /* struct mtk_pll_data - hardware-specific PLLs data */
49 * struct mtk_fixed_clk - fixed clocks
51 * @id: index of clocks
52 * @parent: index of parnet clocks
55 struct mtk_fixed_clk {
61 #define FIXED_CLK(_id, _parent, _rate) { \
68 * struct mtk_fixed_factor - fixed multiplier and divider clocks
70 * @id: index of clocks
71 * @parent: index of parnet clocks
74 * @flag: hardware-specific flags
76 struct mtk_fixed_factor {
84 #define FACTOR(_id, _parent, _mult, _div, _flags) { \
93 * struct mtk_composite - aggregate clock of mux, divider and gate clocks
95 * @id: index of clocks
96 * @parent: index of parnet clocks
97 * @mux_reg: hardware-specific mux register
98 * @gate_reg: hardware-specific gate register
99 * @mux_mask: mask to the mux bit field
100 * @mux_shift: shift to the mux bit field
101 * @gate_shift: shift to the gate bit field
102 * @num_parents: number of parent clocks
103 * @flags: hardware-specific flags
105 struct mtk_composite {
114 signed char mux_shift;
115 signed char upd_shift;
116 signed char gate_shift;
117 signed char num_parents;
121 #define MUX_GATE_FLAGS(_id, _parents, _reg, _shift, _width, _gate, \
125 .mux_shift = _shift, \
126 .mux_mask = BIT(_width) - 1, \
128 .gate_shift = _gate, \
129 .parent = _parents, \
130 .num_parents = ARRAY_SIZE(_parents), \
134 #define MUX_GATE(_id, _parents, _reg, _shift, _width, _gate) \
135 MUX_GATE_FLAGS(_id, _parents, _reg, _shift, _width, _gate, 0)
137 #define MUX(_id, _parents, _reg, _shift, _width) { \
140 .mux_shift = _shift, \
141 .mux_mask = BIT(_width) - 1, \
143 .parent = _parents, \
144 .num_parents = ARRAY_SIZE(_parents), \
148 #define MUX_CLR_SET_UPD_FLAGS(_id, _parents, _mux_ofs, _mux_set_ofs,\
149 _mux_clr_ofs, _shift, _width, _gate, \
150 _upd_ofs, _upd, _flags) { \
152 .mux_reg = _mux_ofs, \
153 .mux_set_reg = _mux_set_ofs, \
154 .mux_clr_reg = _mux_clr_ofs, \
155 .upd_reg = _upd_ofs, \
157 .mux_shift = _shift, \
158 .mux_mask = BIT(_width) - 1, \
159 .gate_reg = _mux_ofs, \
160 .gate_shift = _gate, \
161 .parent = _parents, \
162 .num_parents = ARRAY_SIZE(_parents), \
166 struct mtk_gate_regs {
173 * struct mtk_gate - gate clocks
175 * @id: index of gate clocks
176 * @parent: index of parnet clocks
177 * @regs: hardware-specific mux register
178 * @shift: shift to the gate bit field
179 * @flags: hardware-specific flags
184 const struct mtk_gate_regs *regs;
189 /* struct mtk_clk_tree - clock tree */
190 struct mtk_clk_tree {
191 unsigned long xtal_rate;
192 unsigned long xtal2_rate;
193 const int fdivs_offs;
194 const int muxes_offs;
195 const struct mtk_pll_data *plls;
196 const struct mtk_fixed_clk *fclks;
197 const struct mtk_fixed_factor *fdivs;
198 const struct mtk_composite *muxes;
201 struct mtk_clk_priv {
203 const struct mtk_clk_tree *tree;
208 const struct mtk_clk_tree *tree;
209 const struct mtk_gate *gates;
212 extern const struct clk_ops mtk_clk_apmixedsys_ops;
213 extern const struct clk_ops mtk_clk_topckgen_ops;
214 extern const struct clk_ops mtk_clk_gate_ops;
216 int mtk_common_clk_init(struct udevice *dev,
217 const struct mtk_clk_tree *tree);
218 int mtk_common_clk_gate_init(struct udevice *dev,
219 const struct mtk_clk_tree *tree,
220 const struct mtk_gate *gates);
222 #endif /* __DRV_CLK_MTK_H */