1 // SPDX-License-Identifier: GPL-2.0
3 * MediaTek common clock driver
5 * Copyright (C) 2018 MediaTek Inc.
6 * Author: Ryder Lee <ryder.lee@mediatek.com>
10 #include <clk-uclass.h>
20 #define CON0_BASE_EN BIT(0)
21 #define CON0_PWR_ON BIT(0)
22 #define CON0_ISO_EN BIT(1)
23 #define CON1_PCW_CHG BIT(31)
25 #define POSTDIV_MASK 0x7
26 #define INTEGER_BITS 7
28 /* scpsys clock off control */
29 #define CLK_SCP_CFG0 0x200
30 #define CLK_SCP_CFG1 0x204
31 #define SCP_ARMCK_OFF_EN GENMASK(9, 0)
32 #define SCP_AXICK_DCM_DIS_EN BIT(0)
33 #define SCP_AXICK_26M_SEL_EN BIT(4)
35 /* shared functions */
38 * In case the rate change propagation to parent clocks is undesirable,
39 * this function is recursively called to find the parent to calculate
40 * the accurate frequency.
42 static int mtk_clk_find_parent_rate(struct clk *clk, int id,
43 const struct driver *drv)
45 struct clk parent = { .id = id, };
50 if (uclass_get_device_by_driver(UCLASS_CLK, drv, &dev))
55 parent.dev = clk->dev;
58 return clk_get_rate(&parent);
61 static int mtk_clk_mux_set_parent(void __iomem *base, u32 parent,
62 const struct mtk_composite *mux)
66 while (mux->parent[index] != parent)
67 if (++index == mux->num_parents)
70 /* switch mux to a select parent */
71 val = readl(base + mux->mux_reg);
72 val &= ~(mux->mux_mask << mux->mux_shift);
74 val |= index << mux->mux_shift;
75 writel(val, base + mux->mux_reg);
80 /* apmixedsys functions */
82 static unsigned long __mtk_pll_recalc_rate(const struct mtk_pll_data *pll,
83 u32 fin, u32 pcw, int postdiv)
85 int pcwbits = pll->pcwbits;
90 /* The fractional part of the PLL divider. */
91 pcwfbits = pcwbits > INTEGER_BITS ? pcwbits - INTEGER_BITS : 0;
95 if (pcwfbits && (vco & GENMASK(pcwfbits - 1, 0)))
103 return ((unsigned long)vco + postdiv - 1) / postdiv;
107 * MediaTek PLLs are configured through their pcw value. The pcw value
108 * describes a divider in the PLL feedback loop which consists of 7 bits
109 * for the integer part and the remaining bits (if present) for the
110 * fractional part. Also they have a 3 bit power-of-two post divider.
112 static void mtk_pll_set_rate_regs(struct clk *clk, u32 pcw, int postdiv)
114 struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
115 const struct mtk_pll_data *pll = &priv->tree->plls[clk->id];
119 val = readl(priv->base + pll->pd_reg);
120 val &= ~(POSTDIV_MASK << pll->pd_shift);
121 val |= (ffs(postdiv) - 1) << pll->pd_shift;
123 /* postdiv and pcw need to set at the same time if on same register */
124 if (pll->pd_reg != pll->pcw_reg) {
125 writel(val, priv->base + pll->pd_reg);
126 val = readl(priv->base + pll->pcw_reg);
130 val &= ~GENMASK(pll->pcw_shift + pll->pcwbits - 1, pll->pcw_shift);
131 val |= pcw << pll->pcw_shift;
132 val &= ~CON1_PCW_CHG;
133 writel(val, priv->base + pll->pcw_reg);
136 writel(val, priv->base + pll->pcw_reg);
142 * mtk_pll_calc_values - calculate good values for a given input frequency.
144 * @pcw: The pcw value (output)
145 * @postdiv: The post divider (output)
146 * @freq: The desired target frequency
148 static void mtk_pll_calc_values(struct clk *clk, u32 *pcw, u32 *postdiv,
151 struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
152 const struct mtk_pll_data *pll = &priv->tree->plls[clk->id];
153 unsigned long fmin = 1000 * MHZ;
157 if (freq > pll->fmax)
160 for (val = 0; val < 5; val++) {
162 if ((u64)freq * *postdiv >= fmin)
166 /* _pcw = freq * postdiv / xtal_rate * 2^pcwfbits */
167 _pcw = ((u64)freq << val) << (pll->pcwbits - INTEGER_BITS);
168 do_div(_pcw, priv->tree->xtal2_rate);
173 static ulong mtk_apmixedsys_set_rate(struct clk *clk, ulong rate)
178 mtk_pll_calc_values(clk, &pcw, &postdiv, rate);
179 mtk_pll_set_rate_regs(clk, pcw, postdiv);
184 static ulong mtk_apmixedsys_get_rate(struct clk *clk)
186 struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
187 const struct mtk_pll_data *pll = &priv->tree->plls[clk->id];
191 postdiv = (readl(priv->base + pll->pd_reg) >> pll->pd_shift) &
193 postdiv = 1 << postdiv;
195 pcw = readl(priv->base + pll->pcw_reg) >> pll->pcw_shift;
196 pcw &= GENMASK(pll->pcwbits - 1, 0);
198 return __mtk_pll_recalc_rate(pll, priv->tree->xtal2_rate,
202 static int mtk_apmixedsys_enable(struct clk *clk)
204 struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
205 const struct mtk_pll_data *pll = &priv->tree->plls[clk->id];
208 r = readl(priv->base + pll->pwr_reg) | CON0_PWR_ON;
209 writel(r, priv->base + pll->pwr_reg);
212 r = readl(priv->base + pll->pwr_reg) & ~CON0_ISO_EN;
213 writel(r, priv->base + pll->pwr_reg);
216 r = readl(priv->base + pll->reg + REG_CON0);
218 writel(r, priv->base + pll->reg + REG_CON0);
222 if (pll->flags & HAVE_RST_BAR) {
223 r = readl(priv->base + pll->reg + REG_CON0);
224 r |= pll->rst_bar_mask;
225 writel(r, priv->base + pll->reg + REG_CON0);
231 static int mtk_apmixedsys_disable(struct clk *clk)
233 struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
234 const struct mtk_pll_data *pll = &priv->tree->plls[clk->id];
237 if (pll->flags & HAVE_RST_BAR) {
238 r = readl(priv->base + pll->reg + REG_CON0);
239 r &= ~pll->rst_bar_mask;
240 writel(r, priv->base + pll->reg + REG_CON0);
243 r = readl(priv->base + pll->reg + REG_CON0);
245 writel(r, priv->base + pll->reg + REG_CON0);
247 r = readl(priv->base + pll->pwr_reg) | CON0_ISO_EN;
248 writel(r, priv->base + pll->pwr_reg);
250 r = readl(priv->base + pll->pwr_reg) & ~CON0_PWR_ON;
251 writel(r, priv->base + pll->pwr_reg);
256 /* topckgen functions */
258 static ulong mtk_factor_recalc_rate(const struct mtk_fixed_factor *fdiv,
261 u64 rate = parent_rate * fdiv->mult;
263 do_div(rate, fdiv->div);
268 static int mtk_topckgen_get_factor_rate(struct clk *clk, u32 off)
270 struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
271 const struct mtk_fixed_factor *fdiv = &priv->tree->fdivs[off];
274 switch (fdiv->flags & CLK_PARENT_MASK) {
275 case CLK_PARENT_APMIXED:
276 rate = mtk_clk_find_parent_rate(clk, fdiv->parent,
277 DM_GET_DRIVER(mtk_clk_apmixedsys));
279 case CLK_PARENT_TOPCKGEN:
280 rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL);
284 rate = priv->tree->xtal_rate;
287 return mtk_factor_recalc_rate(fdiv, rate);
290 static int mtk_topckgen_get_mux_rate(struct clk *clk, u32 off)
292 struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
293 const struct mtk_composite *mux = &priv->tree->muxes[off];
296 index = readl(priv->base + mux->mux_reg);
297 index &= mux->mux_mask << mux->mux_shift;
298 index = index >> mux->mux_shift;
300 if (mux->parent[index])
301 return mtk_clk_find_parent_rate(clk, mux->parent[index],
304 return priv->tree->xtal_rate;
307 static ulong mtk_topckgen_get_rate(struct clk *clk)
309 struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
311 if (clk->id < priv->tree->fdivs_offs)
312 return priv->tree->fclks[clk->id].rate;
313 else if (clk->id < priv->tree->muxes_offs)
314 return mtk_topckgen_get_factor_rate(clk, clk->id -
315 priv->tree->fdivs_offs);
317 return mtk_topckgen_get_mux_rate(clk, clk->id -
318 priv->tree->muxes_offs);
321 static int mtk_topckgen_enable(struct clk *clk)
323 struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
324 const struct mtk_composite *mux;
327 if (clk->id < priv->tree->muxes_offs)
330 mux = &priv->tree->muxes[clk->id - priv->tree->muxes_offs];
331 if (mux->gate_shift < 0)
334 /* enable clock gate */
335 val = readl(priv->base + mux->gate_reg);
336 val &= ~BIT(mux->gate_shift);
337 writel(val, priv->base + mux->gate_reg);
339 if (mux->flags & CLK_DOMAIN_SCPSYS) {
340 /* enable scpsys clock off control */
341 writel(SCP_ARMCK_OFF_EN, priv->base + CLK_SCP_CFG0);
342 writel(SCP_AXICK_DCM_DIS_EN | SCP_AXICK_26M_SEL_EN,
343 priv->base + CLK_SCP_CFG1);
349 static int mtk_topckgen_disable(struct clk *clk)
351 struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
352 const struct mtk_composite *mux;
355 if (clk->id < priv->tree->muxes_offs)
358 mux = &priv->tree->muxes[clk->id - priv->tree->muxes_offs];
359 if (mux->gate_shift < 0)
362 /* disable clock gate */
363 val = readl(priv->base + mux->gate_reg);
364 val |= BIT(mux->gate_shift);
365 writel(val, priv->base + mux->gate_reg);
370 static int mtk_topckgen_set_parent(struct clk *clk, struct clk *parent)
372 struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
374 if (clk->id < priv->tree->muxes_offs)
377 return mtk_clk_mux_set_parent(priv->base, parent->id,
378 &priv->tree->muxes[clk->id - priv->tree->muxes_offs]);
383 static int mtk_clk_gate_enable(struct clk *clk)
385 struct mtk_cg_priv *priv = dev_get_priv(clk->dev);
386 const struct mtk_gate *gate = &priv->gates[clk->id];
387 u32 bit = BIT(gate->shift);
389 switch (gate->flags & CLK_GATE_MASK) {
390 case CLK_GATE_SETCLR:
391 writel(bit, priv->base + gate->regs->clr_ofs);
393 case CLK_GATE_SETCLR_INV:
394 writel(bit, priv->base + gate->regs->set_ofs);
396 case CLK_GATE_NO_SETCLR:
397 clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, 0);
399 case CLK_GATE_NO_SETCLR_INV:
400 clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, bit);
410 static int mtk_clk_gate_disable(struct clk *clk)
412 struct mtk_cg_priv *priv = dev_get_priv(clk->dev);
413 const struct mtk_gate *gate = &priv->gates[clk->id];
414 u32 bit = BIT(gate->shift);
416 switch (gate->flags & CLK_GATE_MASK) {
417 case CLK_GATE_SETCLR:
418 writel(bit, priv->base + gate->regs->set_ofs);
420 case CLK_GATE_SETCLR_INV:
421 writel(bit, priv->base + gate->regs->clr_ofs);
423 case CLK_GATE_NO_SETCLR:
424 clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, bit);
426 case CLK_GATE_NO_SETCLR_INV:
427 clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, 0);
437 static ulong mtk_clk_gate_get_rate(struct clk *clk)
439 struct mtk_cg_priv *priv = dev_get_priv(clk->dev);
440 const struct mtk_gate *gate = &priv->gates[clk->id];
442 switch (gate->flags & CLK_PARENT_MASK) {
443 case CLK_PARENT_APMIXED:
444 return mtk_clk_find_parent_rate(clk, gate->parent,
445 DM_GET_DRIVER(mtk_clk_apmixedsys));
447 case CLK_PARENT_TOPCKGEN:
448 return mtk_clk_find_parent_rate(clk, gate->parent,
449 DM_GET_DRIVER(mtk_clk_topckgen));
453 return priv->tree->xtal_rate;
457 const struct clk_ops mtk_clk_apmixedsys_ops = {
458 .enable = mtk_apmixedsys_enable,
459 .disable = mtk_apmixedsys_disable,
460 .set_rate = mtk_apmixedsys_set_rate,
461 .get_rate = mtk_apmixedsys_get_rate,
464 const struct clk_ops mtk_clk_topckgen_ops = {
465 .enable = mtk_topckgen_enable,
466 .disable = mtk_topckgen_disable,
467 .get_rate = mtk_topckgen_get_rate,
468 .set_parent = mtk_topckgen_set_parent,
471 const struct clk_ops mtk_clk_gate_ops = {
472 .enable = mtk_clk_gate_enable,
473 .disable = mtk_clk_gate_disable,
474 .get_rate = mtk_clk_gate_get_rate,
477 int mtk_common_clk_init(struct udevice *dev,
478 const struct mtk_clk_tree *tree)
480 struct mtk_clk_priv *priv = dev_get_priv(dev);
482 priv->base = dev_read_addr_ptr(dev);
491 int mtk_common_clk_gate_init(struct udevice *dev,
492 const struct mtk_clk_tree *tree,
493 const struct mtk_gate *gates)
495 struct mtk_cg_priv *priv = dev_get_priv(dev);
497 priv->base = dev_read_addr_ptr(dev);