1 // SPDX-License-Identifier: GPL-2.0
3 * MediaTek clock driver for MT8518 SoC
5 * Copyright (C) 2019 BayLibre, SAS
6 * Author: Chen Zhong <chen.zhong@mediatek.com>
12 #include <dt-bindings/clock/mt8518-clk.h>
16 #define MT8518_PLL_FMAX (3000UL * MHZ)
17 #define MT8518_CON0_RST_BAR BIT(27)
20 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
21 _pd_shift, _pcw_reg, _pcw_shift) { \
24 .pwr_reg = _pwr_reg, \
25 .en_mask = _en_mask, \
26 .rst_bar_mask = MT8518_CON0_RST_BAR, \
27 .fmax = MT8518_PLL_FMAX, \
29 .pcwbits = _pcwbits, \
31 .pd_shift = _pd_shift, \
32 .pcw_reg = _pcw_reg, \
33 .pcw_shift = _pcw_shift, \
36 static const struct mtk_pll_data apmixed_plls[] = {
37 PLL(CLK_APMIXED_ARMPLL, 0x0100, 0x0110, 0x00000001,
38 0, 21, 0x0104, 24, 0x0104, 0),
39 PLL(CLK_APMIXED_MAINPLL, 0x0120, 0x0130, 0x00000001,
40 HAVE_RST_BAR, 21, 0x0124, 24, 0x0124, 0),
41 PLL(CLK_APMIXED_UNIVPLL, 0x0140, 0x0150, 0x30000001,
42 HAVE_RST_BAR, 7, 0x0144, 24, 0x0144, 0),
43 PLL(CLK_APMIXED_MMPLL, 0x0160, 0x0170, 0x00000001,
44 0, 21, 0x0164, 24, 0x0164, 0),
45 PLL(CLK_APMIXED_APLL1, 0x0180, 0x0190, 0x00000001,
46 0, 31, 0x0180, 1, 0x0184, 0),
47 PLL(CLK_APMIXED_APLL2, 0x01A0, 0x01B0, 0x00000001,
48 0, 31, 0x01A0, 1, 0x01A4, 0),
49 PLL(CLK_APMIXED_TVDPLL, 0x01C0, 0x01D0, 0x00000001,
50 0, 21, 0x01C4, 24, 0x01C4, 0),
54 #define FACTOR0(_id, _parent, _mult, _div) \
55 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
57 #define FACTOR1(_id, _parent, _mult, _div) \
58 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
60 #define FACTOR2(_id, _parent, _mult, _div) \
61 FACTOR(_id, _parent, _mult, _div, 0)
63 static const struct mtk_fixed_clk top_fixed_clks[] = {
64 FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 26000000),
65 FIXED_CLK(CLK_TOP_FQ_TRNG_OUT0, CLK_TOP_CLK_NULL, 500000000),
66 FIXED_CLK(CLK_TOP_FQ_TRNG_OUT1, CLK_TOP_CLK_NULL, 500000000),
67 FIXED_CLK(CLK_TOP_CLK32K, CLK_XTAL, 32000),
70 static const struct mtk_fixed_factor top_fixed_divs[] = {
71 FACTOR2(CLK_TOP_DMPLL, CLK_XTAL, 1, 1),
72 FACTOR0(CLK_TOP_MAINPLL_D4, CLK_APMIXED_MAINPLL, 1, 4),
73 FACTOR0(CLK_TOP_MAINPLL_D8, CLK_APMIXED_MAINPLL, 1, 8),
74 FACTOR0(CLK_TOP_MAINPLL_D16, CLK_APMIXED_MAINPLL, 1, 16),
75 FACTOR0(CLK_TOP_MAINPLL_D11, CLK_APMIXED_MAINPLL, 1, 11),
76 FACTOR0(CLK_TOP_MAINPLL_D22, CLK_APMIXED_MAINPLL, 1, 22),
77 FACTOR0(CLK_TOP_MAINPLL_D3, CLK_APMIXED_MAINPLL, 1, 3),
78 FACTOR0(CLK_TOP_MAINPLL_D6, CLK_APMIXED_MAINPLL, 1, 6),
79 FACTOR0(CLK_TOP_MAINPLL_D12, CLK_APMIXED_MAINPLL, 1, 12),
80 FACTOR0(CLK_TOP_MAINPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
81 FACTOR0(CLK_TOP_MAINPLL_D10, CLK_APMIXED_MAINPLL, 1, 10),
82 FACTOR0(CLK_TOP_MAINPLL_D20, CLK_APMIXED_MAINPLL, 1, 20),
83 FACTOR0(CLK_TOP_MAINPLL_D40, CLK_APMIXED_MAINPLL, 1, 40),
84 FACTOR0(CLK_TOP_MAINPLL_D7, CLK_APMIXED_MAINPLL, 1, 7),
85 FACTOR0(CLK_TOP_MAINPLL_D14, CLK_APMIXED_MAINPLL, 1, 14),
86 FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_APMIXED_UNIVPLL, 1, 2),
87 FACTOR0(CLK_TOP_UNIVPLL_D4, CLK_APMIXED_UNIVPLL, 1, 4),
88 FACTOR0(CLK_TOP_UNIVPLL_D8, CLK_APMIXED_UNIVPLL, 1, 8),
89 FACTOR0(CLK_TOP_UNIVPLL_D16, CLK_APMIXED_UNIVPLL, 1, 16),
90 FACTOR0(CLK_TOP_UNIVPLL_D3, CLK_APMIXED_UNIVPLL, 1, 3),
91 FACTOR0(CLK_TOP_UNIVPLL_D6, CLK_APMIXED_UNIVPLL, 1, 6),
92 FACTOR0(CLK_TOP_UNIVPLL_D12, CLK_APMIXED_UNIVPLL, 1, 12),
93 FACTOR0(CLK_TOP_UNIVPLL_D24, CLK_APMIXED_UNIVPLL, 1, 24),
94 FACTOR0(CLK_TOP_UNIVPLL_D5, CLK_APMIXED_UNIVPLL, 1, 5),
95 FACTOR0(CLK_TOP_UNIVPLL_D20, CLK_APMIXED_UNIVPLL, 1, 20),
96 FACTOR0(CLK_TOP_UNIVPLL_D10, CLK_APMIXED_UNIVPLL, 1, 10),
97 FACTOR0(CLK_TOP_MMPLL_D2, CLK_APMIXED_MMPLL, 1, 2),
98 FACTOR0(CLK_TOP_USB20_48M, CLK_APMIXED_UNIVPLL, 1, 26),
99 FACTOR0(CLK_TOP_APLL1, CLK_APMIXED_APLL1, 1, 1),
100 FACTOR1(CLK_TOP_APLL1_D4, CLK_TOP_APLL1, 1, 4),
101 FACTOR0(CLK_TOP_APLL2, CLK_APMIXED_APLL2, 1, 1),
102 FACTOR1(CLK_TOP_APLL2_D2, CLK_TOP_APLL2, 1, 2),
103 FACTOR1(CLK_TOP_APLL2_D3, CLK_TOP_APLL2, 1, 3),
104 FACTOR1(CLK_TOP_APLL2_D4, CLK_TOP_APLL2, 1, 4),
105 FACTOR1(CLK_TOP_APLL2_D8, CLK_TOP_APLL2, 1, 8),
106 FACTOR2(CLK_TOP_CLK26M, CLK_XTAL, 1, 1),
107 FACTOR2(CLK_TOP_CLK26M_D2, CLK_XTAL, 1, 2),
108 FACTOR2(CLK_TOP_CLK26M_D4, CLK_XTAL, 1, 4),
109 FACTOR2(CLK_TOP_CLK26M_D8, CLK_XTAL, 1, 8),
110 FACTOR2(CLK_TOP_CLK26M_D793, CLK_XTAL, 1, 793),
111 FACTOR0(CLK_TOP_TVDPLL, CLK_APMIXED_TVDPLL, 1, 1),
112 FACTOR1(CLK_TOP_TVDPLL_D2, CLK_TOP_TVDPLL, 1, 2),
113 FACTOR1(CLK_TOP_TVDPLL_D4, CLK_TOP_TVDPLL, 1, 4),
114 FACTOR1(CLK_TOP_TVDPLL_D8, CLK_TOP_TVDPLL, 1, 8),
115 FACTOR1(CLK_TOP_TVDPLL_D16, CLK_TOP_TVDPLL, 1, 16),
116 FACTOR1(CLK_TOP_USB20_CLK480M, CLK_TOP_CLK_NULL, 1, 1),
117 FACTOR1(CLK_TOP_RG_APLL1_D2, CLK_TOP_APLL1_SRC_SEL, 1, 2),
118 FACTOR1(CLK_TOP_RG_APLL1_D4, CLK_TOP_APLL1_SRC_SEL, 1, 4),
119 FACTOR1(CLK_TOP_RG_APLL1_D8, CLK_TOP_APLL1_SRC_SEL, 1, 8),
120 FACTOR1(CLK_TOP_RG_APLL1_D16, CLK_TOP_APLL1_SRC_SEL, 1, 16),
121 FACTOR1(CLK_TOP_RG_APLL1_D3, CLK_TOP_APLL1_SRC_SEL, 1, 3),
122 FACTOR1(CLK_TOP_RG_APLL2_D2, CLK_TOP_APLL2_SRC_SEL, 1, 2),
123 FACTOR1(CLK_TOP_RG_APLL2_D4, CLK_TOP_APLL2_SRC_SEL, 1, 4),
124 FACTOR1(CLK_TOP_RG_APLL2_D8, CLK_TOP_APLL2_SRC_SEL, 1, 8),
125 FACTOR1(CLK_TOP_RG_APLL2_D16, CLK_TOP_APLL2_SRC_SEL, 1, 16),
126 FACTOR1(CLK_TOP_RG_APLL2_D3, CLK_TOP_APLL2_SRC_SEL, 1, 3),
127 FACTOR1(CLK_TOP_NFI1X_INFRA_BCLK, CLK_TOP_NFI2X_SEL, 1, 2),
128 FACTOR1(CLK_TOP_AHB_INFRA_D2, CLK_TOP_AXIBUS_SEL, 1, 2),
131 static const int uart0_parents[] = {
136 static const int emi1x_parents[] = {
141 static const int emi_ddrphy_parents[] = {
146 static const int msdc1_parents[] = {
214 static const int pwm_mm_parents[] = {
219 static const int pmicspi_parents[] = {
227 static const int nfi2x_parents[] = {
238 static const int ddrphycfg_parents[] = {
243 static const int smi_parents[] = {
259 static const int usb_parents[] = {
267 static const int spinor_parents[] = {
278 static const int eth_parents[] = {
286 static const int aud1_parents[] = {
288 CLK_TOP_APLL1_SRC_SEL
291 static const int aud2_parents[] = {
293 CLK_TOP_APLL2_SRC_SEL
296 static const int i2c_parents[] = {
304 static const int aud_i2s0_m_parents[] = {
309 static const int aud_spdifin_parents[] = {
315 static const int dbg_atclk_parents[] = {
323 static const int png_sys_parents[] = {
332 static const int sej_13m_parents[] = {
337 static const int imgrz_sys_parents[] = {
348 static const int graph_eclk_parents[] = {
360 static const int fdbi_parents[] = {
375 static const int faudio_parents[] = {
382 static const int fa2sys_parents[] = {
384 CLK_TOP_APLL1_SRC_SEL,
388 CLK_TOP_RG_APLL1_D16,
393 static const int fa1sys_parents[] = {
395 CLK_TOP_APLL2_SRC_SEL,
399 CLK_TOP_RG_APLL2_D16,
404 static const int fasm_m_parents[] = {
411 static const int fecc_ck_parents[] = {
447 static const int pe2_mac_parents[] = {
455 static const int cmsys_parents[] = {
466 static const int gcpu_parents[] = {
477 static const int spis_ck_parents[] = {
609 static const int apll1_ref_parents[] = {
618 static const int int_32k_parents[] = {
623 static const int apll1_src_parents[] = {
630 static const int apll2_src_parents[] = {
637 static const int faud_intbus_parents[] = {
769 static const int axibus_parents[] = {
805 static const int hapll1_parents[] = {
807 CLK_TOP_APLL1_SRC_SEL,
811 CLK_TOP_RG_APLL1_D16,
817 static const int hapll2_parents[] = {
819 CLK_TOP_APLL2_SRC_SEL,
823 CLK_TOP_RG_APLL2_D16,
829 static const int spinfi_parents[] = {
841 static const int msdc0_parents[] = {
973 static const int msdc0_clk50_parents[] = {
1009 static const int msdc2_parents[] = {
1026 CLK_TOP_MAINPLL_D16,
1074 CLK_TOP_MAINPLL_D12,
1141 static const int disp_dpi_ck_parents[] = {
1177 static const struct mtk_composite top_muxes[] = {
1179 MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
1180 MUX(CLK_TOP_EMI1X_SEL, emi1x_parents, 0x000, 1, 1),
1181 MUX(CLK_TOP_EMI_DDRPHY_SEL, emi_ddrphy_parents, 0x000, 2, 1),
1182 MUX(CLK_TOP_MSDC1_SEL, msdc1_parents, 0x000, 4, 8),
1183 MUX(CLK_TOP_PWM_MM_SEL, pwm_mm_parents, 0x000, 18, 1),
1184 MUX(CLK_TOP_UART1_SEL, uart0_parents, 0x000, 19, 1),
1185 MUX(CLK_TOP_SPM_52M_SEL, uart0_parents, 0x000, 22, 1),
1186 MUX(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x000, 23, 3),
1188 MUX(CLK_TOP_NFI2X_SEL, nfi2x_parents, 0x004, 0, 3),
1189 MUX(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x004, 15, 1),
1190 MUX(CLK_TOP_SMI_SEL, smi_parents, 0x004, 16, 4),
1191 MUX(CLK_TOP_USB_SEL, usb_parents, 0x004, 20, 3),
1193 MUX(CLK_TOP_SPINOR_SEL, spinor_parents, 0x040, 0, 3),
1194 MUX(CLK_TOP_ETH_SEL, eth_parents, 0x040, 6, 3),
1195 MUX(CLK_TOP_AUD1_SEL, aud1_parents, 0x040, 22, 1),
1196 MUX(CLK_TOP_AUD2_SEL, aud2_parents, 0x040, 23, 1),
1197 MUX(CLK_TOP_I2C_SEL, i2c_parents, 0x040, 28, 3),
1199 MUX(CLK_TOP_AUD_I2S0_M_SEL, aud_i2s0_m_parents, 0x044, 12, 1),
1200 MUX(CLK_TOP_AUD_I2S3_M_SEL, aud_i2s0_m_parents, 0x044, 15, 1),
1201 MUX(CLK_TOP_AUD_I2S4_M_SEL, aud_i2s0_m_parents, 0x044, 16, 1),
1202 MUX(CLK_TOP_AUD_I2S6_M_SEL, aud_i2s0_m_parents, 0x044, 18, 1),
1204 MUX(CLK_TOP_PWM_SEL, pwm_mm_parents, 0x07c, 0, 1),
1205 MUX(CLK_TOP_AUD_SPDIFIN_SEL, aud_spdifin_parents, 0x07c, 2, 2),
1206 MUX(CLK_TOP_UART2_SEL, uart0_parents, 0x07c, 4, 1),
1207 MUX(CLK_TOP_DBG_ATCLK_SEL, dbg_atclk_parents, 0x07c, 7, 3),
1208 MUX(CLK_TOP_PNG_SYS_SEL, png_sys_parents, 0x07c, 16, 3),
1209 MUX(CLK_TOP_SEJ_13M_SEL, sej_13m_parents, 0x07c, 22, 1),
1211 MUX(CLK_TOP_IMGRZ_SYS_SEL, imgrz_sys_parents, 0xc0, 0, 3),
1212 MUX(CLK_TOP_GRAPH_ECLK_SEL, graph_eclk_parents, 0xc0, 8, 4),
1213 MUX(CLK_TOP_FDBI_SEL, fdbi_parents, 0xc0, 12, 4),
1214 MUX(CLK_TOP_FAUDIO_SEL, faudio_parents, 0xc0, 16, 2),
1215 MUX(CLK_TOP_FA2SYS_SEL, fa2sys_parents, 0xc0, 24, 3),
1216 MUX(CLK_TOP_FA1SYS_SEL, fa1sys_parents, 0xc0, 27, 3),
1217 MUX(CLK_TOP_FASM_M_SEL, fasm_m_parents, 0xc0, 30, 2),
1219 MUX(CLK_TOP_FASM_H_SEL, fasm_m_parents, 0xC4, 0, 2),
1220 MUX(CLK_TOP_FASM_L_SEL, fasm_m_parents, 0xC4, 2, 2),
1221 MUX(CLK_TOP_FECC_CK_SEL, fecc_ck_parents, 0xC4, 18, 6),
1222 MUX(CLK_TOP_PE2_MAC_SEL, pe2_mac_parents, 0xC4, 24, 3),
1223 MUX(CLK_TOP_CMSYS_SEL, cmsys_parents, 0xC4, 28, 3),
1225 MUX(CLK_TOP_GCPU_SEL, gcpu_parents, 0xC8, 0, 3),
1226 MUX(CLK_TOP_SPIS_CK_SEL, spis_ck_parents, 0xC8, 4, 8),
1228 MUX(CLK_TOP_APLL1_REF_SEL, apll1_ref_parents, 0xCC, 6, 3),
1229 MUX(CLK_TOP_APLL2_REF_SEL, apll1_ref_parents, 0xCC, 9, 3),
1230 MUX(CLK_TOP_INT_32K_SEL, int_32k_parents, 0xCC, 12, 1),
1231 MUX(CLK_TOP_APLL1_SRC_SEL, apll1_src_parents, 0xCC, 13, 2),
1232 MUX(CLK_TOP_APLL2_SRC_SEL, apll2_src_parents, 0xCC, 15, 2),
1234 MUX(CLK_TOP_FAUD_INTBUS_SEL, faud_intbus_parents, 0xD4, 8, 8),
1235 MUX(CLK_TOP_AXIBUS_SEL, axibus_parents, 0xD4, 24, 8),
1237 MUX(CLK_TOP_HAPLL1_SEL, hapll1_parents, 0xDC, 0, 4),
1238 MUX(CLK_TOP_HAPLL2_SEL, hapll2_parents, 0xDC, 4, 4),
1239 MUX(CLK_TOP_SPINFI_SEL, spinfi_parents, 0xDC, 8, 4),
1241 MUX(CLK_TOP_MSDC0_SEL, msdc0_parents, 0xF4, 0, 8),
1242 MUX(CLK_TOP_MSDC0_CLK50_SEL, msdc0_clk50_parents, 0xF4, 8, 6),
1243 MUX(CLK_TOP_MSDC2_SEL, msdc2_parents, 0xF4, 15, 8),
1244 MUX(CLK_TOP_MSDC2_CLK50_SEL, msdc0_clk50_parents, 0xF4, 23, 6),
1246 MUX(CLK_TOP_DISP_DPI_CK_SEL, disp_dpi_ck_parents, 0xF8, 0, 6),
1247 MUX(CLK_TOP_SPI1_SEL, spis_ck_parents, 0xF8, 6, 8),
1248 MUX(CLK_TOP_SPI2_SEL, spis_ck_parents, 0xF8, 14, 8),
1249 MUX(CLK_TOP_SPI3_SEL, spis_ck_parents, 0xF8, 22, 8),
1252 static const struct mtk_gate_regs top0_cg_regs = {
1258 static const struct mtk_gate_regs top1_cg_regs = {
1264 static const struct mtk_gate_regs top2_cg_regs = {
1270 static const struct mtk_gate_regs top3_cg_regs = {
1276 static const struct mtk_gate_regs top4_cg_regs = {
1282 static const struct mtk_gate_regs top5_cg_regs = {
1288 static const struct mtk_gate_regs top6_cg_regs = {
1294 static const struct mtk_gate_regs top7_cg_regs = {
1300 #define GATE_TOP0(_id, _parent, _shift) { \
1302 .parent = _parent, \
1303 .regs = &top0_cg_regs, \
1305 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
1308 #define GATE_TOP1(_id, _parent, _shift) { \
1310 .parent = _parent, \
1311 .regs = &top1_cg_regs, \
1313 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
1316 #define GATE_TOP2(_id, _parent, _shift) { \
1318 .parent = _parent, \
1319 .regs = &top2_cg_regs, \
1321 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
1324 #define GATE_TOP2_I(_id, _parent, _shift) { \
1326 .parent = _parent, \
1327 .regs = &top2_cg_regs, \
1329 .flags = CLK_GATE_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
1332 #define GATE_TOP3(_id, _parent, _shift) { \
1334 .parent = _parent, \
1335 .regs = &top3_cg_regs, \
1337 .flags = CLK_GATE_NO_SETCLR | CLK_PARENT_TOPCKGEN, \
1340 #define GATE_TOP4(_id, _parent, _shift) { \
1342 .parent = _parent, \
1343 .regs = &top4_cg_regs, \
1345 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
1348 #define GATE_TOP5(_id, _parent, _shift) { \
1350 .parent = _parent, \
1351 .regs = &top5_cg_regs, \
1353 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
1356 #define GATE_TOP5_I(_id, _parent, _shift) { \
1358 .parent = _parent, \
1359 .regs = &top5_cg_regs, \
1361 .flags = CLK_GATE_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
1364 #define GATE_TOP6(_id, _parent, _shift) { \
1366 .parent = _parent, \
1367 .regs = &top6_cg_regs, \
1369 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
1372 #define GATE_TOP7(_id, _parent, _shift) { \
1374 .parent = _parent, \
1375 .regs = &top7_cg_regs, \
1377 .flags = CLK_GATE_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
1380 static const struct mtk_gate top_clks[] = {
1382 GATE_TOP0(CLK_TOP_PWM_MM, CLK_TOP_PWM_MM_SEL, 0),
1383 GATE_TOP0(CLK_TOP_SMI, CLK_TOP_SMI_SEL, 9),
1384 GATE_TOP0(CLK_TOP_SPI2, CLK_TOP_SPI2_SEL, 10),
1385 GATE_TOP0(CLK_TOP_SPI3, CLK_TOP_SPI3_SEL, 11),
1386 GATE_TOP0(CLK_TOP_SPINFI, CLK_TOP_SPINFI_SEL, 12),
1387 GATE_TOP0(CLK_TOP_26M_DEBUG, CLK_TOP_CLK26M, 16),
1388 GATE_TOP0(CLK_TOP_USB_48M_DEBUG, CLK_TOP_USB20_48M, 17),
1389 GATE_TOP0(CLK_TOP_52M_DEBUG, CLK_TOP_UNIVPLL_D24, 18),
1390 GATE_TOP0(CLK_TOP_32K_DEBUG, CLK_TOP_INT_32K_SEL, 19),
1392 GATE_TOP1(CLK_TOP_THERM, CLK_TOP_AXIBUS_SEL, 1),
1393 GATE_TOP1(CLK_TOP_APDMA, CLK_TOP_AXIBUS_SEL, 2),
1394 GATE_TOP1(CLK_TOP_I2C0, CLK_TOP_AHB_INFRA_D2, 3),
1395 GATE_TOP1(CLK_TOP_I2C1, CLK_TOP_AHB_INFRA_D2, 4),
1396 GATE_TOP1(CLK_TOP_AUXADC1, CLK_TOP_CLK26M, 5),
1397 GATE_TOP1(CLK_TOP_NFI, CLK_TOP_NFI1X_INFRA_BCLK, 6),
1398 GATE_TOP1(CLK_TOP_NFIECC, CLK_TOP_AXIBUS_SEL, 7),
1399 GATE_TOP1(CLK_TOP_DEBUGSYS, CLK_TOP_DBG_ATCLK_SEL, 8),
1400 GATE_TOP1(CLK_TOP_PWM, CLK_TOP_AXIBUS_SEL, 9),
1401 GATE_TOP1(CLK_TOP_UART0, CLK_TOP_UART0_SEL, 10),
1402 GATE_TOP1(CLK_TOP_UART1, CLK_TOP_UART1_SEL, 11),
1403 GATE_TOP1(CLK_TOP_USB, CLK_TOP_USB_B, 13),
1404 GATE_TOP1(CLK_TOP_FLASHIF_26M, CLK_TOP_CLK26M, 14),
1405 GATE_TOP1(CLK_TOP_AUXADC2, CLK_TOP_CLK26M, 15),
1406 GATE_TOP1(CLK_TOP_I2C2, CLK_TOP_AHB_INFRA_D2, 16),
1407 GATE_TOP1(CLK_TOP_MSDC0, CLK_TOP_MSDC0_SEL, 17),
1408 GATE_TOP1(CLK_TOP_MSDC1, CLK_TOP_MSDC1_SEL, 18),
1409 GATE_TOP1(CLK_TOP_NFI2X, CLK_TOP_NFI2X_SEL, 19),
1410 GATE_TOP1(CLK_TOP_MEMSLP_DLYER, CLK_TOP_CLK26M, 22),
1411 GATE_TOP1(CLK_TOP_SPI, CLK_TOP_SPI1_SEL, 23),
1412 GATE_TOP1(CLK_TOP_APXGPT, CLK_TOP_CLK26M, 24),
1413 GATE_TOP1(CLK_TOP_PMICWRAP_MD, CLK_TOP_CLK26M, 27),
1414 GATE_TOP1(CLK_TOP_PMICWRAP_CONN, CLK_TOP_PMICSPI_SEL, 28),
1415 GATE_TOP1(CLK_TOP_PMIC_SYSCK, CLK_TOP_CLK26M, 29),
1416 GATE_TOP1(CLK_TOP_AUX_ADC, CLK_TOP_CLK26M, 30),
1417 GATE_TOP1(CLK_TOP_AUX_TP, CLK_TOP_CLK26M, 31),
1419 GATE_TOP2(CLK_TOP_RBIST, CLK_TOP_UNIVPLL_D12, 1),
1420 GATE_TOP2(CLK_TOP_NFI_BUS, CLK_TOP_AXIBUS_SEL, 2),
1421 GATE_TOP2(CLK_TOP_GCE, CLK_TOP_AXIBUS_SEL, 4),
1422 GATE_TOP2(CLK_TOP_TRNG, CLK_TOP_AXIBUS_SEL, 5),
1423 GATE_TOP2(CLK_TOP_PWM_B, CLK_TOP_PWM_SEL, 8),
1424 GATE_TOP2(CLK_TOP_PWM1_FB, CLK_TOP_PWM_SEL, 9),
1425 GATE_TOP2(CLK_TOP_PWM2_FB, CLK_TOP_PWM_SEL, 10),
1426 GATE_TOP2(CLK_TOP_PWM3_FB, CLK_TOP_PWM_SEL, 11),
1427 GATE_TOP2(CLK_TOP_PWM4_FB, CLK_TOP_PWM_SEL, 12),
1428 GATE_TOP2(CLK_TOP_PWM5_FB, CLK_TOP_PWM_SEL, 13),
1429 GATE_TOP2(CLK_TOP_FLASHIF_FREERUN, CLK_TOP_AXIBUS_SEL, 15),
1430 GATE_TOP2(CLK_TOP_CQDMA, CLK_TOP_AXIBUS_SEL, 17),
1431 GATE_TOP2(CLK_TOP_66M_ETH, CLK_TOP_AXIBUS_SEL, 19),
1432 GATE_TOP2(CLK_TOP_133M_ETH, CLK_TOP_AXIBUS_SEL, 20),
1433 GATE_TOP2(CLK_TOP_FLASHIF_AXI, CLK_TOP_SPI1_SEL, 23),
1434 GATE_TOP2(CLK_TOP_USBIF, CLK_TOP_AXIBUS_SEL, 24),
1435 GATE_TOP2(CLK_TOP_UART2, CLK_TOP_RG_UART2, 25),
1436 GATE_TOP2(CLK_TOP_GCPU_B, CLK_TOP_AXIBUS_SEL, 27),
1437 GATE_TOP2_I(CLK_TOP_MSDC0_B, CLK_TOP_MSDC0, 28),
1438 GATE_TOP2_I(CLK_TOP_MSDC1_B, CLK_TOP_MSDC1, 29),
1439 GATE_TOP2_I(CLK_TOP_MSDC2_B, CLK_TOP_MSDC2, 30),
1440 GATE_TOP2(CLK_TOP_USB_B, CLK_TOP_USB_SEL, 31),
1442 GATE_TOP3(CLK_TOP_APLL12_DIV0, CLK_TOP_APLL12_CK_DIV0, 0),
1443 GATE_TOP3(CLK_TOP_APLL12_DIV3, CLK_TOP_APLL12_CK_DIV3, 3),
1444 GATE_TOP3(CLK_TOP_APLL12_DIV4, CLK_TOP_APLL12_CK_DIV4, 4),
1445 GATE_TOP3(CLK_TOP_APLL12_DIV6, CLK_TOP_APLL12_CK_DIV6, 8),
1447 GATE_TOP4(CLK_TOP_SPINOR, CLK_TOP_SPINOR_SEL, 0),
1448 GATE_TOP4(CLK_TOP_MSDC2, CLK_TOP_MSDC2_SEL, 1),
1449 GATE_TOP4(CLK_TOP_ETH, CLK_TOP_ETH_SEL, 2),
1450 GATE_TOP4(CLK_TOP_AUD1, CLK_TOP_AUD1_SEL, 8),
1451 GATE_TOP4(CLK_TOP_AUD2, CLK_TOP_AUD2_SEL, 9),
1452 GATE_TOP4(CLK_TOP_I2C, CLK_TOP_I2C_SEL, 12),
1453 GATE_TOP4(CLK_TOP_PWM_INFRA, CLK_TOP_PWM_SEL, 13),
1454 GATE_TOP4(CLK_TOP_AUD_SPDIF_IN, CLK_TOP_AUD_SPDIFIN_SEL, 14),
1455 GATE_TOP4(CLK_TOP_RG_UART2, CLK_TOP_UART2_SEL, 15),
1456 GATE_TOP4(CLK_TOP_DBG_AT, CLK_TOP_DBG_ATCLK_SEL, 17),
1458 GATE_TOP5_I(CLK_TOP_IMGRZ_SYS, CLK_TOP_IMGRZ_SYS_SEL, 0),
1459 GATE_TOP5_I(CLK_TOP_PNG_SYS, CLK_TOP_PNG_SYS_SEL, 1),
1460 GATE_TOP5_I(CLK_TOP_GRAPH_E, CLK_TOP_GRAPH_ECLK_SEL, 2),
1461 GATE_TOP5_I(CLK_TOP_FDBI, CLK_TOP_FDBI_SEL, 3),
1462 GATE_TOP5_I(CLK_TOP_FAUDIO, CLK_TOP_FAUDIO_SEL, 4),
1463 GATE_TOP5_I(CLK_TOP_FAUD_INTBUS, CLK_TOP_FAUD_INTBUS_SEL, 5),
1464 GATE_TOP5_I(CLK_TOP_HAPLL1, CLK_TOP_HAPLL1_SEL, 6),
1465 GATE_TOP5_I(CLK_TOP_HAPLL2, CLK_TOP_HAPLL2_SEL, 7),
1466 GATE_TOP5_I(CLK_TOP_FA2SYS, CLK_TOP_FA2SYS_SEL, 8),
1467 GATE_TOP5_I(CLK_TOP_FA1SYS, CLK_TOP_FA1SYS_SEL, 9),
1468 GATE_TOP5_I(CLK_TOP_FASM_L, CLK_TOP_FASM_L_SEL, 10),
1469 GATE_TOP5_I(CLK_TOP_FASM_M, CLK_TOP_FASM_M_SEL, 11),
1470 GATE_TOP5_I(CLK_TOP_FASM_H, CLK_TOP_FASM_H_SEL, 12),
1471 GATE_TOP5_I(CLK_TOP_FECC, CLK_TOP_FECC_CK_SEL, 23),
1472 GATE_TOP5_I(CLK_TOP_PE2_MAC, CLK_TOP_PE2_MAC_SEL, 24),
1473 GATE_TOP5_I(CLK_TOP_CMSYS, CLK_TOP_CMSYS_SEL, 25),
1474 GATE_TOP5_I(CLK_TOP_GCPU, CLK_TOP_GCPU_SEL, 26),
1475 GATE_TOP5(CLK_TOP_SPIS, CLK_TOP_SPIS_CK_SEL, 27),
1477 GATE_TOP6(CLK_TOP_I2C3, CLK_TOP_AHB_INFRA_D2, 0),
1478 GATE_TOP6(CLK_TOP_SPI_SLV_B, CLK_TOP_SPIS_CK_SEL, 1),
1479 GATE_TOP6(CLK_TOP_SPI_SLV_BUS, CLK_TOP_AXIBUS_SEL, 2),
1480 GATE_TOP6(CLK_TOP_PCIE_MAC_BUS, CLK_TOP_AXIBUS_SEL, 3),
1481 GATE_TOP6(CLK_TOP_CMSYS_BUS, CLK_TOP_AXIBUS_SEL, 4),
1482 GATE_TOP6(CLK_TOP_ECC_B, CLK_TOP_AXIBUS_SEL, 5),
1483 GATE_TOP6(CLK_TOP_PCIE_PHY_BUS, CLK_TOP_CLK26M, 6),
1484 GATE_TOP6(CLK_TOP_PCIE_AUX, CLK_TOP_CLK26M, 7),
1486 GATE_TOP7(CLK_TOP_DISP_DPI, CLK_TOP_DISP_DPI_CK_SEL, 0),
1489 static const struct mtk_clk_tree mt8518_clk_tree = {
1490 .xtal_rate = 26 * MHZ,
1491 .xtal2_rate = 26 * MHZ,
1492 .fdivs_offs = CLK_TOP_DMPLL,
1493 .muxes_offs = CLK_TOP_UART0_SEL,
1494 .plls = apmixed_plls,
1495 .fclks = top_fixed_clks,
1496 .fdivs = top_fixed_divs,
1500 static int mt8518_apmixedsys_probe(struct udevice *dev)
1502 return mtk_common_clk_init(dev, &mt8518_clk_tree);
1505 static int mt8518_topckgen_probe(struct udevice *dev)
1507 return mtk_common_clk_init(dev, &mt8518_clk_tree);
1510 static int mt8518_topckgen_cg_probe(struct udevice *dev)
1512 return mtk_common_clk_gate_init(dev, &mt8518_clk_tree, top_clks);
1515 static const struct udevice_id mt8518_apmixed_compat[] = {
1516 { .compatible = "mediatek,mt8518-apmixedsys", },
1520 static const struct udevice_id mt8518_topckgen_compat[] = {
1521 { .compatible = "mediatek,mt8518-topckgen", },
1525 static const struct udevice_id mt8518_topckgen_cg_compat[] = {
1526 { .compatible = "mediatek,mt8518-topckgen-cg", },
1530 U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
1531 .name = "mt8518-apmixedsys",
1533 .of_match = mt8518_apmixed_compat,
1534 .probe = mt8518_apmixedsys_probe,
1535 .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
1536 .ops = &mtk_clk_apmixedsys_ops,
1537 .flags = DM_FLAG_PRE_RELOC,
1540 U_BOOT_DRIVER(mtk_clk_topckgen) = {
1541 .name = "mt8518-topckgen",
1543 .of_match = mt8518_topckgen_compat,
1544 .probe = mt8518_topckgen_probe,
1545 .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
1546 .ops = &mtk_clk_topckgen_ops,
1547 .flags = DM_FLAG_PRE_RELOC,
1550 U_BOOT_DRIVER(mtk_clk_topckgen_cg) = {
1551 .name = "mt8518-topckgen-cg",
1553 .of_match = mt8518_topckgen_cg_compat,
1554 .probe = mt8518_topckgen_cg_probe,
1555 .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
1556 .ops = &mtk_clk_gate_ops,
1557 .flags = DM_FLAG_PRE_RELOC,