drivers/clk/mediatek/clk-mt8518.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * MediaTek clock driver for MT8518 SoC
   4  *
   5  * Copyright (C) 2019 BayLibre, SAS
   6  * Author: Chen Zhong <chen.zhong@mediatek.com>
   7  */
   8
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <asm/io.h>
  12 #include <dt-bindings/clock/mt8518-clk.h>
  13
  14 #include "clk-mtk.h"
  15
  16 #define MT8518_PLL_FMAX         (3000UL * MHZ)
  17 #define MT8518_CON0_RST_BAR     BIT(27)
  18
  19 /* apmixedsys */
  20 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg,   \
  21             _pd_shift, _pcw_reg, _pcw_shift) {                          \
  22                 .id = _id,                                              \
  23                 .reg = _reg,                                            \
  24                 .pwr_reg = _pwr_reg,                                    \
  25                 .en_mask = _en_mask,                                    \
  26                 .rst_bar_mask = MT8518_CON0_RST_BAR,                    \
  27                 .fmax = MT8518_PLL_FMAX,                                \
  28                 .flags = _flags,                                        \
  29                 .pcwbits = _pcwbits,                                    \
  30                 .pd_reg = _pd_reg,                                      \
  31                 .pd_shift = _pd_shift,                                  \
  32                 .pcw_reg = _pcw_reg,                                    \
  33                 .pcw_shift = _pcw_shift,                                \
  34         }
  35
  36 static const struct mtk_pll_data apmixed_plls[] = {
  37         PLL(CLK_APMIXED_ARMPLL, 0x0100, 0x0110, 0x00000001,
  38             0, 21, 0x0104, 24, 0x0104, 0),
  39         PLL(CLK_APMIXED_MAINPLL, 0x0120, 0x0130, 0x00000001,
  40             HAVE_RST_BAR, 21, 0x0124, 24, 0x0124, 0),
  41         PLL(CLK_APMIXED_UNIVPLL, 0x0140, 0x0150, 0x30000001,
  42             HAVE_RST_BAR, 7, 0x0144, 24, 0x0144, 0),
  43         PLL(CLK_APMIXED_MMPLL, 0x0160, 0x0170, 0x00000001,
  44             0, 21, 0x0164, 24, 0x0164, 0),
  45         PLL(CLK_APMIXED_APLL1, 0x0180, 0x0190, 0x00000001,
  46             0, 31, 0x0180, 1, 0x0184, 0),
  47         PLL(CLK_APMIXED_APLL2, 0x01A0, 0x01B0, 0x00000001,
  48             0, 31, 0x01A0, 1, 0x01A4, 0),
  49         PLL(CLK_APMIXED_TVDPLL, 0x01C0, 0x01D0, 0x00000001,
  50             0, 21, 0x01C4, 24, 0x01C4, 0),
  51 };
  52
  53 /* topckgen */
  54 #define FACTOR0(_id, _parent, _mult, _div)      \
  55         FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
  56
  57 #define FACTOR1(_id, _parent, _mult, _div)      \
  58         FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
  59
  60 #define FACTOR2(_id, _parent, _mult, _div)      \
  61         FACTOR(_id, _parent, _mult, _div, 0)
  62
  63 static const struct mtk_fixed_clk top_fixed_clks[] = {
  64         FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 26000000),
  65         FIXED_CLK(CLK_TOP_FQ_TRNG_OUT0, CLK_TOP_CLK_NULL, 500000000),
  66         FIXED_CLK(CLK_TOP_FQ_TRNG_OUT1, CLK_TOP_CLK_NULL, 500000000),
  67         FIXED_CLK(CLK_TOP_CLK32K, CLK_XTAL, 32000),
  68 };
  69
  70 static const struct mtk_fixed_factor top_fixed_divs[] = {
  71         FACTOR2(CLK_TOP_DMPLL, CLK_XTAL, 1, 1),
  72         FACTOR0(CLK_TOP_MAINPLL_D4, CLK_APMIXED_MAINPLL, 1, 4),
  73         FACTOR0(CLK_TOP_MAINPLL_D8, CLK_APMIXED_MAINPLL, 1, 8),
  74         FACTOR0(CLK_TOP_MAINPLL_D16, CLK_APMIXED_MAINPLL, 1, 16),
  75         FACTOR0(CLK_TOP_MAINPLL_D11, CLK_APMIXED_MAINPLL, 1, 11),
  76         FACTOR0(CLK_TOP_MAINPLL_D22, CLK_APMIXED_MAINPLL, 1, 22),
  77         FACTOR0(CLK_TOP_MAINPLL_D3, CLK_APMIXED_MAINPLL, 1, 3),
  78         FACTOR0(CLK_TOP_MAINPLL_D6, CLK_APMIXED_MAINPLL, 1, 6),
  79         FACTOR0(CLK_TOP_MAINPLL_D12, CLK_APMIXED_MAINPLL, 1, 12),
  80         FACTOR0(CLK_TOP_MAINPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
  81         FACTOR0(CLK_TOP_MAINPLL_D10, CLK_APMIXED_MAINPLL, 1, 10),
  82         FACTOR0(CLK_TOP_MAINPLL_D20, CLK_APMIXED_MAINPLL, 1, 20),
  83         FACTOR0(CLK_TOP_MAINPLL_D40, CLK_APMIXED_MAINPLL, 1, 40),
  84         FACTOR0(CLK_TOP_MAINPLL_D7, CLK_APMIXED_MAINPLL, 1, 7),
  85         FACTOR0(CLK_TOP_MAINPLL_D14, CLK_APMIXED_MAINPLL, 1, 14),
  86         FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_APMIXED_UNIVPLL, 1, 2),
  87         FACTOR0(CLK_TOP_UNIVPLL_D4, CLK_APMIXED_UNIVPLL, 1, 4),
  88         FACTOR0(CLK_TOP_UNIVPLL_D8, CLK_APMIXED_UNIVPLL, 1, 8),
  89         FACTOR0(CLK_TOP_UNIVPLL_D16, CLK_APMIXED_UNIVPLL, 1, 16),
  90         FACTOR0(CLK_TOP_UNIVPLL_D3, CLK_APMIXED_UNIVPLL, 1, 3),
  91         FACTOR0(CLK_TOP_UNIVPLL_D6, CLK_APMIXED_UNIVPLL, 1, 6),
  92         FACTOR0(CLK_TOP_UNIVPLL_D12, CLK_APMIXED_UNIVPLL, 1, 12),
  93         FACTOR0(CLK_TOP_UNIVPLL_D24, CLK_APMIXED_UNIVPLL, 1, 24),
  94         FACTOR0(CLK_TOP_UNIVPLL_D5, CLK_APMIXED_UNIVPLL, 1, 5),
  95         FACTOR0(CLK_TOP_UNIVPLL_D20, CLK_APMIXED_UNIVPLL, 1, 20),
  96         FACTOR0(CLK_TOP_UNIVPLL_D10, CLK_APMIXED_UNIVPLL, 1, 10),
  97         FACTOR0(CLK_TOP_MMPLL_D2, CLK_APMIXED_MMPLL, 1, 2),
  98         FACTOR0(CLK_TOP_USB20_48M, CLK_APMIXED_UNIVPLL, 1, 26),
  99         FACTOR0(CLK_TOP_APLL1, CLK_APMIXED_APLL1, 1, 1),
 100         FACTOR1(CLK_TOP_APLL1_D4, CLK_TOP_APLL1, 1, 4),
 101         FACTOR0(CLK_TOP_APLL2, CLK_APMIXED_APLL2, 1, 1),
 102         FACTOR1(CLK_TOP_APLL2_D2, CLK_TOP_APLL2, 1, 2),
 103         FACTOR1(CLK_TOP_APLL2_D3, CLK_TOP_APLL2, 1, 3),
 104         FACTOR1(CLK_TOP_APLL2_D4, CLK_TOP_APLL2, 1, 4),
 105         FACTOR1(CLK_TOP_APLL2_D8, CLK_TOP_APLL2, 1, 8),
 106         FACTOR2(CLK_TOP_CLK26M, CLK_XTAL, 1, 1),
 107         FACTOR2(CLK_TOP_CLK26M_D2, CLK_XTAL, 1, 2),
 108         FACTOR2(CLK_TOP_CLK26M_D4, CLK_XTAL, 1, 4),
 109         FACTOR2(CLK_TOP_CLK26M_D8, CLK_XTAL, 1, 8),
 110         FACTOR2(CLK_TOP_CLK26M_D793, CLK_XTAL, 1, 793),
 111         FACTOR0(CLK_TOP_TVDPLL, CLK_APMIXED_TVDPLL, 1, 1),
 112         FACTOR1(CLK_TOP_TVDPLL_D2, CLK_TOP_TVDPLL, 1, 2),
 113         FACTOR1(CLK_TOP_TVDPLL_D4, CLK_TOP_TVDPLL, 1, 4),
 114         FACTOR1(CLK_TOP_TVDPLL_D8, CLK_TOP_TVDPLL, 1, 8),
 115         FACTOR1(CLK_TOP_TVDPLL_D16, CLK_TOP_TVDPLL, 1, 16),
 116         FACTOR1(CLK_TOP_USB20_CLK480M, CLK_TOP_CLK_NULL, 1, 1),
 117         FACTOR1(CLK_TOP_RG_APLL1_D2, CLK_TOP_APLL1_SRC_SEL, 1, 2),
 118         FACTOR1(CLK_TOP_RG_APLL1_D4, CLK_TOP_APLL1_SRC_SEL, 1, 4),
 119         FACTOR1(CLK_TOP_RG_APLL1_D8, CLK_TOP_APLL1_SRC_SEL, 1, 8),
 120         FACTOR1(CLK_TOP_RG_APLL1_D16, CLK_TOP_APLL1_SRC_SEL, 1, 16),
 121         FACTOR1(CLK_TOP_RG_APLL1_D3, CLK_TOP_APLL1_SRC_SEL, 1, 3),
 122         FACTOR1(CLK_TOP_RG_APLL2_D2, CLK_TOP_APLL2_SRC_SEL, 1, 2),
 123         FACTOR1(CLK_TOP_RG_APLL2_D4, CLK_TOP_APLL2_SRC_SEL, 1, 4),
 124         FACTOR1(CLK_TOP_RG_APLL2_D8, CLK_TOP_APLL2_SRC_SEL, 1, 8),
 125         FACTOR1(CLK_TOP_RG_APLL2_D16, CLK_TOP_APLL2_SRC_SEL, 1, 16),
 126         FACTOR1(CLK_TOP_RG_APLL2_D3, CLK_TOP_APLL2_SRC_SEL, 1, 3),
 127         FACTOR1(CLK_TOP_NFI1X_INFRA_BCLK, CLK_TOP_NFI2X_SEL, 1, 2),
 128         FACTOR1(CLK_TOP_AHB_INFRA_D2, CLK_TOP_AXIBUS_SEL, 1, 2),
 129 };
 130
 131 static const int uart0_parents[] = {
 132         CLK_TOP_CLK26M,
 133         CLK_TOP_UNIVPLL_D24
 134 };
 135
 136 static const int emi1x_parents[] = {
 137         CLK_TOP_CLK26M,
 138         CLK_TOP_DMPLL
 139 };
 140
 141 static const int emi_ddrphy_parents[] = {
 142         CLK_TOP_EMI1X_SEL,
 143         CLK_TOP_EMI1X_SEL
 144 };
 145
 146 static const int msdc1_parents[] = {
 147         CLK_TOP_CLK_NULL,
 148         CLK_TOP_CLK26M,
 149         CLK_TOP_UNIVPLL_D6,
 150         CLK_TOP_CLK_NULL,
 151         CLK_TOP_MAINPLL_D8,
 152         CLK_TOP_CLK_NULL,
 153         CLK_TOP_CLK_NULL,
 154         CLK_TOP_CLK_NULL,
 155         CLK_TOP_UNIVPLL_D8,
 156         CLK_TOP_CLK_NULL,
 157         CLK_TOP_CLK_NULL,
 158         CLK_TOP_CLK_NULL,
 159         CLK_TOP_CLK_NULL,
 160         CLK_TOP_CLK_NULL,
 161         CLK_TOP_CLK_NULL,
 162         CLK_TOP_CLK_NULL,
 163         CLK_TOP_MAINPLL_D16,
 164         CLK_TOP_CLK_NULL,
 165         CLK_TOP_CLK_NULL,
 166         CLK_TOP_CLK_NULL,
 167         CLK_TOP_CLK_NULL,
 168         CLK_TOP_CLK_NULL,
 169         CLK_TOP_CLK_NULL,
 170         CLK_TOP_CLK_NULL,
 171         CLK_TOP_CLK_NULL,
 172         CLK_TOP_CLK_NULL,
 173         CLK_TOP_CLK_NULL,
 174         CLK_TOP_CLK_NULL,
 175         CLK_TOP_CLK_NULL,
 176         CLK_TOP_CLK_NULL,
 177         CLK_TOP_CLK_NULL,
 178         CLK_TOP_CLK_NULL,
 179         CLK_TOP_MMPLL_D2,
 180         CLK_TOP_CLK_NULL,
 181         CLK_TOP_CLK_NULL,
 182         CLK_TOP_CLK_NULL,
 183         CLK_TOP_CLK_NULL,
 184         CLK_TOP_CLK_NULL,
 185         CLK_TOP_CLK_NULL,
 186         CLK_TOP_CLK_NULL,
 187         CLK_TOP_CLK_NULL,
 188         CLK_TOP_CLK_NULL,
 189         CLK_TOP_CLK_NULL,
 190         CLK_TOP_CLK_NULL,
 191         CLK_TOP_CLK_NULL,
 192         CLK_TOP_CLK_NULL,
 193         CLK_TOP_CLK_NULL,
 194         CLK_TOP_CLK_NULL,
 195         CLK_TOP_CLK_NULL,
 196         CLK_TOP_CLK_NULL,
 197         CLK_TOP_CLK_NULL,
 198         CLK_TOP_CLK_NULL,
 199         CLK_TOP_CLK_NULL,
 200         CLK_TOP_CLK_NULL,
 201         CLK_TOP_CLK_NULL,
 202         CLK_TOP_CLK_NULL,
 203         CLK_TOP_CLK_NULL,
 204         CLK_TOP_CLK_NULL,
 205         CLK_TOP_CLK_NULL,
 206         CLK_TOP_CLK_NULL,
 207         CLK_TOP_CLK_NULL,
 208         CLK_TOP_CLK_NULL,
 209         CLK_TOP_CLK_NULL,
 210         CLK_TOP_CLK_NULL,
 211         CLK_TOP_MAINPLL_D12
 212 };
 213
 214 static const int pwm_mm_parents[] = {
 215         CLK_TOP_CLK26M,
 216         CLK_TOP_UNIVPLL_D12
 217 };
 218
 219 static const int pmicspi_parents[] = {
 220         CLK_TOP_UNIVPLL_D20,
 221         CLK_TOP_USB20_48M,
 222         CLK_TOP_UNIVPLL_D16,
 223         CLK_TOP_CLK26M,
 224         CLK_TOP_CLK26M_D2
 225 };
 226
 227 static const int nfi2x_parents[] = {
 228         CLK_TOP_CLK26M,
 229         CLK_TOP_MAINPLL_D4,
 230         CLK_TOP_MAINPLL_D5,
 231         CLK_TOP_MAINPLL_D6,
 232         CLK_TOP_MAINPLL_D7,
 233         CLK_TOP_MAINPLL_D8,
 234         CLK_TOP_MAINPLL_D10,
 235         CLK_TOP_MAINPLL_D12
 236 };
 237
 238 static const int ddrphycfg_parents[] = {
 239         CLK_TOP_CLK26M,
 240         CLK_TOP_MAINPLL_D16
 241 };
 242
 243 static const int smi_parents[] = {
 244         CLK_TOP_CLK_NULL,
 245         CLK_TOP_CLK26M,
 246         CLK_TOP_CLK_NULL,
 247         CLK_TOP_CLK_NULL,
 248         CLK_TOP_CLK_NULL,
 249         CLK_TOP_CLK_NULL,
 250         CLK_TOP_CLK_NULL,
 251         CLK_TOP_CLK_NULL,
 252         CLK_TOP_CLK_NULL,
 253         CLK_TOP_UNIVPLL_D4,
 254         CLK_TOP_MAINPLL_D7,
 255         CLK_TOP_CLK_NULL,
 256         CLK_TOP_MAINPLL_D14
 257 };
 258
 259 static const int usb_parents[] = {
 260         CLK_TOP_CLK_NULL,
 261         CLK_TOP_CLK26M,
 262         CLK_TOP_UNIVPLL_D16,
 263         CLK_TOP_CLK_NULL,
 264         CLK_TOP_MAINPLL_D20
 265 };
 266
 267 static const int spinor_parents[] = {
 268         CLK_TOP_CLK26M_D2,
 269         CLK_TOP_CLK26M,
 270         CLK_TOP_MAINPLL_D40,
 271         CLK_TOP_UNIVPLL_D24,
 272         CLK_TOP_UNIVPLL_D20,
 273         CLK_TOP_MAINPLL_D20,
 274         CLK_TOP_MAINPLL_D16,
 275         CLK_TOP_UNIVPLL_D12
 276 };
 277
 278 static const int eth_parents[] = {
 279         CLK_TOP_CLK26M,
 280         CLK_TOP_MAINPLL_D40,
 281         CLK_TOP_UNIVPLL_D24,
 282         CLK_TOP_UNIVPLL_D20,
 283         CLK_TOP_MAINPLL_D20
 284 };
 285
 286 static const int aud1_parents[] = {
 287         CLK_TOP_CLK26M,
 288         CLK_TOP_APLL1_SRC_SEL
 289 };
 290
 291 static const int aud2_parents[] = {
 292         CLK_TOP_CLK26M,
 293         CLK_TOP_APLL2_SRC_SEL
 294 };
 295
 296 static const int i2c_parents[] = {
 297         CLK_TOP_CLK26M,
 298         CLK_TOP_USB20_48M,
 299         CLK_TOP_UNIVPLL_D12,
 300         CLK_TOP_UNIVPLL_D10,
 301         CLK_TOP_UNIVPLL_D8
 302 };
 303
 304 static const int aud_i2s0_m_parents[] = {
 305         CLK_TOP_AUD1,
 306         CLK_TOP_AUD2
 307 };
 308
 309 static const int aud_spdifin_parents[] = {
 310         CLK_TOP_CLK26M,
 311         CLK_TOP_UNIVPLL_D2,
 312         CLK_TOP_TVDPLL
 313 };
 314
 315 static const int dbg_atclk_parents[] = {
 316         CLK_TOP_CLK_NULL,
 317         CLK_TOP_CLK26M,
 318         CLK_TOP_MAINPLL_D5,
 319         CLK_TOP_CLK_NULL,
 320         CLK_TOP_UNIVPLL_D5
 321 };
 322
 323 static const int png_sys_parents[] = {
 324         CLK_TOP_CLK26M,
 325         CLK_TOP_UNIVPLL_D8,
 326         CLK_TOP_MAINPLL_D7,
 327         CLK_TOP_MAINPLL_D6,
 328         CLK_TOP_MAINPLL_D5,
 329         CLK_TOP_UNIVPLL_D3
 330 };
 331
 332 static const int sej_13m_parents[] = {
 333         CLK_TOP_CLK26M,
 334         CLK_TOP_CLK26M_D2
 335 };
 336
 337 static const int imgrz_sys_parents[] = {
 338         CLK_TOP_CLK26M,
 339         CLK_TOP_MAINPLL_D6,
 340         CLK_TOP_MAINPLL_D7,
 341         CLK_TOP_MAINPLL_D5,
 342         CLK_TOP_UNIVPLL_D4,
 343         CLK_TOP_UNIVPLL_D10,
 344         CLK_TOP_UNIVPLL_D5,
 345         CLK_TOP_UNIVPLL_D6
 346 };
 347
 348 static const int graph_eclk_parents[] = {
 349         CLK_TOP_CLK26M,
 350         CLK_TOP_MAINPLL_D6,
 351         CLK_TOP_UNIVPLL_D8,
 352         CLK_TOP_UNIVPLL_D16,
 353         CLK_TOP_MAINPLL_D7,
 354         CLK_TOP_UNIVPLL_D4,
 355         CLK_TOP_UNIVPLL_D10,
 356         CLK_TOP_UNIVPLL_D24,
 357         CLK_TOP_MAINPLL_D8
 358 };
 359
 360 static const int fdbi_parents[] = {
 361         CLK_TOP_CLK26M,
 362         CLK_TOP_MAINPLL_D12,
 363         CLK_TOP_MAINPLL_D14,
 364         CLK_TOP_MAINPLL_D16,
 365         CLK_TOP_UNIVPLL_D10,
 366         CLK_TOP_UNIVPLL_D12,
 367         CLK_TOP_UNIVPLL_D16,
 368         CLK_TOP_UNIVPLL_D24,
 369         CLK_TOP_TVDPLL_D2,
 370         CLK_TOP_TVDPLL_D4,
 371         CLK_TOP_TVDPLL_D8,
 372         CLK_TOP_TVDPLL_D16
 373 };
 374
 375 static const int faudio_parents[] = {
 376         CLK_TOP_CLK26M,
 377         CLK_TOP_UNIVPLL_D24,
 378         CLK_TOP_APLL1_D4,
 379         CLK_TOP_APLL2_D4
 380 };
 381
 382 static const int fa2sys_parents[] = {
 383         CLK_TOP_CLK26M,
 384         CLK_TOP_APLL1_SRC_SEL,
 385         CLK_TOP_RG_APLL1_D2,
 386         CLK_TOP_RG_APLL1_D4,
 387         CLK_TOP_RG_APLL1_D8,
 388         CLK_TOP_RG_APLL1_D16,
 389         CLK_TOP_CLK26M_D2,
 390         CLK_TOP_RG_APLL1_D3
 391 };
 392
 393 static const int fa1sys_parents[] = {
 394         CLK_TOP_CLK26M,
 395         CLK_TOP_APLL2_SRC_SEL,
 396         CLK_TOP_RG_APLL2_D2,
 397         CLK_TOP_RG_APLL2_D4,
 398         CLK_TOP_RG_APLL2_D8,
 399         CLK_TOP_RG_APLL2_D16,
 400         CLK_TOP_CLK26M_D2,
 401         CLK_TOP_RG_APLL2_D3
 402 };
 403
 404 static const int fasm_m_parents[] = {
 405         CLK_TOP_CLK26M,
 406         CLK_TOP_UNIVPLL_D12,
 407         CLK_TOP_UNIVPLL_D6,
 408         CLK_TOP_MAINPLL_D7
 409 };
 410
 411 static const int fecc_ck_parents[] = {
 412         CLK_TOP_CLK_NULL,
 413         CLK_TOP_CLK_NULL,
 414         CLK_TOP_CLK_NULL,
 415         CLK_TOP_CLK_NULL,
 416         CLK_TOP_CLK_NULL,
 417         CLK_TOP_CLK_NULL,
 418         CLK_TOP_CLK_NULL,
 419         CLK_TOP_CLK_NULL,
 420         CLK_TOP_CLK_NULL,
 421         CLK_TOP_CLK26M,
 422         CLK_TOP_UNIVPLL_D6,
 423         CLK_TOP_CLK_NULL,
 424         CLK_TOP_UNIVPLL_D4,
 425         CLK_TOP_CLK_NULL,
 426         CLK_TOP_CLK_NULL,
 427         CLK_TOP_CLK_NULL,
 428         CLK_TOP_UNIVPLL_D3,
 429         CLK_TOP_CLK_NULL,
 430         CLK_TOP_CLK_NULL,
 431         CLK_TOP_CLK_NULL,
 432         CLK_TOP_CLK_NULL,
 433         CLK_TOP_CLK_NULL,
 434         CLK_TOP_CLK_NULL,
 435         CLK_TOP_CLK_NULL,
 436         CLK_TOP_CLK_NULL,
 437         CLK_TOP_CLK_NULL,
 438         CLK_TOP_CLK_NULL,
 439         CLK_TOP_CLK_NULL,
 440         CLK_TOP_CLK_NULL,
 441         CLK_TOP_CLK_NULL,
 442         CLK_TOP_CLK_NULL,
 443         CLK_TOP_CLK_NULL,
 444         CLK_TOP_MAINPLL_D3
 445 };
 446
 447 static const int pe2_mac_parents[] = {
 448         CLK_TOP_CLK26M,
 449         CLK_TOP_MAINPLL_D11,
 450         CLK_TOP_MAINPLL_D16,
 451         CLK_TOP_UNIVPLL_D12,
 452         CLK_TOP_UNIVPLL_D10
 453 };
 454
 455 static const int cmsys_parents[] = {
 456         CLK_TOP_CLK26M,
 457         CLK_TOP_UNIVPLL_D5,
 458         CLK_TOP_UNIVPLL_D6,
 459         CLK_TOP_MAINPLL_D5,
 460         CLK_TOP_APLL2,
 461         CLK_TOP_APLL2_D2,
 462         CLK_TOP_APLL2_D4,
 463         CLK_TOP_APLL2_D3
 464 };
 465
 466 static const int gcpu_parents[] = {
 467         CLK_TOP_CLK26M,
 468         CLK_TOP_MAINPLL_D4,
 469         CLK_TOP_MAINPLL_D5,
 470         CLK_TOP_MAINPLL_D6,
 471         CLK_TOP_MAINPLL_D7,
 472         CLK_TOP_UNIVPLL_D4,
 473         CLK_TOP_UNIVPLL_D10,
 474         CLK_TOP_UNIVPLL_D3
 475 };
 476
 477 static const int spis_ck_parents[] = {
 478         CLK_TOP_CLK_NULL,
 479         CLK_TOP_CLK26M,
 480         CLK_TOP_UNIVPLL_D12,
 481         CLK_TOP_CLK_NULL,
 482         CLK_TOP_UNIVPLL_D8,
 483         CLK_TOP_CLK_NULL,
 484         CLK_TOP_CLK_NULL,
 485         CLK_TOP_CLK_NULL,
 486         CLK_TOP_UNIVPLL_D6,
 487         CLK_TOP_CLK_NULL,
 488         CLK_TOP_CLK_NULL,
 489         CLK_TOP_CLK_NULL,
 490         CLK_TOP_CLK_NULL,
 491         CLK_TOP_CLK_NULL,
 492         CLK_TOP_CLK_NULL,
 493         CLK_TOP_CLK_NULL,
 494         CLK_TOP_UNIVPLL_D5,
 495         CLK_TOP_CLK_NULL,
 496         CLK_TOP_CLK_NULL,
 497         CLK_TOP_CLK_NULL,
 498         CLK_TOP_CLK_NULL,
 499         CLK_TOP_CLK_NULL,
 500         CLK_TOP_CLK_NULL,
 501         CLK_TOP_CLK_NULL,
 502         CLK_TOP_CLK_NULL,
 503         CLK_TOP_CLK_NULL,
 504         CLK_TOP_CLK_NULL,
 505         CLK_TOP_CLK_NULL,
 506         CLK_TOP_CLK_NULL,
 507         CLK_TOP_CLK_NULL,
 508         CLK_TOP_CLK_NULL,
 509         CLK_TOP_CLK_NULL,
 510         CLK_TOP_UNIVPLL_D4,
 511         CLK_TOP_CLK_NULL,
 512         CLK_TOP_CLK_NULL,
 513         CLK_TOP_CLK_NULL,
 514         CLK_TOP_CLK_NULL,
 515         CLK_TOP_CLK_NULL,
 516         CLK_TOP_CLK_NULL,
 517         CLK_TOP_CLK_NULL,
 518         CLK_TOP_CLK_NULL,
 519         CLK_TOP_CLK_NULL,
 520         CLK_TOP_CLK_NULL,
 521         CLK_TOP_CLK_NULL,
 522         CLK_TOP_CLK_NULL,
 523         CLK_TOP_CLK_NULL,
 524         CLK_TOP_CLK_NULL,
 525         CLK_TOP_CLK_NULL,
 526         CLK_TOP_CLK_NULL,
 527         CLK_TOP_CLK_NULL,
 528         CLK_TOP_CLK_NULL,
 529         CLK_TOP_CLK_NULL,
 530         CLK_TOP_CLK_NULL,
 531         CLK_TOP_CLK_NULL,
 532         CLK_TOP_CLK_NULL,
 533         CLK_TOP_CLK_NULL,
 534         CLK_TOP_CLK_NULL,
 535         CLK_TOP_CLK_NULL,
 536         CLK_TOP_CLK_NULL,
 537         CLK_TOP_CLK_NULL,
 538         CLK_TOP_CLK_NULL,
 539         CLK_TOP_CLK_NULL,
 540         CLK_TOP_CLK_NULL,
 541         CLK_TOP_CLK_NULL,
 542         CLK_TOP_MAINPLL_D4,
 543         CLK_TOP_CLK_NULL,
 544         CLK_TOP_CLK_NULL,
 545         CLK_TOP_CLK_NULL,
 546         CLK_TOP_CLK_NULL,
 547         CLK_TOP_CLK_NULL,
 548         CLK_TOP_CLK_NULL,
 549         CLK_TOP_CLK_NULL,
 550         CLK_TOP_CLK_NULL,
 551         CLK_TOP_CLK_NULL,
 552         CLK_TOP_CLK_NULL,
 553         CLK_TOP_CLK_NULL,
 554         CLK_TOP_CLK_NULL,
 555         CLK_TOP_CLK_NULL,
 556         CLK_TOP_CLK_NULL,
 557         CLK_TOP_CLK_NULL,
 558         CLK_TOP_CLK_NULL,
 559         CLK_TOP_CLK_NULL,
 560         CLK_TOP_CLK_NULL,
 561         CLK_TOP_CLK_NULL,
 562         CLK_TOP_CLK_NULL,
 563         CLK_TOP_CLK_NULL,
 564         CLK_TOP_CLK_NULL,
 565         CLK_TOP_CLK_NULL,
 566         CLK_TOP_CLK_NULL,
 567         CLK_TOP_CLK_NULL,
 568         CLK_TOP_CLK_NULL,
 569         CLK_TOP_CLK_NULL,
 570         CLK_TOP_CLK_NULL,
 571         CLK_TOP_CLK_NULL,
 572         CLK_TOP_CLK_NULL,
 573         CLK_TOP_CLK_NULL,
 574         CLK_TOP_CLK_NULL,
 575         CLK_TOP_CLK_NULL,
 576         CLK_TOP_CLK_NULL,
 577         CLK_TOP_CLK_NULL,
 578         CLK_TOP_CLK_NULL,
 579         CLK_TOP_CLK_NULL,
 580         CLK_TOP_CLK_NULL,
 581         CLK_TOP_CLK_NULL,
 582         CLK_TOP_CLK_NULL,
 583         CLK_TOP_CLK_NULL,
 584         CLK_TOP_CLK_NULL,
 585         CLK_TOP_CLK_NULL,
 586         CLK_TOP_CLK_NULL,
 587         CLK_TOP_CLK_NULL,
 588         CLK_TOP_CLK_NULL,
 589         CLK_TOP_CLK_NULL,
 590         CLK_TOP_CLK_NULL,
 591         CLK_TOP_CLK_NULL,
 592         CLK_TOP_CLK_NULL,
 593         CLK_TOP_CLK_NULL,
 594         CLK_TOP_CLK_NULL,
 595         CLK_TOP_CLK_NULL,
 596         CLK_TOP_CLK_NULL,
 597         CLK_TOP_CLK_NULL,
 598         CLK_TOP_CLK_NULL,
 599         CLK_TOP_CLK_NULL,
 600         CLK_TOP_CLK_NULL,
 601         CLK_TOP_CLK_NULL,
 602         CLK_TOP_CLK_NULL,
 603         CLK_TOP_CLK_NULL,
 604         CLK_TOP_CLK_NULL,
 605         CLK_TOP_CLK_NULL,
 606         CLK_TOP_UNIVPLL_D3
 607 };
 608
 609 static const int apll1_ref_parents[] = {
 610         CLK_TOP_CLK_NULL,
 611         CLK_TOP_CLK_NULL,
 612         CLK_TOP_CLK_NULL,
 613         CLK_TOP_CLK_NULL,
 614         CLK_TOP_CLK_NULL,
 615         CLK_TOP_CLK_NULL
 616 };
 617
 618 static const int int_32k_parents[] = {
 619         CLK_TOP_CLK32K,
 620         CLK_TOP_CLK26M_D793
 621 };
 622
 623 static const int apll1_src_parents[] = {
 624         CLK_TOP_APLL1,
 625         CLK_TOP_CLK_NULL,
 626         CLK_TOP_CLK_NULL,
 627         CLK_TOP_CLK_NULL
 628 };
 629
 630 static const int apll2_src_parents[] = {
 631         CLK_TOP_APLL2,
 632         CLK_TOP_CLK_NULL,
 633         CLK_TOP_CLK_NULL,
 634         CLK_TOP_CLK_NULL
 635 };
 636
 637 static const int faud_intbus_parents[] = {
 638         CLK_TOP_CLK_NULL,
 639         CLK_TOP_CLK26M,
 640         CLK_TOP_MAINPLL_D11,
 641         CLK_TOP_CLK_NULL,
 642         CLK_TOP_CLK26M,
 643         CLK_TOP_CLK_NULL,
 644         CLK_TOP_CLK_NULL,
 645         CLK_TOP_CLK_NULL,
 646         CLK_TOP_UNIVPLL_D10,
 647         CLK_TOP_CLK_NULL,
 648         CLK_TOP_CLK_NULL,
 649         CLK_TOP_CLK_NULL,
 650         CLK_TOP_CLK_NULL,
 651         CLK_TOP_CLK_NULL,
 652         CLK_TOP_CLK_NULL,
 653         CLK_TOP_CLK_NULL,
 654         CLK_TOP_RG_APLL2_D8,
 655         CLK_TOP_CLK_NULL,
 656         CLK_TOP_CLK_NULL,
 657         CLK_TOP_CLK_NULL,
 658         CLK_TOP_CLK_NULL,
 659         CLK_TOP_CLK_NULL,
 660         CLK_TOP_CLK_NULL,
 661         CLK_TOP_CLK_NULL,
 662         CLK_TOP_CLK_NULL,
 663         CLK_TOP_CLK_NULL,
 664         CLK_TOP_CLK_NULL,
 665         CLK_TOP_CLK_NULL,
 666         CLK_TOP_CLK_NULL,
 667         CLK_TOP_CLK_NULL,
 668         CLK_TOP_CLK_NULL,
 669         CLK_TOP_CLK_NULL,
 670         CLK_TOP_CLK26M_D2,
 671         CLK_TOP_CLK_NULL,
 672         CLK_TOP_CLK_NULL,
 673         CLK_TOP_CLK_NULL,
 674         CLK_TOP_CLK_NULL,
 675         CLK_TOP_CLK_NULL,
 676         CLK_TOP_CLK_NULL,
 677         CLK_TOP_CLK_NULL,
 678         CLK_TOP_CLK_NULL,
 679         CLK_TOP_CLK_NULL,
 680         CLK_TOP_CLK_NULL,
 681         CLK_TOP_CLK_NULL,
 682         CLK_TOP_CLK_NULL,
 683         CLK_TOP_CLK_NULL,
 684         CLK_TOP_CLK_NULL,
 685         CLK_TOP_CLK_NULL,
 686         CLK_TOP_CLK_NULL,
 687         CLK_TOP_CLK_NULL,
 688         CLK_TOP_CLK_NULL,
 689         CLK_TOP_CLK_NULL,
 690         CLK_TOP_CLK_NULL,
 691         CLK_TOP_CLK_NULL,
 692         CLK_TOP_CLK_NULL,
 693         CLK_TOP_CLK_NULL,
 694         CLK_TOP_CLK_NULL,
 695         CLK_TOP_CLK_NULL,
 696         CLK_TOP_CLK_NULL,
 697         CLK_TOP_CLK_NULL,
 698         CLK_TOP_CLK_NULL,
 699         CLK_TOP_CLK_NULL,
 700         CLK_TOP_CLK_NULL,
 701         CLK_TOP_CLK_NULL,
 702         CLK_TOP_RG_APLL1_D8,
 703         CLK_TOP_CLK_NULL,
 704         CLK_TOP_CLK_NULL,
 705         CLK_TOP_CLK_NULL,
 706         CLK_TOP_CLK_NULL,
 707         CLK_TOP_CLK_NULL,
 708         CLK_TOP_CLK_NULL,
 709         CLK_TOP_CLK_NULL,
 710         CLK_TOP_CLK_NULL,
 711         CLK_TOP_CLK_NULL,
 712         CLK_TOP_CLK_NULL,
 713         CLK_TOP_CLK_NULL,
 714         CLK_TOP_CLK_NULL,
 715         CLK_TOP_CLK_NULL,
 716         CLK_TOP_CLK_NULL,
 717         CLK_TOP_CLK_NULL,
 718         CLK_TOP_CLK_NULL,
 719         CLK_TOP_CLK_NULL,
 720         CLK_TOP_CLK_NULL,
 721         CLK_TOP_CLK_NULL,
 722         CLK_TOP_CLK_NULL,
 723         CLK_TOP_CLK_NULL,
 724         CLK_TOP_CLK_NULL,
 725         CLK_TOP_CLK_NULL,
 726         CLK_TOP_CLK_NULL,
 727         CLK_TOP_CLK_NULL,
 728         CLK_TOP_CLK_NULL,
 729         CLK_TOP_CLK_NULL,
 730         CLK_TOP_CLK_NULL,
 731         CLK_TOP_CLK_NULL,
 732         CLK_TOP_CLK_NULL,
 733         CLK_TOP_CLK_NULL,
 734         CLK_TOP_CLK_NULL,
 735         CLK_TOP_CLK_NULL,
 736         CLK_TOP_CLK_NULL,
 737         CLK_TOP_CLK_NULL,
 738         CLK_TOP_CLK_NULL,
 739         CLK_TOP_CLK_NULL,
 740         CLK_TOP_CLK_NULL,
 741         CLK_TOP_CLK_NULL,
 742         CLK_TOP_CLK_NULL,
 743         CLK_TOP_CLK_NULL,
 744         CLK_TOP_CLK_NULL,
 745         CLK_TOP_CLK_NULL,
 746         CLK_TOP_CLK_NULL,
 747         CLK_TOP_CLK_NULL,
 748         CLK_TOP_CLK_NULL,
 749         CLK_TOP_CLK_NULL,
 750         CLK_TOP_CLK_NULL,
 751         CLK_TOP_CLK_NULL,
 752         CLK_TOP_CLK_NULL,
 753         CLK_TOP_CLK_NULL,
 754         CLK_TOP_CLK_NULL,
 755         CLK_TOP_CLK_NULL,
 756         CLK_TOP_CLK_NULL,
 757         CLK_TOP_CLK_NULL,
 758         CLK_TOP_CLK_NULL,
 759         CLK_TOP_CLK_NULL,
 760         CLK_TOP_CLK_NULL,
 761         CLK_TOP_CLK_NULL,
 762         CLK_TOP_CLK_NULL,
 763         CLK_TOP_CLK_NULL,
 764         CLK_TOP_CLK_NULL,
 765         CLK_TOP_CLK_NULL,
 766         CLK_TOP_UNIVPLL_D20
 767 };
 768
 769 static const int axibus_parents[] = {
 770         CLK_TOP_CLK_NULL,
 771         CLK_TOP_CLK26M,
 772         CLK_TOP_MAINPLL_D11,
 773         CLK_TOP_CLK_NULL,
 774         CLK_TOP_MAINPLL_D12,
 775         CLK_TOP_CLK_NULL,
 776         CLK_TOP_CLK_NULL,
 777         CLK_TOP_CLK_NULL,
 778         CLK_TOP_UNIVPLL_D10,
 779         CLK_TOP_CLK_NULL,
 780         CLK_TOP_CLK_NULL,
 781         CLK_TOP_CLK_NULL,
 782         CLK_TOP_CLK_NULL,
 783         CLK_TOP_CLK_NULL,
 784         CLK_TOP_CLK_NULL,
 785         CLK_TOP_CLK_NULL,
 786         CLK_TOP_CLK26M_D2,
 787         CLK_TOP_CLK_NULL,
 788         CLK_TOP_CLK_NULL,
 789         CLK_TOP_CLK_NULL,
 790         CLK_TOP_CLK_NULL,
 791         CLK_TOP_CLK_NULL,
 792         CLK_TOP_CLK_NULL,
 793         CLK_TOP_CLK_NULL,
 794         CLK_TOP_CLK_NULL,
 795         CLK_TOP_CLK_NULL,
 796         CLK_TOP_CLK_NULL,
 797         CLK_TOP_CLK_NULL,
 798         CLK_TOP_CLK_NULL,
 799         CLK_TOP_CLK_NULL,
 800         CLK_TOP_CLK_NULL,
 801         CLK_TOP_CLK_NULL,
 802         CLK_TOP_APLL2_D8
 803 };
 804
 805 static const int hapll1_parents[] = {
 806         CLK_TOP_CLK26M,
 807         CLK_TOP_APLL1_SRC_SEL,
 808         CLK_TOP_RG_APLL1_D2,
 809         CLK_TOP_RG_APLL1_D4,
 810         CLK_TOP_RG_APLL1_D8,
 811         CLK_TOP_RG_APLL1_D16,
 812         CLK_TOP_CLK26M_D2,
 813         CLK_TOP_CLK26M_D8,
 814         CLK_TOP_RG_APLL1_D3
 815 };
 816
 817 static const int hapll2_parents[] = {
 818         CLK_TOP_CLK26M,
 819         CLK_TOP_APLL2_SRC_SEL,
 820         CLK_TOP_RG_APLL2_D2,
 821         CLK_TOP_RG_APLL2_D4,
 822         CLK_TOP_RG_APLL2_D8,
 823         CLK_TOP_RG_APLL2_D16,
 824         CLK_TOP_CLK26M_D2,
 825         CLK_TOP_CLK26M_D4,
 826         CLK_TOP_RG_APLL2_D3
 827 };
 828
 829 static const int spinfi_parents[] = {
 830         CLK_TOP_CLK26M,
 831         CLK_TOP_UNIVPLL_D24,
 832         CLK_TOP_UNIVPLL_D20,
 833         CLK_TOP_MAINPLL_D22,
 834         CLK_TOP_UNIVPLL_D16,
 835         CLK_TOP_MAINPLL_D16,
 836         CLK_TOP_UNIVPLL_D12,
 837         CLK_TOP_UNIVPLL_D10,
 838         CLK_TOP_MAINPLL_D11
 839 };
 840
 841 static const int msdc0_parents[] = {
 842         CLK_TOP_CLK_NULL,
 843         CLK_TOP_CLK26M,
 844         CLK_TOP_UNIVPLL_D6,
 845         CLK_TOP_CLK_NULL,
 846         CLK_TOP_MAINPLL_D8,
 847         CLK_TOP_CLK_NULL,
 848         CLK_TOP_CLK_NULL,
 849         CLK_TOP_CLK_NULL,
 850         CLK_TOP_UNIVPLL_D8,
 851         CLK_TOP_CLK_NULL,
 852         CLK_TOP_CLK_NULL,
 853         CLK_TOP_CLK_NULL,
 854         CLK_TOP_CLK_NULL,
 855         CLK_TOP_CLK_NULL,
 856         CLK_TOP_CLK_NULL,
 857         CLK_TOP_CLK_NULL,
 858         CLK_TOP_MAINPLL_D16,
 859         CLK_TOP_CLK_NULL,
 860         CLK_TOP_CLK_NULL,
 861         CLK_TOP_CLK_NULL,
 862         CLK_TOP_CLK_NULL,
 863         CLK_TOP_CLK_NULL,
 864         CLK_TOP_CLK_NULL,
 865         CLK_TOP_CLK_NULL,
 866         CLK_TOP_CLK_NULL,
 867         CLK_TOP_CLK_NULL,
 868         CLK_TOP_CLK_NULL,
 869         CLK_TOP_CLK_NULL,
 870         CLK_TOP_CLK_NULL,
 871         CLK_TOP_CLK_NULL,
 872         CLK_TOP_CLK_NULL,
 873         CLK_TOP_CLK_NULL,
 874         CLK_TOP_MAINPLL_D12,
 875         CLK_TOP_CLK_NULL,
 876         CLK_TOP_CLK_NULL,
 877         CLK_TOP_CLK_NULL,
 878         CLK_TOP_CLK_NULL,
 879         CLK_TOP_CLK_NULL,
 880         CLK_TOP_CLK_NULL,
 881         CLK_TOP_CLK_NULL,
 882         CLK_TOP_CLK_NULL,
 883         CLK_TOP_CLK_NULL,
 884         CLK_TOP_CLK_NULL,
 885         CLK_TOP_CLK_NULL,
 886         CLK_TOP_CLK_NULL,
 887         CLK_TOP_CLK_NULL,
 888         CLK_TOP_CLK_NULL,
 889         CLK_TOP_CLK_NULL,
 890         CLK_TOP_CLK_NULL,
 891         CLK_TOP_CLK_NULL,
 892         CLK_TOP_CLK_NULL,
 893         CLK_TOP_CLK_NULL,
 894         CLK_TOP_CLK_NULL,
 895         CLK_TOP_CLK_NULL,
 896         CLK_TOP_CLK_NULL,
 897         CLK_TOP_CLK_NULL,
 898         CLK_TOP_CLK_NULL,
 899         CLK_TOP_CLK_NULL,
 900         CLK_TOP_CLK_NULL,
 901         CLK_TOP_CLK_NULL,
 902         CLK_TOP_CLK_NULL,
 903         CLK_TOP_CLK_NULL,
 904         CLK_TOP_CLK_NULL,
 905         CLK_TOP_CLK_NULL,
 906         CLK_APMIXED_MMPLL,
 907         CLK_TOP_CLK_NULL,
 908         CLK_TOP_CLK_NULL,
 909         CLK_TOP_CLK_NULL,
 910         CLK_TOP_CLK_NULL,
 911         CLK_TOP_CLK_NULL,
 912         CLK_TOP_CLK_NULL,
 913         CLK_TOP_CLK_NULL,
 914         CLK_TOP_CLK_NULL,
 915         CLK_TOP_CLK_NULL,
 916         CLK_TOP_CLK_NULL,
 917         CLK_TOP_CLK_NULL,
 918         CLK_TOP_CLK_NULL,
 919         CLK_TOP_CLK_NULL,
 920         CLK_TOP_CLK_NULL,
 921         CLK_TOP_CLK_NULL,
 922         CLK_TOP_CLK_NULL,
 923         CLK_TOP_CLK_NULL,
 924         CLK_TOP_CLK_NULL,
 925         CLK_TOP_CLK_NULL,
 926         CLK_TOP_CLK_NULL,
 927         CLK_TOP_CLK_NULL,
 928         CLK_TOP_CLK_NULL,
 929         CLK_TOP_CLK_NULL,
 930         CLK_TOP_CLK_NULL,
 931         CLK_TOP_CLK_NULL,
 932         CLK_TOP_CLK_NULL,
 933         CLK_TOP_CLK_NULL,
 934         CLK_TOP_CLK_NULL,
 935         CLK_TOP_CLK_NULL,
 936         CLK_TOP_CLK_NULL,
 937         CLK_TOP_CLK_NULL,
 938         CLK_TOP_CLK_NULL,
 939         CLK_TOP_CLK_NULL,
 940         CLK_TOP_CLK_NULL,
 941         CLK_TOP_CLK_NULL,
 942         CLK_TOP_CLK_NULL,
 943         CLK_TOP_CLK_NULL,
 944         CLK_TOP_CLK_NULL,
 945         CLK_TOP_CLK_NULL,
 946         CLK_TOP_CLK_NULL,
 947         CLK_TOP_CLK_NULL,
 948         CLK_TOP_CLK_NULL,
 949         CLK_TOP_CLK_NULL,
 950         CLK_TOP_CLK_NULL,
 951         CLK_TOP_CLK_NULL,
 952         CLK_TOP_CLK_NULL,
 953         CLK_TOP_CLK_NULL,
 954         CLK_TOP_CLK_NULL,
 955         CLK_TOP_CLK_NULL,
 956         CLK_TOP_CLK_NULL,
 957         CLK_TOP_CLK_NULL,
 958         CLK_TOP_CLK_NULL,
 959         CLK_TOP_CLK_NULL,
 960         CLK_TOP_CLK_NULL,
 961         CLK_TOP_CLK_NULL,
 962         CLK_TOP_CLK_NULL,
 963         CLK_TOP_CLK_NULL,
 964         CLK_TOP_CLK_NULL,
 965         CLK_TOP_CLK_NULL,
 966         CLK_TOP_CLK_NULL,
 967         CLK_TOP_CLK_NULL,
 968         CLK_TOP_CLK_NULL,
 969         CLK_TOP_CLK_NULL,
 970         CLK_TOP_MMPLL_D2
 971 };
 972
 973 static const int msdc0_clk50_parents[] = {
 974         CLK_TOP_CLK_NULL,
 975         CLK_TOP_CLK_NULL,
 976         CLK_TOP_CLK_NULL,
 977         CLK_TOP_CLK_NULL,
 978         CLK_TOP_CLK_NULL,
 979         CLK_TOP_CLK_NULL,
 980         CLK_TOP_CLK_NULL,
 981         CLK_TOP_CLK_NULL,
 982         CLK_TOP_CLK_NULL,
 983         CLK_TOP_CLK26M,
 984         CLK_TOP_UNIVPLL_D6,
 985         CLK_TOP_CLK_NULL,
 986         CLK_TOP_MAINPLL_D8,
 987         CLK_TOP_CLK_NULL,
 988         CLK_TOP_CLK_NULL,
 989         CLK_TOP_CLK_NULL,
 990         CLK_TOP_UNIVPLL_D8,
 991         CLK_TOP_CLK_NULL,
 992         CLK_TOP_CLK_NULL,
 993         CLK_TOP_CLK_NULL,
 994         CLK_TOP_CLK_NULL,
 995         CLK_TOP_CLK_NULL,
 996         CLK_TOP_CLK_NULL,
 997         CLK_TOP_CLK_NULL,
 998         CLK_TOP_CLK_NULL,
 999         CLK_TOP_CLK_NULL,
1000         CLK_TOP_CLK_NULL,
1001         CLK_TOP_CLK_NULL,
1002         CLK_TOP_CLK_NULL,
1003         CLK_TOP_CLK_NULL,
1004         CLK_TOP_CLK_NULL,
1005         CLK_TOP_CLK_NULL,
1006         CLK_TOP_MAINPLL_D6
1007 };
1008
1009 static const int msdc2_parents[] = {
1010         CLK_TOP_CLK_NULL,
1011         CLK_TOP_CLK26M,
1012         CLK_TOP_UNIVPLL_D6,
1013         CLK_TOP_CLK_NULL,
1014         CLK_TOP_MAINPLL_D8,
1015         CLK_TOP_CLK_NULL,
1016         CLK_TOP_CLK_NULL,
1017         CLK_TOP_CLK_NULL,
1018         CLK_TOP_UNIVPLL_D8,
1019         CLK_TOP_CLK_NULL,
1020         CLK_TOP_CLK_NULL,
1021         CLK_TOP_CLK_NULL,
1022         CLK_TOP_CLK_NULL,
1023         CLK_TOP_CLK_NULL,
1024         CLK_TOP_CLK_NULL,
1025         CLK_TOP_CLK_NULL,
1026         CLK_TOP_MAINPLL_D16,
1027         CLK_TOP_CLK_NULL,
1028         CLK_TOP_CLK_NULL,
1029         CLK_TOP_CLK_NULL,
1030         CLK_TOP_CLK_NULL,
1031         CLK_TOP_CLK_NULL,
1032         CLK_TOP_CLK_NULL,
1033         CLK_TOP_CLK_NULL,
1034         CLK_TOP_CLK_NULL,
1035         CLK_TOP_CLK_NULL,
1036         CLK_TOP_CLK_NULL,
1037         CLK_TOP_CLK_NULL,
1038         CLK_TOP_CLK_NULL,
1039         CLK_TOP_CLK_NULL,
1040         CLK_TOP_CLK_NULL,
1041         CLK_TOP_CLK_NULL,
1042         CLK_TOP_MMPLL_D2,
1043         CLK_TOP_CLK_NULL,
1044         CLK_TOP_CLK_NULL,
1045         CLK_TOP_CLK_NULL,
1046         CLK_TOP_CLK_NULL,
1047         CLK_TOP_CLK_NULL,
1048         CLK_TOP_CLK_NULL,
1049         CLK_TOP_CLK_NULL,
1050         CLK_TOP_CLK_NULL,
1051         CLK_TOP_CLK_NULL,
1052         CLK_TOP_CLK_NULL,
1053         CLK_TOP_CLK_NULL,
1054         CLK_TOP_CLK_NULL,
1055         CLK_TOP_CLK_NULL,
1056         CLK_TOP_CLK_NULL,
1057         CLK_TOP_CLK_NULL,
1058         CLK_TOP_CLK_NULL,
1059         CLK_TOP_CLK_NULL,
1060         CLK_TOP_CLK_NULL,
1061         CLK_TOP_CLK_NULL,
1062         CLK_TOP_CLK_NULL,
1063         CLK_TOP_CLK_NULL,
1064         CLK_TOP_CLK_NULL,
1065         CLK_TOP_CLK_NULL,
1066         CLK_TOP_CLK_NULL,
1067         CLK_TOP_CLK_NULL,
1068         CLK_TOP_CLK_NULL,
1069         CLK_TOP_CLK_NULL,
1070         CLK_TOP_CLK_NULL,
1071         CLK_TOP_CLK_NULL,
1072         CLK_TOP_CLK_NULL,
1073         CLK_TOP_CLK_NULL,
1074         CLK_TOP_MAINPLL_D12,
1075         CLK_TOP_CLK_NULL,
1076         CLK_TOP_CLK_NULL,
1077         CLK_TOP_CLK_NULL,
1078         CLK_TOP_CLK_NULL,
1079         CLK_TOP_CLK_NULL,
1080         CLK_TOP_CLK_NULL,
1081         CLK_TOP_CLK_NULL,
1082         CLK_TOP_CLK_NULL,
1083         CLK_TOP_CLK_NULL,
1084         CLK_TOP_CLK_NULL,
1085         CLK_TOP_CLK_NULL,
1086         CLK_TOP_CLK_NULL,
1087         CLK_TOP_CLK_NULL,
1088         CLK_TOP_CLK_NULL,
1089         CLK_TOP_CLK_NULL,
1090         CLK_TOP_CLK_NULL,
1091         CLK_TOP_CLK_NULL,
1092         CLK_TOP_CLK_NULL,
1093         CLK_TOP_CLK_NULL,
1094         CLK_TOP_CLK_NULL,
1095         CLK_TOP_CLK_NULL,
1096         CLK_TOP_CLK_NULL,
1097         CLK_TOP_CLK_NULL,
1098         CLK_TOP_CLK_NULL,
1099         CLK_TOP_CLK_NULL,
1100         CLK_TOP_CLK_NULL,
1101         CLK_TOP_CLK_NULL,
1102         CLK_TOP_CLK_NULL,
1103         CLK_TOP_CLK_NULL,
1104         CLK_TOP_CLK_NULL,
1105         CLK_TOP_CLK_NULL,
1106         CLK_TOP_CLK_NULL,
1107         CLK_TOP_CLK_NULL,
1108         CLK_TOP_CLK_NULL,
1109         CLK_TOP_CLK_NULL,
1110         CLK_TOP_CLK_NULL,
1111         CLK_TOP_CLK_NULL,
1112         CLK_TOP_CLK_NULL,
1113         CLK_TOP_CLK_NULL,
1114         CLK_TOP_CLK_NULL,
1115         CLK_TOP_CLK_NULL,
1116         CLK_TOP_CLK_NULL,
1117         CLK_TOP_CLK_NULL,
1118         CLK_TOP_CLK_NULL,
1119         CLK_TOP_CLK_NULL,
1120         CLK_TOP_CLK_NULL,
1121         CLK_TOP_CLK_NULL,
1122         CLK_TOP_CLK_NULL,
1123         CLK_TOP_CLK_NULL,
1124         CLK_TOP_CLK_NULL,
1125         CLK_TOP_CLK_NULL,
1126         CLK_TOP_CLK_NULL,
1127         CLK_TOP_CLK_NULL,
1128         CLK_TOP_CLK_NULL,
1129         CLK_TOP_CLK_NULL,
1130         CLK_TOP_CLK_NULL,
1131         CLK_TOP_CLK_NULL,
1132         CLK_TOP_CLK_NULL,
1133         CLK_TOP_CLK_NULL,
1134         CLK_TOP_CLK_NULL,
1135         CLK_TOP_CLK_NULL,
1136         CLK_TOP_CLK_NULL,
1137         CLK_TOP_CLK_NULL,
1138         CLK_APMIXED_MMPLL
1139 };
1140
1141 static const int disp_dpi_ck_parents[] = {
1142         CLK_TOP_CLK_NULL,
1143         CLK_TOP_CLK_NULL,
1144         CLK_TOP_CLK_NULL,
1145         CLK_TOP_CLK_NULL,
1146         CLK_TOP_CLK_NULL,
1147         CLK_TOP_CLK_NULL,
1148         CLK_TOP_CLK_NULL,
1149         CLK_TOP_CLK_NULL,
1150         CLK_TOP_CLK_NULL,
1151         CLK_TOP_CLK26M,
1152         CLK_TOP_TVDPLL_D2,
1153         CLK_TOP_CLK_NULL,
1154         CLK_TOP_TVDPLL_D4,
1155         CLK_TOP_CLK_NULL,
1156         CLK_TOP_CLK_NULL,
1157         CLK_TOP_CLK_NULL,
1158         CLK_TOP_TVDPLL_D8,
1159         CLK_TOP_CLK_NULL,
1160         CLK_TOP_CLK_NULL,
1161         CLK_TOP_CLK_NULL,
1162         CLK_TOP_CLK_NULL,
1163         CLK_TOP_CLK_NULL,
1164         CLK_TOP_CLK_NULL,
1165         CLK_TOP_CLK_NULL,
1166         CLK_TOP_CLK_NULL,
1167         CLK_TOP_CLK_NULL,
1168         CLK_TOP_CLK_NULL,
1169         CLK_TOP_CLK_NULL,
1170         CLK_TOP_CLK_NULL,
1171         CLK_TOP_CLK_NULL,
1172         CLK_TOP_CLK_NULL,
1173         CLK_TOP_CLK_NULL,
1174         CLK_TOP_TVDPLL_D16
1175 };
1176
1177 static const struct mtk_composite top_muxes[] = {
1178         /* CLK_MUX_SEL0 */
1179         MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
1180         MUX(CLK_TOP_EMI1X_SEL, emi1x_parents, 0x000, 1, 1),
1181         MUX(CLK_TOP_EMI_DDRPHY_SEL, emi_ddrphy_parents, 0x000, 2, 1),
1182         MUX(CLK_TOP_MSDC1_SEL, msdc1_parents, 0x000, 4, 8),
1183         MUX(CLK_TOP_PWM_MM_SEL, pwm_mm_parents, 0x000, 18, 1),
1184         MUX(CLK_TOP_UART1_SEL, uart0_parents, 0x000, 19, 1),
1185         MUX(CLK_TOP_SPM_52M_SEL, uart0_parents, 0x000, 22, 1),
1186         MUX(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x000, 23, 3),
1187         /* CLK_MUX_SEL1 */
1188         MUX(CLK_TOP_NFI2X_SEL, nfi2x_parents, 0x004, 0, 3),
1189         MUX(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x004, 15, 1),
1190         MUX(CLK_TOP_SMI_SEL, smi_parents, 0x004, 16, 4),
1191         MUX(CLK_TOP_USB_SEL, usb_parents, 0x004, 20, 3),
1192         /* CLK_MUX_SEL8 */
1193         MUX(CLK_TOP_SPINOR_SEL, spinor_parents, 0x040, 0, 3),
1194         MUX(CLK_TOP_ETH_SEL, eth_parents, 0x040, 6, 3),
1195         MUX(CLK_TOP_AUD1_SEL, aud1_parents, 0x040, 22, 1),
1196         MUX(CLK_TOP_AUD2_SEL, aud2_parents, 0x040, 23, 1),
1197         MUX(CLK_TOP_I2C_SEL, i2c_parents, 0x040, 28, 3),
1198         /* CLK_SEL_9 */
1199         MUX(CLK_TOP_AUD_I2S0_M_SEL, aud_i2s0_m_parents, 0x044, 12, 1),
1200         MUX(CLK_TOP_AUD_I2S3_M_SEL, aud_i2s0_m_parents, 0x044, 15, 1),
1201         MUX(CLK_TOP_AUD_I2S4_M_SEL, aud_i2s0_m_parents, 0x044, 16, 1),
1202         MUX(CLK_TOP_AUD_I2S6_M_SEL, aud_i2s0_m_parents, 0x044, 18, 1),
1203         /* CLK_MUX_SEL13 */
1204         MUX(CLK_TOP_PWM_SEL, pwm_mm_parents, 0x07c, 0, 1),
1205         MUX(CLK_TOP_AUD_SPDIFIN_SEL, aud_spdifin_parents, 0x07c, 2, 2),
1206         MUX(CLK_TOP_UART2_SEL, uart0_parents, 0x07c, 4, 1),
1207         MUX(CLK_TOP_DBG_ATCLK_SEL, dbg_atclk_parents, 0x07c, 7, 3),
1208         MUX(CLK_TOP_PNG_SYS_SEL, png_sys_parents, 0x07c, 16, 3),
1209         MUX(CLK_TOP_SEJ_13M_SEL, sej_13m_parents, 0x07c, 22, 1),
1210         /* CLK_MUX_SEL14 */
1211         MUX(CLK_TOP_IMGRZ_SYS_SEL, imgrz_sys_parents, 0xc0, 0, 3),
1212         MUX(CLK_TOP_GRAPH_ECLK_SEL, graph_eclk_parents, 0xc0, 8, 4),
1213         MUX(CLK_TOP_FDBI_SEL, fdbi_parents, 0xc0, 12, 4),
1214         MUX(CLK_TOP_FAUDIO_SEL, faudio_parents, 0xc0, 16, 2),
1215         MUX(CLK_TOP_FA2SYS_SEL, fa2sys_parents, 0xc0, 24, 3),
1216         MUX(CLK_TOP_FA1SYS_SEL, fa1sys_parents, 0xc0, 27, 3),
1217         MUX(CLK_TOP_FASM_M_SEL, fasm_m_parents, 0xc0, 30, 2),
1218         /* CLK_MUX_SEL15 */
1219         MUX(CLK_TOP_FASM_H_SEL, fasm_m_parents, 0xC4, 0, 2),
1220         MUX(CLK_TOP_FASM_L_SEL, fasm_m_parents, 0xC4, 2, 2),
1221         MUX(CLK_TOP_FECC_CK_SEL, fecc_ck_parents, 0xC4, 18, 6),
1222         MUX(CLK_TOP_PE2_MAC_SEL, pe2_mac_parents, 0xC4, 24, 3),
1223         MUX(CLK_TOP_CMSYS_SEL, cmsys_parents, 0xC4, 28, 3),
1224         /* CLK_MUX_SEL16 */
1225         MUX(CLK_TOP_GCPU_SEL, gcpu_parents, 0xC8, 0, 3),
1226         MUX(CLK_TOP_SPIS_CK_SEL, spis_ck_parents, 0xC8, 4, 8),
1227         /* CLK_MUX_SEL17 */
1228         MUX(CLK_TOP_APLL1_REF_SEL, apll1_ref_parents, 0xCC, 6, 3),
1229         MUX(CLK_TOP_APLL2_REF_SEL, apll1_ref_parents, 0xCC, 9, 3),
1230         MUX(CLK_TOP_INT_32K_SEL, int_32k_parents, 0xCC, 12, 1),
1231         MUX(CLK_TOP_APLL1_SRC_SEL, apll1_src_parents, 0xCC, 13, 2),
1232         MUX(CLK_TOP_APLL2_SRC_SEL, apll2_src_parents, 0xCC, 15, 2),
1233         /* CLK_MUX_SEL19 */
1234         MUX(CLK_TOP_FAUD_INTBUS_SEL, faud_intbus_parents, 0xD4, 8, 8),
1235         MUX(CLK_TOP_AXIBUS_SEL, axibus_parents, 0xD4, 24, 8),
1236         /* CLK_MUX_SEL21 */
1237         MUX(CLK_TOP_HAPLL1_SEL, hapll1_parents, 0xDC, 0, 4),
1238         MUX(CLK_TOP_HAPLL2_SEL, hapll2_parents, 0xDC, 4, 4),
1239         MUX(CLK_TOP_SPINFI_SEL, spinfi_parents, 0xDC, 8, 4),
1240         /* CLK_MUX_SEL22 */
1241         MUX(CLK_TOP_MSDC0_SEL, msdc0_parents, 0xF4, 0, 8),
1242         MUX(CLK_TOP_MSDC0_CLK50_SEL, msdc0_clk50_parents, 0xF4, 8, 6),
1243         MUX(CLK_TOP_MSDC2_SEL, msdc2_parents, 0xF4, 15, 8),
1244         MUX(CLK_TOP_MSDC2_CLK50_SEL, msdc0_clk50_parents, 0xF4, 23, 6),
1245         /* CLK_MUX_SEL23 */
1246         MUX(CLK_TOP_DISP_DPI_CK_SEL, disp_dpi_ck_parents, 0xF8, 0, 6),
1247         MUX(CLK_TOP_SPI1_SEL, spis_ck_parents, 0xF8, 6, 8),
1248         MUX(CLK_TOP_SPI2_SEL, spis_ck_parents, 0xF8, 14, 8),
1249         MUX(CLK_TOP_SPI3_SEL, spis_ck_parents, 0xF8, 22, 8),
1250 };
1251
1252 static const struct mtk_gate_regs top0_cg_regs = {
1253         .set_ofs = 0x50,
1254         .clr_ofs = 0x80,
1255         .sta_ofs = 0x20,
1256 };
1257
1258 static const struct mtk_gate_regs top1_cg_regs = {
1259         .set_ofs = 0x54,
1260         .clr_ofs = 0x84,
1261         .sta_ofs = 0x24,
1262 };
1263
1264 static const struct mtk_gate_regs top2_cg_regs = {
1265         .set_ofs = 0x6c,
1266         .clr_ofs = 0x9c,
1267         .sta_ofs = 0x3c,
1268 };
1269
1270 static const struct mtk_gate_regs top3_cg_regs = {
1271         .set_ofs = 0x44,
1272         .clr_ofs = 0x44,
1273         .sta_ofs = 0x44,
1274 };
1275
1276 static const struct mtk_gate_regs top4_cg_regs = {
1277         .set_ofs = 0xa0,
1278         .clr_ofs = 0xb0,
1279         .sta_ofs = 0x70,
1280 };
1281
1282 static const struct mtk_gate_regs top5_cg_regs = {
1283         .set_ofs = 0x120,
1284         .clr_ofs = 0x140,
1285         .sta_ofs = 0xe0,
1286 };
1287
1288 static const struct mtk_gate_regs top6_cg_regs = {
1289         .set_ofs = 0x128,
1290         .clr_ofs = 0x148,
1291         .sta_ofs = 0xe8,
1292 };
1293
1294 static const struct mtk_gate_regs top7_cg_regs = {
1295         .set_ofs = 0x12c,
1296         .clr_ofs = 0x14c,
1297         .sta_ofs = 0xec,
1298 };
1299
1300 #define GATE_TOP0(_id, _parent, _shift) {                       \
1301                 .id = _id,                                      \
1302                 .parent = _parent,                              \
1303                 .regs = &top0_cg_regs,                          \
1304                 .shift = _shift,                                \
1305                 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
1306         }
1307
1308 #define GATE_TOP1(_id, _parent, _shift) {                       \
1309                 .id = _id,                                      \
1310                 .parent = _parent,                              \
1311                 .regs = &top1_cg_regs,                          \
1312                 .shift = _shift,                                \
1313                 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
1314         }
1315
1316 #define GATE_TOP2(_id, _parent, _shift) {                       \
1317                 .id = _id,                                      \
1318                 .parent = _parent,                              \
1319                 .regs = &top2_cg_regs,                          \
1320                 .shift = _shift,                                \
1321                 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
1322         }
1323
1324 #define GATE_TOP2_I(_id, _parent, _shift) {                             \
1325                 .id = _id,                                              \
1326                 .parent = _parent,                                      \
1327                 .regs = &top2_cg_regs,                                  \
1328                 .shift = _shift,                                        \
1329                 .flags = CLK_GATE_SETCLR_INV | CLK_PARENT_TOPCKGEN,     \
1330         }
1331
1332 #define GATE_TOP3(_id, _parent, _shift) {                       \
1333                 .id = _id,                                      \
1334                 .parent = _parent,                              \
1335                 .regs = &top3_cg_regs,                          \
1336                 .shift = _shift,                                \
1337                 .flags = CLK_GATE_NO_SETCLR | CLK_PARENT_TOPCKGEN,      \
1338         }
1339
1340 #define GATE_TOP4(_id, _parent, _shift) {                               \
1341                 .id = _id,                                              \
1342                 .parent = _parent,                                      \
1343                 .regs = &top4_cg_regs,                                  \
1344                 .shift = _shift,                                        \
1345                 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
1346         }
1347
1348 #define GATE_TOP5(_id, _parent, _shift) {                               \
1349                 .id = _id,                                              \
1350                 .parent = _parent,                                      \
1351                 .regs = &top5_cg_regs,                                  \
1352                 .shift = _shift,                                        \
1353                 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
1354         }
1355
1356 #define GATE_TOP5_I(_id, _parent, _shift) {                             \
1357                 .id = _id,                                              \
1358                 .parent = _parent,                                      \
1359                 .regs = &top5_cg_regs,                                  \
1360                 .shift = _shift,                                        \
1361                 .flags = CLK_GATE_SETCLR_INV | CLK_PARENT_TOPCKGEN,     \
1362         }
1363
1364 #define GATE_TOP6(_id, _parent, _shift) {                               \
1365                 .id = _id,                                              \
1366                 .parent = _parent,                                      \
1367                 .regs = &top6_cg_regs,                                  \
1368                 .shift = _shift,                                        \
1369                 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
1370         }
1371
1372 #define GATE_TOP7(_id, _parent, _shift) {                               \
1373                 .id = _id,                                              \
1374                 .parent = _parent,                                      \
1375                 .regs = &top7_cg_regs,                                  \
1376                 .shift = _shift,                                        \
1377                 .flags = CLK_GATE_SETCLR_INV | CLK_PARENT_TOPCKGEN,     \
1378         }
1379
1380 static const struct mtk_gate top_clks[] = {
1381         /* TOP0 */
1382         GATE_TOP0(CLK_TOP_PWM_MM, CLK_TOP_PWM_MM_SEL, 0),
1383         GATE_TOP0(CLK_TOP_SMI, CLK_TOP_SMI_SEL, 9),
1384         GATE_TOP0(CLK_TOP_SPI2, CLK_TOP_SPI2_SEL, 10),
1385         GATE_TOP0(CLK_TOP_SPI3, CLK_TOP_SPI3_SEL, 11),
1386         GATE_TOP0(CLK_TOP_SPINFI, CLK_TOP_SPINFI_SEL, 12),
1387         GATE_TOP0(CLK_TOP_26M_DEBUG, CLK_TOP_CLK26M, 16),
1388         GATE_TOP0(CLK_TOP_USB_48M_DEBUG, CLK_TOP_USB20_48M, 17),
1389         GATE_TOP0(CLK_TOP_52M_DEBUG, CLK_TOP_UNIVPLL_D24, 18),
1390         GATE_TOP0(CLK_TOP_32K_DEBUG, CLK_TOP_INT_32K_SEL, 19),
1391         /* TOP1 */
1392         GATE_TOP1(CLK_TOP_THERM, CLK_TOP_AXIBUS_SEL, 1),
1393         GATE_TOP1(CLK_TOP_APDMA, CLK_TOP_AXIBUS_SEL, 2),
1394         GATE_TOP1(CLK_TOP_I2C0, CLK_TOP_AHB_INFRA_D2, 3),
1395         GATE_TOP1(CLK_TOP_I2C1, CLK_TOP_AHB_INFRA_D2, 4),
1396         GATE_TOP1(CLK_TOP_AUXADC1, CLK_TOP_CLK26M, 5),
1397         GATE_TOP1(CLK_TOP_NFI, CLK_TOP_NFI1X_INFRA_BCLK, 6),
1398         GATE_TOP1(CLK_TOP_NFIECC, CLK_TOP_AXIBUS_SEL, 7),
1399         GATE_TOP1(CLK_TOP_DEBUGSYS, CLK_TOP_DBG_ATCLK_SEL, 8),
1400         GATE_TOP1(CLK_TOP_PWM, CLK_TOP_AXIBUS_SEL, 9),
1401         GATE_TOP1(CLK_TOP_UART0, CLK_TOP_UART0_SEL, 10),
1402         GATE_TOP1(CLK_TOP_UART1, CLK_TOP_UART1_SEL, 11),
1403         GATE_TOP1(CLK_TOP_USB, CLK_TOP_USB_B, 13),
1404         GATE_TOP1(CLK_TOP_FLASHIF_26M, CLK_TOP_CLK26M, 14),
1405         GATE_TOP1(CLK_TOP_AUXADC2, CLK_TOP_CLK26M, 15),
1406         GATE_TOP1(CLK_TOP_I2C2, CLK_TOP_AHB_INFRA_D2, 16),
1407         GATE_TOP1(CLK_TOP_MSDC0, CLK_TOP_MSDC0_SEL, 17),
1408         GATE_TOP1(CLK_TOP_MSDC1, CLK_TOP_MSDC1_SEL, 18),
1409         GATE_TOP1(CLK_TOP_NFI2X, CLK_TOP_NFI2X_SEL, 19),
1410         GATE_TOP1(CLK_TOP_MEMSLP_DLYER, CLK_TOP_CLK26M, 22),
1411         GATE_TOP1(CLK_TOP_SPI, CLK_TOP_SPI1_SEL, 23),
1412         GATE_TOP1(CLK_TOP_APXGPT, CLK_TOP_CLK26M, 24),
1413         GATE_TOP1(CLK_TOP_PMICWRAP_MD, CLK_TOP_CLK26M, 27),
1414         GATE_TOP1(CLK_TOP_PMICWRAP_CONN, CLK_TOP_PMICSPI_SEL, 28),
1415         GATE_TOP1(CLK_TOP_PMIC_SYSCK, CLK_TOP_CLK26M, 29),
1416         GATE_TOP1(CLK_TOP_AUX_ADC, CLK_TOP_CLK26M, 30),
1417         GATE_TOP1(CLK_TOP_AUX_TP, CLK_TOP_CLK26M, 31),
1418         /* TOP2 */
1419         GATE_TOP2(CLK_TOP_RBIST, CLK_TOP_UNIVPLL_D12, 1),
1420         GATE_TOP2(CLK_TOP_NFI_BUS, CLK_TOP_AXIBUS_SEL, 2),
1421         GATE_TOP2(CLK_TOP_GCE, CLK_TOP_AXIBUS_SEL, 4),
1422         GATE_TOP2(CLK_TOP_TRNG, CLK_TOP_AXIBUS_SEL, 5),
1423         GATE_TOP2(CLK_TOP_PWM_B, CLK_TOP_PWM_SEL, 8),
1424         GATE_TOP2(CLK_TOP_PWM1_FB, CLK_TOP_PWM_SEL, 9),
1425         GATE_TOP2(CLK_TOP_PWM2_FB, CLK_TOP_PWM_SEL, 10),
1426         GATE_TOP2(CLK_TOP_PWM3_FB, CLK_TOP_PWM_SEL, 11),
1427         GATE_TOP2(CLK_TOP_PWM4_FB, CLK_TOP_PWM_SEL, 12),
1428         GATE_TOP2(CLK_TOP_PWM5_FB, CLK_TOP_PWM_SEL, 13),
1429         GATE_TOP2(CLK_TOP_FLASHIF_FREERUN, CLK_TOP_AXIBUS_SEL, 15),
1430         GATE_TOP2(CLK_TOP_CQDMA, CLK_TOP_AXIBUS_SEL, 17),
1431         GATE_TOP2(CLK_TOP_66M_ETH, CLK_TOP_AXIBUS_SEL, 19),
1432         GATE_TOP2(CLK_TOP_133M_ETH, CLK_TOP_AXIBUS_SEL, 20),
1433         GATE_TOP2(CLK_TOP_FLASHIF_AXI, CLK_TOP_SPI1_SEL, 23),
1434         GATE_TOP2(CLK_TOP_USBIF, CLK_TOP_AXIBUS_SEL, 24),
1435         GATE_TOP2(CLK_TOP_UART2, CLK_TOP_RG_UART2, 25),
1436         GATE_TOP2(CLK_TOP_GCPU_B, CLK_TOP_AXIBUS_SEL, 27),
1437         GATE_TOP2_I(CLK_TOP_MSDC0_B, CLK_TOP_MSDC0, 28),
1438         GATE_TOP2_I(CLK_TOP_MSDC1_B, CLK_TOP_MSDC1, 29),
1439         GATE_TOP2_I(CLK_TOP_MSDC2_B, CLK_TOP_MSDC2, 30),
1440         GATE_TOP2(CLK_TOP_USB_B, CLK_TOP_USB_SEL, 31),
1441         /* TOP3 */
1442         GATE_TOP3(CLK_TOP_APLL12_DIV0, CLK_TOP_APLL12_CK_DIV0, 0),
1443         GATE_TOP3(CLK_TOP_APLL12_DIV3, CLK_TOP_APLL12_CK_DIV3, 3),
1444         GATE_TOP3(CLK_TOP_APLL12_DIV4, CLK_TOP_APLL12_CK_DIV4, 4),
1445         GATE_TOP3(CLK_TOP_APLL12_DIV6, CLK_TOP_APLL12_CK_DIV6, 8),
1446         /* TOP4 */
1447         GATE_TOP4(CLK_TOP_SPINOR, CLK_TOP_SPINOR_SEL, 0),
1448         GATE_TOP4(CLK_TOP_MSDC2, CLK_TOP_MSDC2_SEL, 1),
1449         GATE_TOP4(CLK_TOP_ETH, CLK_TOP_ETH_SEL, 2),
1450         GATE_TOP4(CLK_TOP_AUD1, CLK_TOP_AUD1_SEL, 8),
1451         GATE_TOP4(CLK_TOP_AUD2, CLK_TOP_AUD2_SEL, 9),
1452         GATE_TOP4(CLK_TOP_I2C, CLK_TOP_I2C_SEL, 12),
1453         GATE_TOP4(CLK_TOP_PWM_INFRA, CLK_TOP_PWM_SEL, 13),
1454         GATE_TOP4(CLK_TOP_AUD_SPDIF_IN, CLK_TOP_AUD_SPDIFIN_SEL, 14),
1455         GATE_TOP4(CLK_TOP_RG_UART2, CLK_TOP_UART2_SEL, 15),
1456         GATE_TOP4(CLK_TOP_DBG_AT, CLK_TOP_DBG_ATCLK_SEL, 17),
1457         /* TOP5 */
1458         GATE_TOP5_I(CLK_TOP_IMGRZ_SYS, CLK_TOP_IMGRZ_SYS_SEL, 0),
1459         GATE_TOP5_I(CLK_TOP_PNG_SYS, CLK_TOP_PNG_SYS_SEL, 1),
1460         GATE_TOP5_I(CLK_TOP_GRAPH_E, CLK_TOP_GRAPH_ECLK_SEL, 2),
1461         GATE_TOP5_I(CLK_TOP_FDBI, CLK_TOP_FDBI_SEL, 3),
1462         GATE_TOP5_I(CLK_TOP_FAUDIO, CLK_TOP_FAUDIO_SEL, 4),
1463         GATE_TOP5_I(CLK_TOP_FAUD_INTBUS, CLK_TOP_FAUD_INTBUS_SEL, 5),
1464         GATE_TOP5_I(CLK_TOP_HAPLL1, CLK_TOP_HAPLL1_SEL, 6),
1465         GATE_TOP5_I(CLK_TOP_HAPLL2, CLK_TOP_HAPLL2_SEL, 7),
1466         GATE_TOP5_I(CLK_TOP_FA2SYS, CLK_TOP_FA2SYS_SEL, 8),
1467         GATE_TOP5_I(CLK_TOP_FA1SYS, CLK_TOP_FA1SYS_SEL, 9),
1468         GATE_TOP5_I(CLK_TOP_FASM_L, CLK_TOP_FASM_L_SEL, 10),
1469         GATE_TOP5_I(CLK_TOP_FASM_M, CLK_TOP_FASM_M_SEL, 11),
1470         GATE_TOP5_I(CLK_TOP_FASM_H, CLK_TOP_FASM_H_SEL, 12),
1471         GATE_TOP5_I(CLK_TOP_FECC, CLK_TOP_FECC_CK_SEL, 23),
1472         GATE_TOP5_I(CLK_TOP_PE2_MAC, CLK_TOP_PE2_MAC_SEL, 24),
1473         GATE_TOP5_I(CLK_TOP_CMSYS, CLK_TOP_CMSYS_SEL, 25),
1474         GATE_TOP5_I(CLK_TOP_GCPU, CLK_TOP_GCPU_SEL, 26),
1475         GATE_TOP5(CLK_TOP_SPIS, CLK_TOP_SPIS_CK_SEL, 27),
1476         /* TOP6 */
1477         GATE_TOP6(CLK_TOP_I2C3, CLK_TOP_AHB_INFRA_D2, 0),
1478         GATE_TOP6(CLK_TOP_SPI_SLV_B, CLK_TOP_SPIS_CK_SEL, 1),
1479         GATE_TOP6(CLK_TOP_SPI_SLV_BUS, CLK_TOP_AXIBUS_SEL, 2),
1480         GATE_TOP6(CLK_TOP_PCIE_MAC_BUS, CLK_TOP_AXIBUS_SEL, 3),
1481         GATE_TOP6(CLK_TOP_CMSYS_BUS, CLK_TOP_AXIBUS_SEL, 4),
1482         GATE_TOP6(CLK_TOP_ECC_B, CLK_TOP_AXIBUS_SEL, 5),
1483         GATE_TOP6(CLK_TOP_PCIE_PHY_BUS, CLK_TOP_CLK26M, 6),
1484         GATE_TOP6(CLK_TOP_PCIE_AUX, CLK_TOP_CLK26M, 7),
1485         /* TOP7 */
1486         GATE_TOP7(CLK_TOP_DISP_DPI, CLK_TOP_DISP_DPI_CK_SEL, 0),
1487 };
1488
1489 static const struct mtk_clk_tree mt8518_clk_tree = {
1490         .xtal_rate = 26 * MHZ,
1491         .xtal2_rate = 26 * MHZ,
1492         .fdivs_offs = CLK_TOP_DMPLL,
1493         .muxes_offs = CLK_TOP_UART0_SEL,
1494         .plls = apmixed_plls,
1495         .fclks = top_fixed_clks,
1496         .fdivs = top_fixed_divs,
1497         .muxes = top_muxes,
1498 };
1499
1500 static int mt8518_apmixedsys_probe(struct udevice *dev)
1501 {
1502         return mtk_common_clk_init(dev, &mt8518_clk_tree);
1503 }
1504
1505 static int mt8518_topckgen_probe(struct udevice *dev)
1506 {
1507         return mtk_common_clk_init(dev, &mt8518_clk_tree);
1508 }
1509
1510 static int mt8518_topckgen_cg_probe(struct udevice *dev)
1511 {
1512         return mtk_common_clk_gate_init(dev, &mt8518_clk_tree, top_clks);
1513 }
1514
1515 static const struct udevice_id mt8518_apmixed_compat[] = {
1516         { .compatible = "mediatek,mt8518-apmixedsys", },
1517         { }
1518 };
1519
1520 static const struct udevice_id mt8518_topckgen_compat[] = {
1521         { .compatible = "mediatek,mt8518-topckgen", },
1522         { }
1523 };
1524
1525 static const struct udevice_id mt8518_topckgen_cg_compat[] = {
1526         { .compatible = "mediatek,mt8518-topckgen-cg", },
1527         { }
1528 };
1529
1530 U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
1531         .name = "mt8518-apmixedsys",
1532         .id = UCLASS_CLK,
1533         .of_match = mt8518_apmixed_compat,
1534         .probe = mt8518_apmixedsys_probe,
1535         .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
1536         .ops = &mtk_clk_apmixedsys_ops,
1537         .flags = DM_FLAG_PRE_RELOC,
1538 };
1539
1540 U_BOOT_DRIVER(mtk_clk_topckgen) = {
1541         .name = "mt8518-topckgen",
1542         .id = UCLASS_CLK,
1543         .of_match = mt8518_topckgen_compat,
1544         .probe = mt8518_topckgen_probe,
1545         .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
1546         .ops = &mtk_clk_topckgen_ops,
1547         .flags = DM_FLAG_PRE_RELOC,
1548 };
1549
1550 U_BOOT_DRIVER(mtk_clk_topckgen_cg) = {
1551         .name = "mt8518-topckgen-cg",
1552         .id = UCLASS_CLK,
1553         .of_match = mt8518_topckgen_cg_compat,
1554         .probe = mt8518_topckgen_cg_probe,
1555         .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
1556         .ops = &mtk_clk_gate_ops,
1557         .flags = DM_FLAG_PRE_RELOC,
1558 };