drivers/clk/mediatek/clk-mt7622-aud.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2017 MediaTek Inc.
   4  * Author: Chen Zhong <chen.zhong@mediatek.com>
   5  *         Sean Wang <sean.wang@mediatek.com>
   6  */
   7
   8 #include <linux/clk-provider.h>
   9 #include <linux/of.h>
  10 #include <linux/of_address.h>
  11 #include <linux/of_device.h>
  12 #include <linux/platform_device.h>
  13
  14 #include "clk-mtk.h"
  15 #include "clk-gate.h"
  16
  17 #include <dt-bindings/clock/mt7622-clk.h>
  18
  19 #define GATE_AUDIO0(_id, _name, _parent, _shift) {      \
  20                 .id = _id,                              \
  21                 .name = _name,                          \
  22                 .parent_name = _parent,                 \
  23                 .regs = &audio0_cg_regs,                        \
  24                 .shift = _shift,                        \
  25                 .ops = &mtk_clk_gate_ops_no_setclr,     \
  26         }
  27
  28 #define GATE_AUDIO1(_id, _name, _parent, _shift) {      \
  29                 .id = _id,                              \
  30                 .name = _name,                          \
  31                 .parent_name = _parent,                 \
  32                 .regs = &audio1_cg_regs,                        \
  33                 .shift = _shift,                        \
  34                 .ops = &mtk_clk_gate_ops_no_setclr,     \
  35         }
  36
  37 #define GATE_AUDIO2(_id, _name, _parent, _shift) {      \
  38                 .id = _id,                              \
  39                 .name = _name,                          \
  40                 .parent_name = _parent,                 \
  41                 .regs = &audio2_cg_regs,                        \
  42                 .shift = _shift,                        \
  43                 .ops = &mtk_clk_gate_ops_no_setclr,     \
  44         }
  45
  46 #define GATE_AUDIO3(_id, _name, _parent, _shift) {      \
  47                 .id = _id,                              \
  48                 .name = _name,                          \
  49                 .parent_name = _parent,                 \
  50                 .regs = &audio3_cg_regs,                        \
  51                 .shift = _shift,                        \
  52                 .ops = &mtk_clk_gate_ops_no_setclr,     \
  53         }
  54
  55 static const struct mtk_gate_regs audio0_cg_regs = {
  56         .set_ofs = 0x0,
  57         .clr_ofs = 0x0,
  58         .sta_ofs = 0x0,
  59 };
  60
  61 static const struct mtk_gate_regs audio1_cg_regs = {
  62         .set_ofs = 0x10,
  63         .clr_ofs = 0x10,
  64         .sta_ofs = 0x10,
  65 };
  66
  67 static const struct mtk_gate_regs audio2_cg_regs = {
  68         .set_ofs = 0x14,
  69         .clr_ofs = 0x14,
  70         .sta_ofs = 0x14,
  71 };
  72
  73 static const struct mtk_gate_regs audio3_cg_regs = {
  74         .set_ofs = 0x634,
  75         .clr_ofs = 0x634,
  76         .sta_ofs = 0x634,
  77 };
  78
  79 static const struct mtk_gate audio_clks[] = {
  80         /* AUDIO0 */
  81         GATE_AUDIO0(CLK_AUDIO_AFE, "audio_afe", "rtc", 2),
  82         GATE_AUDIO0(CLK_AUDIO_HDMI, "audio_hdmi", "apll1_ck_sel", 20),
  83         GATE_AUDIO0(CLK_AUDIO_SPDF, "audio_spdf", "apll1_ck_sel", 21),
  84         GATE_AUDIO0(CLK_AUDIO_APLL, "audio_apll", "apll1_ck_sel", 23),
  85         /* AUDIO1 */
  86         GATE_AUDIO1(CLK_AUDIO_I2SIN1, "audio_i2sin1", "a1sys_hp_sel", 0),
  87         GATE_AUDIO1(CLK_AUDIO_I2SIN2, "audio_i2sin2", "a1sys_hp_sel", 1),
  88         GATE_AUDIO1(CLK_AUDIO_I2SIN3, "audio_i2sin3", "a1sys_hp_sel", 2),
  89         GATE_AUDIO1(CLK_AUDIO_I2SIN4, "audio_i2sin4", "a1sys_hp_sel", 3),
  90         GATE_AUDIO1(CLK_AUDIO_I2SO1, "audio_i2so1", "a1sys_hp_sel", 6),
  91         GATE_AUDIO1(CLK_AUDIO_I2SO2, "audio_i2so2", "a1sys_hp_sel", 7),
  92         GATE_AUDIO1(CLK_AUDIO_I2SO3, "audio_i2so3", "a1sys_hp_sel", 8),
  93         GATE_AUDIO1(CLK_AUDIO_I2SO4, "audio_i2so4", "a1sys_hp_sel", 9),
  94         GATE_AUDIO1(CLK_AUDIO_ASRCI1, "audio_asrci1", "asm_h_sel", 12),
  95         GATE_AUDIO1(CLK_AUDIO_ASRCI2, "audio_asrci2", "asm_h_sel", 13),
  96         GATE_AUDIO1(CLK_AUDIO_ASRCO1, "audio_asrco1", "asm_h_sel", 14),
  97         GATE_AUDIO1(CLK_AUDIO_ASRCO2, "audio_asrco2", "asm_h_sel", 15),
  98         GATE_AUDIO1(CLK_AUDIO_INTDIR, "audio_intdir", "intdir_sel", 20),
  99         GATE_AUDIO1(CLK_AUDIO_A1SYS, "audio_a1sys", "a1sys_hp_sel", 21),
 100         GATE_AUDIO1(CLK_AUDIO_A2SYS, "audio_a2sys", "a2sys_hp_sel", 22),
 101         GATE_AUDIO1(CLK_AUDIO_AFE_CONN, "audio_afe_conn", "a1sys_hp_sel", 23),
 102         /* AUDIO2 */
 103         GATE_AUDIO2(CLK_AUDIO_UL1, "audio_ul1", "a1sys_hp_sel", 0),
 104         GATE_AUDIO2(CLK_AUDIO_UL2, "audio_ul2", "a1sys_hp_sel", 1),
 105         GATE_AUDIO2(CLK_AUDIO_UL3, "audio_ul3", "a1sys_hp_sel", 2),
 106         GATE_AUDIO2(CLK_AUDIO_UL4, "audio_ul4", "a1sys_hp_sel", 3),
 107         GATE_AUDIO2(CLK_AUDIO_UL5, "audio_ul5", "a1sys_hp_sel", 4),
 108         GATE_AUDIO2(CLK_AUDIO_UL6, "audio_ul6", "a1sys_hp_sel", 5),
 109         GATE_AUDIO2(CLK_AUDIO_DL1, "audio_dl1", "a1sys_hp_sel", 6),
 110         GATE_AUDIO2(CLK_AUDIO_DL2, "audio_dl2", "a1sys_hp_sel", 7),
 111         GATE_AUDIO2(CLK_AUDIO_DL3, "audio_dl3", "a1sys_hp_sel", 8),
 112         GATE_AUDIO2(CLK_AUDIO_DL4, "audio_dl4", "a1sys_hp_sel", 9),
 113         GATE_AUDIO2(CLK_AUDIO_DL5, "audio_dl5", "a1sys_hp_sel", 10),
 114         GATE_AUDIO2(CLK_AUDIO_DL6, "audio_dl6", "a1sys_hp_sel", 11),
 115         GATE_AUDIO2(CLK_AUDIO_DLMCH, "audio_dlmch", "a1sys_hp_sel", 12),
 116         GATE_AUDIO2(CLK_AUDIO_ARB1, "audio_arb1", "a1sys_hp_sel", 13),
 117         GATE_AUDIO2(CLK_AUDIO_AWB, "audio_awb", "a1sys_hp_sel", 14),
 118         GATE_AUDIO2(CLK_AUDIO_AWB2, "audio_awb2", "a1sys_hp_sel", 15),
 119         GATE_AUDIO2(CLK_AUDIO_DAI, "audio_dai", "a1sys_hp_sel", 16),
 120         GATE_AUDIO2(CLK_AUDIO_MOD, "audio_mod", "a1sys_hp_sel", 17),
 121         /* AUDIO3 */
 122         GATE_AUDIO3(CLK_AUDIO_ASRCI3, "audio_asrci3", "asm_h_sel", 2),
 123         GATE_AUDIO3(CLK_AUDIO_ASRCI4, "audio_asrci4", "asm_h_sel", 3),
 124         GATE_AUDIO3(CLK_AUDIO_ASRCO3, "audio_asrco3", "asm_h_sel", 6),
 125         GATE_AUDIO3(CLK_AUDIO_ASRCO4, "audio_asrco4", "asm_h_sel", 7),
 126         GATE_AUDIO3(CLK_AUDIO_MEM_ASRC1, "audio_mem_asrc1", "asm_h_sel", 10),
 127         GATE_AUDIO3(CLK_AUDIO_MEM_ASRC2, "audio_mem_asrc2", "asm_h_sel", 11),
 128         GATE_AUDIO3(CLK_AUDIO_MEM_ASRC3, "audio_mem_asrc3", "asm_h_sel", 12),
 129         GATE_AUDIO3(CLK_AUDIO_MEM_ASRC4, "audio_mem_asrc4", "asm_h_sel", 13),
 130         GATE_AUDIO3(CLK_AUDIO_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14),
 131 };
 132
 133 static int clk_mt7622_audiosys_init(struct platform_device *pdev)
 134 {
 135         struct clk_onecell_data *clk_data;
 136         struct device_node *node = pdev->dev.of_node;
 137         int r;
 138
 139         clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);
 140
 141         mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
 142                                clk_data);
 143
 144         r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 145         if (r) {
 146                 dev_err(&pdev->dev,
 147                         "could not register clock provider: %s: %d\n",
 148                         pdev->name, r);
 149
 150                 goto err_clk_provider;
 151         }
 152
 153         r = devm_of_platform_populate(&pdev->dev);
 154         if (r)
 155                 goto err_plat_populate;
 156
 157         return 0;
 158
 159 err_plat_populate:
 160         of_clk_del_provider(node);
 161 err_clk_provider:
 162         return r;
 163 }
 164
 165 static const struct of_device_id of_match_clk_mt7622_aud[] = {
 166         {
 167                 .compatible = "mediatek,mt7622-audsys",
 168                 .data = clk_mt7622_audiosys_init,
 169         }, {
 170                 /* sentinel */
 171         }
 172 };
 173
 174 static int clk_mt7622_aud_probe(struct platform_device *pdev)
 175 {
 176         int (*clk_init)(struct platform_device *);
 177         int r;
 178
 179         clk_init = of_device_get_match_data(&pdev->dev);
 180         if (!clk_init)
 181                 return -EINVAL;
 182
 183         r = clk_init(pdev);
 184         if (r)
 185                 dev_err(&pdev->dev,
 186                         "could not register clock provider: %s: %d\n",
 187                         pdev->name, r);
 188
 189         return r;
 190 }
 191
 192 static struct platform_driver clk_mt7622_aud_drv = {
 193         .probe = clk_mt7622_aud_probe,
 194         .driver = {
 195                 .name = "clk-mt7622-aud",
 196                 .of_match_table = of_match_clk_mt7622_aud,
 197         },
 198 };
 199
 200 builtin_platform_driver(clk_mt7622_aud_drv);