1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019 DENX Software Engineering
4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
11 #include <clk-uclass.h>
12 #include <dm/device.h>
13 #include <dm/devres.h>
14 #include <dm/uclass.h>
17 #include <linux/err.h>
19 #define UBOOT_DM_CLK_IMX_PLLV3_GENERIC "imx_clk_pllv3_generic"
20 #define UBOOT_DM_CLK_IMX_PLLV3_SYS "imx_clk_pllv3_sys"
21 #define UBOOT_DM_CLK_IMX_PLLV3_USB "imx_clk_pllv3_usb"
22 #define UBOOT_DM_CLK_IMX_PLLV3_AV "imx_clk_pllv3_av"
24 #define PLL_NUM_OFFSET 0x10
25 #define PLL_DENOM_OFFSET 0x20
27 #define BM_PLL_POWER (0x1 << 12)
28 #define BM_PLL_ENABLE (0x1 << 13)
29 #define BM_PLL_LOCK (0x1 << 31)
41 #define to_clk_pllv3(_clk) container_of(_clk, struct clk_pllv3, clk)
43 static ulong clk_pllv3_generic_get_rate(struct clk *clk)
45 struct clk_pllv3 *pll = to_clk_pllv3(dev_get_clk_ptr(clk->dev));
46 unsigned long parent_rate = clk_get_parent_rate(clk);
48 u32 div = (readl(pll->base) >> pll->div_shift) & pll->div_mask;
50 return (div == 1) ? parent_rate * 22 : parent_rate * 20;
53 static ulong clk_pllv3_generic_set_rate(struct clk *clk, ulong rate)
55 struct clk_pllv3 *pll = to_clk_pllv3(clk);
56 unsigned long parent_rate = clk_get_parent_rate(clk);
59 if (rate == parent_rate * 22)
61 else if (rate == parent_rate * 20)
66 val = readl(pll->base);
67 val &= ~(pll->div_mask << pll->div_shift);
68 val |= (div << pll->div_shift);
69 writel(val, pll->base);
71 /* Wait for PLL to lock */
72 while (!(readl(pll->base) & BM_PLL_LOCK))
78 static int clk_pllv3_generic_enable(struct clk *clk)
80 struct clk_pllv3 *pll = to_clk_pllv3(clk);
83 val = readl(pll->base);
85 val |= pll->power_bit;
87 val &= ~pll->power_bit;
89 val |= pll->enable_bit;
91 writel(val, pll->base);
96 static int clk_pllv3_generic_disable(struct clk *clk)
98 struct clk_pllv3 *pll = to_clk_pllv3(clk);
101 val = readl(pll->base);
102 if (pll->powerup_set)
103 val &= ~pll->power_bit;
105 val |= pll->power_bit;
107 val &= ~pll->enable_bit;
109 writel(val, pll->base);
114 static const struct clk_ops clk_pllv3_generic_ops = {
115 .get_rate = clk_pllv3_generic_get_rate,
116 .enable = clk_pllv3_generic_enable,
117 .disable = clk_pllv3_generic_disable,
118 .set_rate = clk_pllv3_generic_set_rate,
121 static ulong clk_pllv3_sys_get_rate(struct clk *clk)
123 struct clk_pllv3 *pll = to_clk_pllv3(clk);
124 unsigned long parent_rate = clk_get_parent_rate(clk);
125 u32 div = readl(pll->base) & pll->div_mask;
127 return parent_rate * div / 2;
130 static ulong clk_pllv3_sys_set_rate(struct clk *clk, ulong rate)
132 struct clk_pllv3 *pll = to_clk_pllv3(clk);
133 unsigned long parent_rate = clk_get_parent_rate(clk);
134 unsigned long min_rate;
135 unsigned long max_rate;
138 if (parent_rate == 0)
141 min_rate = parent_rate * 54 / 2;
142 max_rate = parent_rate * 108 / 2;
144 if (rate < min_rate || rate > max_rate)
147 div = rate * 2 / parent_rate;
148 val = readl(pll->base);
149 val &= ~pll->div_mask;
151 writel(val, pll->base);
153 /* Wait for PLL to lock */
154 while (!(readl(pll->base) & BM_PLL_LOCK))
160 static const struct clk_ops clk_pllv3_sys_ops = {
161 .enable = clk_pllv3_generic_enable,
162 .disable = clk_pllv3_generic_disable,
163 .get_rate = clk_pllv3_sys_get_rate,
164 .set_rate = clk_pllv3_sys_set_rate,
167 static ulong clk_pllv3_av_get_rate(struct clk *clk)
169 struct clk_pllv3 *pll = to_clk_pllv3(clk);
170 unsigned long parent_rate = clk_get_parent_rate(clk);
171 u32 mfn = readl(pll->base + PLL_NUM_OFFSET);
172 u32 mfd = readl(pll->base + PLL_DENOM_OFFSET);
173 u32 div = readl(pll->base) & pll->div_mask;
174 u64 temp64 = (u64)parent_rate;
182 return parent_rate * div + (unsigned long)temp64;
185 static ulong clk_pllv3_av_set_rate(struct clk *clk, ulong rate)
187 struct clk_pllv3 *pll = to_clk_pllv3(clk);
188 unsigned long parent_rate = clk_get_parent_rate(clk);
189 unsigned long min_rate;
190 unsigned long max_rate;
192 u32 mfn, mfd = 1000000;
193 u32 max_mfd = 0x3FFFFFFF;
196 if (parent_rate == 0)
199 min_rate = parent_rate * 27;
200 max_rate = parent_rate * 54;
202 if (rate < min_rate || rate > max_rate)
205 if (parent_rate <= max_mfd)
208 div = rate / parent_rate;
209 temp64 = (u64)(rate - div * parent_rate);
211 do_div(temp64, parent_rate);
214 val = readl(pll->base);
215 val &= ~pll->div_mask;
217 writel(val, pll->base);
218 writel(mfn, pll->base + PLL_NUM_OFFSET);
219 writel(mfd, pll->base + PLL_DENOM_OFFSET);
221 /* Wait for PLL to lock */
222 while (!(readl(pll->base) & BM_PLL_LOCK))
228 static const struct clk_ops clk_pllv3_av_ops = {
229 .enable = clk_pllv3_generic_enable,
230 .disable = clk_pllv3_generic_disable,
231 .get_rate = clk_pllv3_av_get_rate,
232 .set_rate = clk_pllv3_av_set_rate,
235 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
236 const char *parent_name, void __iomem *base,
239 struct clk_pllv3 *pll;
244 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
246 return ERR_PTR(-ENOMEM);
248 pll->power_bit = BM_PLL_POWER;
249 pll->enable_bit = BM_PLL_ENABLE;
252 case IMX_PLLV3_GENERIC:
253 drv_name = UBOOT_DM_CLK_IMX_PLLV3_GENERIC;
255 pll->powerup_set = false;
258 drv_name = UBOOT_DM_CLK_IMX_PLLV3_SYS;
260 pll->powerup_set = false;
263 drv_name = UBOOT_DM_CLK_IMX_PLLV3_USB;
265 pll->powerup_set = true;
268 drv_name = UBOOT_DM_CLK_IMX_PLLV3_AV;
270 pll->powerup_set = false;
274 return ERR_PTR(-ENOTSUPP);
278 pll->div_mask = div_mask;
281 ret = clk_register(clk, drv_name, name, parent_name);
290 U_BOOT_DRIVER(clk_pllv3_generic) = {
291 .name = UBOOT_DM_CLK_IMX_PLLV3_GENERIC,
293 .ops = &clk_pllv3_generic_ops,
294 .flags = DM_FLAG_PRE_RELOC,
297 U_BOOT_DRIVER(clk_pllv3_sys) = {
298 .name = UBOOT_DM_CLK_IMX_PLLV3_SYS,
300 .ops = &clk_pllv3_sys_ops,
301 .flags = DM_FLAG_PRE_RELOC,
304 U_BOOT_DRIVER(clk_pllv3_usb) = {
305 .name = UBOOT_DM_CLK_IMX_PLLV3_USB,
307 .ops = &clk_pllv3_generic_ops,
308 .flags = DM_FLAG_PRE_RELOC,
311 U_BOOT_DRIVER(clk_pllv3_av) = {
312 .name = UBOOT_DM_CLK_IMX_PLLV3_AV,
314 .ops = &clk_pllv3_av_ops,
315 .flags = DM_FLAG_PRE_RELOC,