1 // SPDX-License-Identifier: GPL-2.0+
4 * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
9 #include <clk-uclass.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/imx-regs.h>
13 #include <dt-bindings/clock/imxrt1050-clock.h>
17 static ulong imxrt1050_clk_get_rate(struct clk *clk)
22 debug("%s(#%lu)\n", __func__, clk->id);
24 ret = clk_get_by_id(clk->id, &c);
28 return clk_get_rate(c);
31 static ulong imxrt1050_clk_set_rate(struct clk *clk, ulong rate)
36 debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
38 ret = clk_get_by_id(clk->id, &c);
42 return clk_set_rate(c, rate);
45 static int __imxrt1050_clk_enable(struct clk *clk, bool enable)
50 debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
52 ret = clk_get_by_id(clk->id, &c);
64 static int imxrt1050_clk_disable(struct clk *clk)
66 return __imxrt1050_clk_enable(clk, 0);
69 static int imxrt1050_clk_enable(struct clk *clk)
71 return __imxrt1050_clk_enable(clk, 1);
74 static struct clk_ops imxrt1050_clk_ops = {
75 .set_rate = imxrt1050_clk_set_rate,
76 .get_rate = imxrt1050_clk_get_rate,
77 .enable = imxrt1050_clk_enable,
78 .disable = imxrt1050_clk_disable,
81 static const char * const pll_ref_sels[] = {"osc", "dummy", };
82 static const char * const pll1_bypass_sels[] = {"pll1_arm", "pll1_arm_ref_sel", };
83 static const char * const pll2_bypass_sels[] = {"pll2_sys", "pll2_sys_ref_sel", };
84 static const char * const pll3_bypass_sels[] = {"pll3_usb_otg", "pll3_usb_otg_ref_sel", };
85 static const char * const pll5_bypass_sels[] = {"pll5_video", "pll5_video_ref_sel", };
87 static const char *const pre_periph_sels[] = { "pll2_sys", "pll2_pfd2_396m", "pll2_pfd0_352m", "arm_podf", };
88 static const char *const periph_sels[] = { "pre_periph_sel", "todo", };
89 static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
90 static const char *const lpuart_sels[] = { "pll3_80m", "osc", };
91 static const char *const semc_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_664_62m", };
92 static const char *const semc_sels[] = { "periph_sel", "semc_alt_sel", };
93 static const char *const lcdif_sels[] = { "pll2_sys", "pll3_pfd3_454_74m", "pll5_video:", "pll2_pfd0_352m", "pll2_pfd1_594m", "pll3_pfd1_664_62m"};
95 static int imxrt1050_clk_probe(struct udevice *dev)
100 base = (void *)ANATOP_BASE_ADDR;
102 clk_dm(IMXRT1050_CLK_PLL1_REF_SEL,
103 imx_clk_mux("pll1_arm_ref_sel", base + 0x0, 14, 2,
104 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
105 clk_dm(IMXRT1050_CLK_PLL2_REF_SEL,
106 imx_clk_mux("pll2_sys_ref_sel", base + 0x30, 14, 2,
107 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
108 clk_dm(IMXRT1050_CLK_PLL3_REF_SEL,
109 imx_clk_mux("pll3_usb_otg_ref_sel", base + 0x10, 14, 2,
110 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
111 clk_dm(IMXRT1050_CLK_PLL5_REF_SEL,
112 imx_clk_mux("pll5_video_ref_sel", base + 0xa0, 14, 2,
113 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
115 clk_dm(IMXRT1050_CLK_PLL1_ARM,
116 imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_arm", "pll1_arm_ref_sel",
118 clk_dm(IMXRT1050_CLK_PLL2_SYS,
119 imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_sys", "pll2_sys_ref_sel",
121 clk_dm(IMXRT1050_CLK_PLL3_USB_OTG,
122 imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg",
123 "pll3_usb_otg_ref_sel",
125 clk_dm(IMXRT1050_CLK_PLL5_VIDEO,
126 imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "pll5_video_ref_sel",
130 clk_dm(IMXRT1050_CLK_PLL1_BYPASS,
131 imx_clk_mux_flags("pll1_bypass", base + 0x0, 16, 1,
133 ARRAY_SIZE(pll1_bypass_sels),
134 CLK_SET_RATE_PARENT));
135 clk_dm(IMXRT1050_CLK_PLL2_BYPASS,
136 imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1,
138 ARRAY_SIZE(pll2_bypass_sels),
139 CLK_SET_RATE_PARENT));
140 clk_dm(IMXRT1050_CLK_PLL3_BYPASS,
141 imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1,
143 ARRAY_SIZE(pll3_bypass_sels),
144 CLK_SET_RATE_PARENT));
145 clk_dm(IMXRT1050_CLK_PLL5_BYPASS,
146 imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1,
148 ARRAY_SIZE(pll5_bypass_sels),
149 CLK_SET_RATE_PARENT));
151 clk_dm(IMXRT1050_CLK_VIDEO_POST_DIV_SEL,
152 imx_clk_divider("video_post_div_sel", "pll5_video",
153 base + 0xa0, 19, 2));
154 clk_dm(IMXRT1050_CLK_VIDEO_DIV,
155 imx_clk_divider("video_div", "video_post_div_sel",
156 base + 0x170, 30, 2));
158 clk_dm(IMXRT1050_CLK_PLL3_80M,
159 imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6));
161 clk_dm(IMXRT1050_CLK_PLL2_PFD0_352M,
162 imx_clk_pfd("pll2_pfd0_352m", "pll2_sys", base + 0x100, 0));
163 clk_dm(IMXRT1050_CLK_PLL2_PFD1_594M,
164 imx_clk_pfd("pll2_pfd1_594m", "pll2_sys", base + 0x100, 1));
165 clk_dm(IMXRT1050_CLK_PLL2_PFD2_396M,
166 imx_clk_pfd("pll2_pfd2_396m", "pll2_sys", base + 0x100, 2));
167 clk_dm(IMXRT1050_CLK_PLL3_PFD1_664_62M,
168 imx_clk_pfd("pll3_pfd1_664_62m", "pll3_usb_otg", base + 0xf0,
170 clk_dm(IMXRT1050_CLK_PLL3_PFD3_454_74M,
171 imx_clk_pfd("pll3_pfd3_454_74m", "pll3_usb_otg", base + 0xf0,
175 base = dev_read_addr_ptr(dev);
176 if (base == (void *)FDT_ADDR_T_NONE)
179 clk_dm(IMXRT1050_CLK_ARM_PODF,
180 imx_clk_divider("arm_podf", "pll1_arm",
183 clk_dm(IMXRT1050_CLK_PRE_PERIPH_SEL,
184 imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2,
185 pre_periph_sels, ARRAY_SIZE(pre_periph_sels)));
186 clk_dm(IMXRT1050_CLK_PERIPH_SEL,
187 imx_clk_mux("periph_sel", base + 0x14, 25, 1,
188 periph_sels, ARRAY_SIZE(periph_sels)));
189 clk_dm(IMXRT1050_CLK_USDHC1_SEL,
190 imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1,
191 usdhc_sels, ARRAY_SIZE(usdhc_sels)));
192 clk_dm(IMXRT1050_CLK_USDHC2_SEL,
193 imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1,
194 usdhc_sels, ARRAY_SIZE(usdhc_sels)));
195 clk_dm(IMXRT1050_CLK_LPUART_SEL,
196 imx_clk_mux("lpuart_sel", base + 0x24, 6, 1,
197 lpuart_sels, ARRAY_SIZE(lpuart_sels)));
198 clk_dm(IMXRT1050_CLK_SEMC_ALT_SEL,
199 imx_clk_mux("semc_alt_sel", base + 0x14, 7, 1,
200 semc_alt_sels, ARRAY_SIZE(semc_alt_sels)));
201 clk_dm(IMXRT1050_CLK_SEMC_SEL,
202 imx_clk_mux("semc_sel", base + 0x14, 6, 1,
203 semc_sels, ARRAY_SIZE(semc_sels)));
204 clk_dm(IMXRT1050_CLK_LCDIF_SEL,
205 imx_clk_mux("lcdif_sel", base + 0x38, 15, 3,
206 lcdif_sels, ARRAY_SIZE(lcdif_sels)));
208 clk_dm(IMXRT1050_CLK_AHB_PODF,
209 imx_clk_divider("ahb_podf", "periph_sel",
210 base + 0x14, 10, 3));
211 clk_dm(IMXRT1050_CLK_USDHC1_PODF,
212 imx_clk_divider("usdhc1_podf", "usdhc1_sel",
213 base + 0x24, 11, 3));
214 clk_dm(IMXRT1050_CLK_USDHC2_PODF,
215 imx_clk_divider("usdhc2_podf", "usdhc2_sel",
216 base + 0x24, 16, 3));
217 clk_dm(IMXRT1050_CLK_LPUART_PODF,
218 imx_clk_divider("lpuart_podf", "lpuart_sel",
220 clk_dm(IMXRT1050_CLK_SEMC_PODF,
221 imx_clk_divider("semc_podf", "semc_sel",
222 base + 0x14, 16, 3));
223 clk_dm(IMXRT1050_CLK_LCDIF_PRED,
224 imx_clk_divider("lcdif_pred", "lcdif_sel",
225 base + 0x38, 12, 3));
226 clk_dm(IMXRT1050_CLK_LCDIF_PODF,
227 imx_clk_divider("lcdif_podf", "lcdif_pred",
228 base + 0x18, 23, 3));
230 clk_dm(IMXRT1050_CLK_USDHC1,
231 imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2));
232 clk_dm(IMXRT1050_CLK_USDHC2,
233 imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4));
234 clk_dm(IMXRT1050_CLK_LPUART1,
235 imx_clk_gate2("lpuart1", "lpuart_podf", base + 0x7c, 24));
236 clk_dm(IMXRT1050_CLK_SEMC,
237 imx_clk_gate2("semc", "semc_podf", base + 0x74, 4));
238 clk_dm(IMXRT1050_CLK_LCDIF,
239 imx_clk_gate2("lcdif", "lcdif_podf", base + 0x70, 28));
241 #ifdef CONFIG_SPL_BUILD
242 struct clk *clk, *clk1;
244 /* bypass pll1 before setting its rate */
245 clk_get_by_id(IMXRT1050_CLK_PLL1_REF_SEL, &clk);
246 clk_get_by_id(IMXRT1050_CLK_PLL1_BYPASS, &clk1);
247 clk_set_parent(clk1, clk);
249 clk_get_by_id(IMXRT1050_CLK_PLL1_ARM, &clk);
251 clk_set_rate(clk, 1056000000UL);
253 clk_get_by_id(IMXRT1050_CLK_PLL1_BYPASS, &clk1);
254 clk_set_parent(clk1, clk);
256 clk_get_by_id(IMXRT1050_CLK_SEMC_SEL, &clk1);
257 clk_get_by_id(IMXRT1050_CLK_SEMC_ALT_SEL, &clk);
258 clk_set_parent(clk1, clk);
260 clk_get_by_id(IMXRT1050_CLK_PLL2_SYS, &clk);
262 clk_set_rate(clk, 528000000UL);
264 clk_get_by_id(IMXRT1050_CLK_PLL2_BYPASS, &clk1);
265 clk_set_parent(clk1, clk);
267 /* Configure PLL3_USB_OTG to 480MHz */
268 clk_get_by_id(IMXRT1050_CLK_PLL3_USB_OTG, &clk);
270 clk_set_rate(clk, 480000000UL);
272 clk_get_by_id(IMXRT1050_CLK_PLL3_BYPASS, &clk1);
273 clk_set_parent(clk1, clk);
280 static const struct udevice_id imxrt1050_clk_ids[] = {
281 { .compatible = "fsl,imxrt1050-ccm" },
285 U_BOOT_DRIVER(imxrt1050_clk) = {
286 .name = "clk_imxrt1050",
288 .of_match = imxrt1050_clk_ids,
289 .ops = &imxrt1050_clk_ops,
290 .probe = imxrt1050_clk_probe,
291 .flags = DM_FLAG_PRE_RELOC,