drivers/clk/imx/clk-imx8mp.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2019 NXP
   4  * Peng Fan <peng.fan@nxp.com>
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <clk-uclass.h>
  10 #include <dm.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <dt-bindings/clock/imx8mp-clock.h>
  14
  15 #include "clk.h"
  16
  17 #define PLL_1416X_RATE(_rate, _m, _p, _s)               \
  18         {                                               \
  19                 .rate   =       (_rate),                \
  20                 .mdiv   =       (_m),                   \
  21                 .pdiv   =       (_p),                   \
  22                 .sdiv   =       (_s),                   \
  23         }
  24
  25 #define PLL_1443X_RATE(_rate, _m, _p, _s, _k)           \
  26         {                                               \
  27                 .rate   =       (_rate),                \
  28                 .mdiv   =       (_m),                   \
  29                 .pdiv   =       (_p),                   \
  30                 .sdiv   =       (_s),                   \
  31                 .kdiv   =       (_k),                   \
  32         }
  33
  34 static const struct imx_pll14xx_rate_table imx8mp_pll1416x_tbl[] = {
  35         PLL_1416X_RATE(1800000000U, 225, 3, 0),
  36         PLL_1416X_RATE(1600000000U, 200, 3, 0),
  37         PLL_1416X_RATE(1200000000U, 300, 3, 1),
  38         PLL_1416X_RATE(1000000000U, 250, 3, 1),
  39         PLL_1416X_RATE(800000000U,  200, 3, 1),
  40         PLL_1416X_RATE(750000000U,  250, 2, 2),
  41         PLL_1416X_RATE(700000000U,  350, 3, 2),
  42         PLL_1416X_RATE(600000000U,  300, 3, 2),
  43 };
  44
  45 static const struct imx_pll14xx_rate_table imx8mp_drampll_tbl[] = {
  46         PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
  47 };
  48
  49 static struct imx_pll14xx_clk imx8mp_dram_pll __initdata = {
  50                 .type = PLL_1443X,
  51                 .rate_table = imx8mp_drampll_tbl,
  52                 .rate_count = ARRAY_SIZE(imx8mp_drampll_tbl),
  53 };
  54
  55 static struct imx_pll14xx_clk imx8mp_arm_pll __initdata = {
  56                 .type = PLL_1416X,
  57                 .rate_table = imx8mp_pll1416x_tbl,
  58                 .rate_count = ARRAY_SIZE(imx8mp_pll1416x_tbl),
  59 };
  60
  61 static struct imx_pll14xx_clk imx8mp_sys_pll __initdata = {
  62                 .type = PLL_1416X,
  63                 .rate_table = imx8mp_pll1416x_tbl,
  64                 .rate_count = ARRAY_SIZE(imx8mp_pll1416x_tbl),
  65 };
  66
  67 static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", };
  68 static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
  69 static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
  70 static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
  71 static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
  72 static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
  73
  74 static const char *imx8mp_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m",
  75                                         "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m",
  76                                         "audio_pll1_out", "sys_pll3_out", };
  77
  78 static const char *imx8mp_main_axi_sels[] = {"clock-osc-24m", "sys_pll2_333m", "sys_pll1_800m",
  79                                              "sys_pll2_250m", "sys_pll2_1000m", "audio_pll1_out",
  80                                              "video_pll1_out", "sys_pll1_100m",};
  81
  82 static const char *imx8mp_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m",
  83                                                "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out",
  84                                                "sys_pll2_250m", "audio_pll1_out", };
  85
  86 static const char *imx8mp_noc_sels[] = {"clock-osc-24m", "sys_pll1_800m", "sys_pll3_out",
  87                                         "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out",
  88                                         "video_pll1_out", "audio_pll2_out", };
  89
  90 static const char *imx8mp_noc_io_sels[] = {"clock-osc-24m", "sys_pll1_800m", "sys_pll3_out",
  91                                            "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out",
  92                                            "video_pll1_out", "audio_pll2_out", };
  93
  94 static const char *imx8mp_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m",
  95                                         "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out",
  96                                         "audio_pll1_out", "video_pll1_out", };
  97
  98 static const char *imx8mp_dram_alt_sels[] = {"clock-osc-24m", "sys_pll1_800m", "sys_pll1_100m",
  99                                              "sys_pll2_500m", "sys_pll2_1000m", "sys_pll3_out",
 100                                              "audio_pll1_out", "sys_pll1_266m", };
 101
 102 static const char *imx8mp_dram_apb_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
 103                                              "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
 104                                              "sys_pll2_250m", "audio_pll2_out", };
 105
 106 static const char *imx8mp_i2c5_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
 107                                          "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
 108                                          "audio_pll2_out", "sys_pll1_133m", };
 109
 110 static const char *imx8mp_i2c6_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
 111                                          "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
 112                                          "audio_pll2_out", "sys_pll1_133m", };
 113
 114 static const char *imx8mp_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
 115                                            "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
 116                                            "audio_pll2_out", "sys_pll1_100m", };
 117
 118 static const char *imx8mp_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
 119                                            "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
 120                                            "audio_pll2_out", "sys_pll1_100m", };
 121
 122 static const char *imx8mp_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
 123                                          "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
 124                                          "audio_pll2_out", "sys_pll1_133m", };
 125
 126 static const char *imx8mp_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
 127                                          "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
 128                                          "audio_pll2_out", "sys_pll1_133m", };
 129
 130 static const char *imx8mp_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
 131                                          "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
 132                                          "audio_pll2_out", "sys_pll1_133m", };
 133
 134 static const char *imx8mp_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
 135                                          "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
 136                                          "audio_pll2_out", "sys_pll1_133m", };
 137
 138 static const char *imx8mp_uart1_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
 139                                           "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
 140                                           "clk_ext4", "audio_pll2_out", };
 141
 142 static const char *imx8mp_uart2_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
 143                                           "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
 144                                           "clk_ext3", "audio_pll2_out", };
 145
 146 static const char *imx8mp_uart3_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
 147                                           "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
 148                                           "clk_ext4", "audio_pll2_out", };
 149
 150 static const char *imx8mp_uart4_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
 151                                           "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
 152                                           "clk_ext3", "audio_pll2_out", };
 153
 154 static const char *imx8mp_gic_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
 155                                         "sys_pll2_100m", "sys_pll1_800m",
 156                                         "sys_pll2_500m", "clk_ext4", "audio_pll2_out" };
 157
 158 static const char *imx8mp_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m",
 159                                          "vpu_pll_out", "sys_pll2_125m", "sys_pll3_out",
 160                                          "sys_pll1_80m", "sys_pll2_166m" };
 161
 162 static const char *imx8mp_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
 163                                            "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
 164                                            "audio_pll2_out", "sys_pll1_100m", };
 165
 166 static const char *imx8mp_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
 167
 168
 169 static ulong imx8mp_clk_get_rate(struct clk *clk)
 170 {
 171         struct clk *c;
 172         int ret;
 173
 174         debug("%s(#%lu)\n", __func__, clk->id);
 175
 176         ret = clk_get_by_id(clk->id, &c);
 177         if (ret)
 178                 return ret;
 179
 180         return clk_get_rate(c);
 181 }
 182
 183 static ulong imx8mp_clk_set_rate(struct clk *clk, unsigned long rate)
 184 {
 185         struct clk *c;
 186         int ret;
 187
 188         debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
 189
 190         ret = clk_get_by_id(clk->id, &c);
 191         if (ret)
 192                 return ret;
 193
 194         return clk_set_rate(c, rate);
 195 }
 196
 197 static int __imx8mp_clk_enable(struct clk *clk, bool enable)
 198 {
 199         struct clk *c;
 200         int ret;
 201
 202         debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
 203
 204         ret = clk_get_by_id(clk->id, &c);
 205         if (ret)
 206                 return ret;
 207
 208         if (enable)
 209                 ret = clk_enable(c);
 210         else
 211                 ret = clk_disable(c);
 212
 213         return ret;
 214 }
 215
 216 static int imx8mp_clk_disable(struct clk *clk)
 217 {
 218         return __imx8mp_clk_enable(clk, 0);
 219 }
 220
 221 static int imx8mp_clk_enable(struct clk *clk)
 222 {
 223         return __imx8mp_clk_enable(clk, 1);
 224 }
 225
 226 static struct clk_ops imx8mp_clk_ops = {
 227         .set_rate = imx8mp_clk_set_rate,
 228         .get_rate = imx8mp_clk_get_rate,
 229         .enable = imx8mp_clk_enable,
 230         .disable = imx8mp_clk_disable,
 231 };
 232
 233 static int imx8mp_clk_probe(struct udevice *dev)
 234 {
 235         void __iomem *base;
 236
 237         base = (void *)ANATOP_BASE_ADDR;
 238
 239         clk_dm(IMX8MP_DRAM_PLL_REF_SEL, imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 240         clk_dm(IMX8MP_ARM_PLL_REF_SEL, imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 241         clk_dm(IMX8MP_SYS_PLL1_REF_SEL, imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 242         clk_dm(IMX8MP_SYS_PLL2_REF_SEL, imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 243         clk_dm(IMX8MP_SYS_PLL3_REF_SEL, imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 244
 245         clk_dm(IMX8MP_DRAM_PLL, imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx8mp_dram_pll));
 246         clk_dm(IMX8MP_ARM_PLL, imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx8mp_arm_pll));
 247         clk_dm(IMX8MP_SYS_PLL1, imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel", base + 0x94, &imx8mp_sys_pll));
 248         clk_dm(IMX8MP_SYS_PLL2, imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel", base + 0x104, &imx8mp_sys_pll));
 249         clk_dm(IMX8MP_SYS_PLL3, imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx8mp_sys_pll));
 250
 251         clk_dm(IMX8MP_DRAM_PLL_BYPASS, imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT));
 252         clk_dm(IMX8MP_ARM_PLL_BYPASS, imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT));
 253         clk_dm(IMX8MP_SYS_PLL1_BYPASS, imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT));
 254         clk_dm(IMX8MP_SYS_PLL2_BYPASS, imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT));
 255         clk_dm(IMX8MP_SYS_PLL3_BYPASS, imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT));
 256
 257         clk_dm(IMX8MP_DRAM_PLL_OUT, imx_clk_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13));
 258         clk_dm(IMX8MP_ARM_PLL_OUT, imx_clk_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 11));
 259         clk_dm(IMX8MP_SYS_PLL1_OUT, imx_clk_gate("sys_pll1_out", "sys_pll1_bypass", base + 0x94, 11));
 260         clk_dm(IMX8MP_SYS_PLL2_OUT, imx_clk_gate("sys_pll2_out", "sys_pll2_bypass", base + 0x104, 11));
 261         clk_dm(IMX8MP_SYS_PLL3_OUT, imx_clk_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11));
 262
 263         clk_dm(IMX8MP_SYS_PLL1_40M, imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20));
 264         clk_dm(IMX8MP_SYS_PLL1_80M, imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10));
 265         clk_dm(IMX8MP_SYS_PLL1_100M, imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8));
 266         clk_dm(IMX8MP_SYS_PLL1_133M, imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6));
 267         clk_dm(IMX8MP_SYS_PLL1_160M, imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5));
 268         clk_dm(IMX8MP_SYS_PLL1_200M, imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4));
 269         clk_dm(IMX8MP_SYS_PLL1_266M, imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3));
 270         clk_dm(IMX8MP_SYS_PLL1_400M, imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2));
 271         clk_dm(IMX8MP_SYS_PLL1_800M, imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1));
 272
 273         clk_dm(IMX8MP_SYS_PLL2_50M, imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20));
 274         clk_dm(IMX8MP_SYS_PLL2_100M, imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10));
 275         clk_dm(IMX8MP_SYS_PLL2_125M, imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8));
 276         clk_dm(IMX8MP_SYS_PLL2_166M, imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6));
 277         clk_dm(IMX8MP_SYS_PLL2_200M, imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5));
 278         clk_dm(IMX8MP_SYS_PLL2_250M, imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4));
 279         clk_dm(IMX8MP_SYS_PLL2_333M, imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3));
 280         clk_dm(IMX8MP_SYS_PLL2_500M, imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2));
 281         clk_dm(IMX8MP_SYS_PLL2_1000M, imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
 282
 283         base = dev_read_addr_ptr(dev);
 284         if (base == (void *)FDT_ADDR_T_NONE)
 285                 return -EINVAL;
 286
 287         clk_dm(IMX8MP_CLK_A53_SRC, imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mp_a53_sels, ARRAY_SIZE(imx8mp_a53_sels)));
 288         clk_dm(IMX8MP_CLK_A53_CG, imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
 289         clk_dm(IMX8MP_CLK_A53_DIV, imx_clk_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3));
 290
 291         clk_dm(IMX8MP_CLK_MAIN_AXI, imx8m_clk_composite_critical("main_axi", imx8mp_main_axi_sels, base + 0x8800));
 292         clk_dm(IMX8MP_CLK_NAND_USDHC_BUS, imx8m_clk_composite_critical("nand_usdhc_bus", imx8mp_nand_usdhc_sels, base + 0x8900));
 293         clk_dm(IMX8MP_CLK_NOC, imx8m_clk_composite_critical("noc", imx8mp_noc_sels, base + 0x8d00));
 294         clk_dm(IMX8MP_CLK_NOC_IO, imx8m_clk_composite_critical("noc_io", imx8mp_noc_io_sels, base + 0x8d80));
 295
 296         clk_dm(IMX8MP_CLK_AHB, imx8m_clk_composite_critical("ahb_root", imx8mp_ahb_sels, base + 0x9000));
 297
 298         clk_dm(IMX8MP_CLK_IPG_ROOT, imx_clk_divider2("ipg_root", "ahb_root", base + 0x9080, 0, 1));
 299
 300         clk_dm(IMX8MP_CLK_DRAM_ALT, imx8m_clk_composite("dram_alt", imx8mp_dram_alt_sels, base + 0xa000));
 301         clk_dm(IMX8MP_CLK_DRAM_APB, imx8m_clk_composite_critical("dram_apb", imx8mp_dram_apb_sels, base + 0xa080));
 302         clk_dm(IMX8MP_CLK_I2C5, imx8m_clk_composite("i2c5", imx8mp_i2c5_sels, base + 0xa480));
 303         clk_dm(IMX8MP_CLK_I2C6, imx8m_clk_composite("i2c6", imx8mp_i2c6_sels, base + 0xa500));
 304         clk_dm(IMX8MP_CLK_USDHC1, imx8m_clk_composite("usdhc1", imx8mp_usdhc1_sels, base + 0xac00));
 305         clk_dm(IMX8MP_CLK_USDHC2, imx8m_clk_composite("usdhc2", imx8mp_usdhc2_sels, base + 0xac80));
 306         clk_dm(IMX8MP_CLK_I2C1, imx8m_clk_composite("i2c1", imx8mp_i2c1_sels, base + 0xad00));
 307         clk_dm(IMX8MP_CLK_I2C2, imx8m_clk_composite("i2c2", imx8mp_i2c2_sels, base + 0xad80));
 308         clk_dm(IMX8MP_CLK_I2C3, imx8m_clk_composite("i2c3", imx8mp_i2c3_sels, base + 0xae00));
 309         clk_dm(IMX8MP_CLK_I2C4, imx8m_clk_composite("i2c4", imx8mp_i2c4_sels, base + 0xae80));
 310
 311         clk_dm(IMX8MP_CLK_UART1, imx8m_clk_composite("uart1", imx8mp_uart1_sels, base + 0xaf00));
 312         clk_dm(IMX8MP_CLK_UART2, imx8m_clk_composite("uart2", imx8mp_uart2_sels, base + 0xaf80));
 313         clk_dm(IMX8MP_CLK_UART3, imx8m_clk_composite("uart3", imx8mp_uart3_sels, base + 0xb000));
 314         clk_dm(IMX8MP_CLK_UART4, imx8m_clk_composite("uart4", imx8mp_uart4_sels, base + 0xb080));
 315         clk_dm(IMX8MP_CLK_GIC, imx8m_clk_composite_critical("gic", imx8mp_gic_sels, base + 0xb200));
 316
 317         clk_dm(IMX8MP_CLK_WDOG, imx8m_clk_composite("wdog", imx8mp_wdog_sels, base + 0xb900));
 318         clk_dm(IMX8MP_CLK_USDHC3, imx8m_clk_composite("usdhc3", imx8mp_usdhc3_sels, base + 0xbc80));
 319
 320         clk_dm(IMX8MP_CLK_DRAM_ALT_ROOT, imx_clk_fixed_factor("dram_alt_root", "dram_alt", 1, 4));
 321         clk_dm(IMX8MP_CLK_DRAM_CORE, imx_clk_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mp_dram_core_sels, ARRAY_SIZE(imx8mp_dram_core_sels), CLK_IS_CRITICAL));
 322
 323         clk_dm(IMX8MP_CLK_DRAM1_ROOT, imx_clk_gate4_flags("dram1_root_clk", "dram_core_clk", base + 0x4050, 0, CLK_IS_CRITICAL));
 324         clk_dm(IMX8MP_CLK_GPIO1_ROOT, imx_clk_gate4("gpio1_root_clk", "ipg_root", base + 0x40b0, 0));
 325         clk_dm(IMX8MP_CLK_GPIO2_ROOT, imx_clk_gate4("gpio2_root_clk", "ipg_root", base + 0x40c0, 0));
 326         clk_dm(IMX8MP_CLK_GPIO3_ROOT, imx_clk_gate4("gpio3_root_clk", "ipg_root", base + 0x40d0, 0));
 327         clk_dm(IMX8MP_CLK_GPIO4_ROOT, imx_clk_gate4("gpio4_root_clk", "ipg_root", base + 0x40e0, 0));
 328         clk_dm(IMX8MP_CLK_GPIO5_ROOT, imx_clk_gate4("gpio5_root_clk", "ipg_root", base + 0x40f0, 0));
 329         clk_dm(IMX8MP_CLK_I2C1_ROOT, imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
 330         clk_dm(IMX8MP_CLK_I2C2_ROOT, imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
 331         clk_dm(IMX8MP_CLK_I2C3_ROOT, imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
 332         clk_dm(IMX8MP_CLK_I2C4_ROOT, imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
 333         clk_dm(IMX8MP_CLK_I2C5_ROOT, imx_clk_gate2("i2c5_root_clk", "i2c5", base + 0x4330, 0));
 334         clk_dm(IMX8MP_CLK_I2C6_ROOT, imx_clk_gate2("i2c6_root_clk", "i2c6", base + 0x4340, 0));
 335         clk_dm(IMX8MP_CLK_UART1_ROOT, imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0));
 336         clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0));
 337         clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0));
 338         clk_dm(IMX8MP_CLK_UART4_ROOT, imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0));
 339         clk_dm(IMX8MP_CLK_USDHC1_ROOT, imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
 340         clk_dm(IMX8MP_CLK_USDHC2_ROOT, imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
 341         clk_dm(IMX8MP_CLK_WDOG1_ROOT, imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
 342         clk_dm(IMX8MP_CLK_WDOG2_ROOT, imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
 343         clk_dm(IMX8MP_CLK_WDOG3_ROOT, imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
 344
 345         clk_dm(IMX8MP_CLK_USDHC3_ROOT, imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
 346
 347         return 0;
 348 }
 349
 350 static const struct udevice_id imx8mp_clk_ids[] = {
 351         { .compatible = "fsl,imx8mp-ccm" },
 352         { },
 353 };
 354
 355 U_BOOT_DRIVER(imx8mp_clk) = {
 356         .name = "clk_imx8mp",
 357         .id = UCLASS_CLK,
 358         .of_match = imx8mp_clk_ids,
 359         .ops = &imx8mp_clk_ops,
 360         .probe = imx8mp_clk_probe,
 361         .flags = DM_FLAG_PRE_RELOC,
 362 };