1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2016 Xilinx, Inc.
9 #include <linux/bitops.h>
10 #include <clk-uclass.h>
12 #include <asm/arch/sys_proto.h>
14 #include <linux/err.h>
16 static const resource_size_t zynqmp_crf_apb_clkc_base = 0xfd1a0020;
17 static const resource_size_t zynqmp_crl_apb_clkc_base = 0xff5e0020;
19 /* Full power domain clocks */
20 #define CRF_APB_APLL_CTRL (zynqmp_crf_apb_clkc_base + 0x00)
21 #define CRF_APB_DPLL_CTRL (zynqmp_crf_apb_clkc_base + 0x0c)
22 #define CRF_APB_VPLL_CTRL (zynqmp_crf_apb_clkc_base + 0x18)
23 #define CRF_APB_PLL_STATUS (zynqmp_crf_apb_clkc_base + 0x24)
24 #define CRF_APB_APLL_TO_LPD_CTRL (zynqmp_crf_apb_clkc_base + 0x28)
25 #define CRF_APB_DPLL_TO_LPD_CTRL (zynqmp_crf_apb_clkc_base + 0x2c)
26 #define CRF_APB_VPLL_TO_LPD_CTRL (zynqmp_crf_apb_clkc_base + 0x30)
27 /* Peripheral clocks */
28 #define CRF_APB_ACPU_CTRL (zynqmp_crf_apb_clkc_base + 0x40)
29 #define CRF_APB_DBG_TRACE_CTRL (zynqmp_crf_apb_clkc_base + 0x44)
30 #define CRF_APB_DBG_FPD_CTRL (zynqmp_crf_apb_clkc_base + 0x48)
31 #define CRF_APB_DP_VIDEO_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x50)
32 #define CRF_APB_DP_AUDIO_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x54)
33 #define CRF_APB_DP_STC_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x5c)
34 #define CRF_APB_DDR_CTRL (zynqmp_crf_apb_clkc_base + 0x60)
35 #define CRF_APB_GPU_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x64)
36 #define CRF_APB_SATA_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x80)
37 #define CRF_APB_PCIE_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x94)
38 #define CRF_APB_GDMA_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x98)
39 #define CRF_APB_DPDMA_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x9c)
40 #define CRF_APB_TOPSW_MAIN_CTRL (zynqmp_crf_apb_clkc_base + 0xa0)
41 #define CRF_APB_TOPSW_LSBUS_CTRL (zynqmp_crf_apb_clkc_base + 0xa4)
42 #define CRF_APB_GTGREF0_REF_CTRL (zynqmp_crf_apb_clkc_base + 0xa8)
43 #define CRF_APB_DBG_TSTMP_CTRL (zynqmp_crf_apb_clkc_base + 0xd8)
45 /* Low power domain clocks */
46 #define CRL_APB_IOPLL_CTRL (zynqmp_crl_apb_clkc_base + 0x00)
47 #define CRL_APB_RPLL_CTRL (zynqmp_crl_apb_clkc_base + 0x10)
48 #define CRL_APB_PLL_STATUS (zynqmp_crl_apb_clkc_base + 0x20)
49 #define CRL_APB_IOPLL_TO_FPD_CTRL (zynqmp_crl_apb_clkc_base + 0x24)
50 #define CRL_APB_RPLL_TO_FPD_CTRL (zynqmp_crl_apb_clkc_base + 0x28)
51 /* Peripheral clocks */
52 #define CRL_APB_USB3_DUAL_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x2c)
53 #define CRL_APB_GEM0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x30)
54 #define CRL_APB_GEM1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x34)
55 #define CRL_APB_GEM2_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x38)
56 #define CRL_APB_GEM3_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x3c)
57 #define CRL_APB_USB0_BUS_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x40)
58 #define CRL_APB_USB1_BUS_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x44)
59 #define CRL_APB_QSPI_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x48)
60 #define CRL_APB_SDIO0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x4c)
61 #define CRL_APB_SDIO1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x50)
62 #define CRL_APB_UART0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x54)
63 #define CRL_APB_UART1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x58)
64 #define CRL_APB_SPI0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x5c)
65 #define CRL_APB_SPI1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x60)
66 #define CRL_APB_CAN0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x64)
67 #define CRL_APB_CAN1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x68)
68 #define CRL_APB_CPU_R5_CTRL (zynqmp_crl_apb_clkc_base + 0x70)
69 #define CRL_APB_IOU_SWITCH_CTRL (zynqmp_crl_apb_clkc_base + 0x7c)
70 #define CRL_APB_CSU_PLL_CTRL (zynqmp_crl_apb_clkc_base + 0x80)
71 #define CRL_APB_PCAP_CTRL (zynqmp_crl_apb_clkc_base + 0x84)
72 #define CRL_APB_LPD_SWITCH_CTRL (zynqmp_crl_apb_clkc_base + 0x88)
73 #define CRL_APB_LPD_LSBUS_CTRL (zynqmp_crl_apb_clkc_base + 0x8c)
74 #define CRL_APB_DBG_LPD_CTRL (zynqmp_crl_apb_clkc_base + 0x90)
75 #define CRL_APB_NAND_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x94)
76 #define CRL_APB_ADMA_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x98)
77 #define CRL_APB_PL0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xa0)
78 #define CRL_APB_PL1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xa4)
79 #define CRL_APB_PL2_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xa8)
80 #define CRL_APB_PL3_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xac)
81 #define CRL_APB_PL0_THR_CNT (zynqmp_crl_apb_clkc_base + 0xb4)
82 #define CRL_APB_PL1_THR_CNT (zynqmp_crl_apb_clkc_base + 0xbc)
83 #define CRL_APB_PL2_THR_CNT (zynqmp_crl_apb_clkc_base + 0xc4)
84 #define CRL_APB_PL3_THR_CNT (zynqmp_crl_apb_clkc_base + 0xdc)
85 #define CRL_APB_GEM_TSU_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xe0)
86 #define CRL_APB_DLL_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xe4)
87 #define CRL_APB_AMS_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xe8)
88 #define CRL_APB_I2C0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x100)
89 #define CRL_APB_I2C1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x104)
90 #define CRL_APB_TIMESTAMP_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x108)
92 #define ZYNQ_CLK_MAXDIV 0x3f
93 #define CLK_CTRL_DIV1_SHIFT 16
94 #define CLK_CTRL_DIV1_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT)
95 #define CLK_CTRL_DIV0_SHIFT 8
96 #define CLK_CTRL_DIV0_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT)
97 #define CLK_CTRL_SRCSEL_SHIFT 0
98 #define CLK_CTRL_SRCSEL_MASK (0x3 << CLK_CTRL_SRCSEL_SHIFT)
99 #define PLLCTRL_FBDIV_MASK 0x7f00
100 #define PLLCTRL_FBDIV_SHIFT 8
101 #define PLLCTRL_RESET_MASK 1
102 #define PLLCTRL_RESET_SHIFT 0
103 #define PLLCTRL_BYPASS_MASK 0x8
104 #define PLLCTRL_BYPASS_SHFT 3
105 #define PLLCTRL_POST_SRC_SHFT 24
106 #define PLLCTRL_POST_SRC_MASK (0x7 << PLLCTRL_POST_SRC_SHFT)
107 #define PLLCTRL_PRE_SRC_SHFT 20
108 #define PLLCTRL_PRE_SRC_MASK (0x7 << PLLCTRL_PRE_SRC_SHFT)
111 #define NUM_MIO_PINS 77
116 iopll_to_fpd, rpll_to_fpd, apll_to_lpd, dpll_to_lpd, vpll_to_lpd,
118 dbg_fpd, dbg_lpd, dbg_trace, dbg_tstmp,
119 dp_video_ref, dp_audio_ref,
120 dp_stc_ref, gdma_ref, dpdma_ref,
121 ddr_ref, sata_ref, pcie_ref,
122 gpu_ref, gpu_pp0_ref, gpu_pp1_ref,
123 topsw_main, topsw_lsbus,
125 lpd_switch, lpd_lsbus,
126 usb0_bus_ref, usb1_bus_ref, usb3_dual_ref, usb0, usb1,
128 csu_spb, csu_pll, pcap,
130 gem_tsu_ref, gem_tsu,
131 gem0_ref, gem1_ref, gem2_ref, gem3_ref,
132 gem0_rx, gem1_rx, gem2_rx, gem3_rx,
134 sdio0_ref, sdio1_ref,
135 uart0_ref, uart1_ref,
138 i2c0_ref, i2c1_ref, can0_ref, can1_ref, can0, can1,
148 static const char * const clk_names[clk_max] = {
149 "iopll", "rpll", "apll", "dpll",
150 "vpll", "iopll_to_fpd", "rpll_to_fpd",
151 "apll_to_lpd", "dpll_to_lpd", "vpll_to_lpd",
152 "acpu", "acpu_half", "dbf_fpd", "dbf_lpd",
153 "dbg_trace", "dbg_tstmp", "dp_video_ref",
154 "dp_audio_ref", "dp_stc_ref", "gdma_ref",
155 "dpdma_ref", "ddr_ref", "sata_ref", "pcie_ref",
156 "gpu_ref", "gpu_pp0_ref", "gpu_pp1_ref",
157 "topsw_main", "topsw_lsbus", "gtgref0_ref",
158 "lpd_switch", "lpd_lsbus", "usb0_bus_ref",
159 "usb1_bus_ref", "usb3_dual_ref", "usb0",
160 "usb1", "cpu_r5", "cpu_r5_core", "csu_spb",
161 "csu_pll", "pcap", "iou_switch", "gem_tsu_ref",
162 "gem_tsu", "gem0_ref", "gem1_ref", "gem2_ref",
163 "gem3_ref", "gem0_tx", "gem1_tx", "gem2_tx",
164 "gem3_tx", "qspi_ref", "sdio0_ref", "sdio1_ref",
165 "uart0_ref", "uart1_ref", "spi0_ref",
166 "spi1_ref", "nand_ref", "i2c0_ref", "i2c1_ref",
167 "can0_ref", "can1_ref", "can0", "can1",
168 "dll_ref", "adma_ref", "timestamp_ref",
169 "ams_ref", "pl0", "pl1", "pl2", "pl3", "wdt"
172 struct zynqmp_clk_priv {
173 unsigned long ps_clk_freq;
174 unsigned long video_clk;
175 unsigned long pss_alt_ref_clk;
176 unsigned long gt_crx_ref_clk;
177 unsigned long aux_ref_clk;
180 static u32 zynqmp_clk_get_register(enum zynqmp_clk id)
184 return CRL_APB_IOPLL_CTRL;
186 return CRL_APB_RPLL_CTRL;
188 return CRF_APB_APLL_CTRL;
190 return CRF_APB_DPLL_CTRL;
192 return CRF_APB_VPLL_CTRL;
194 return CRF_APB_ACPU_CTRL;
196 return CRF_APB_DDR_CTRL;
198 return CRL_APB_QSPI_REF_CTRL;
200 return CRL_APB_GEM0_REF_CTRL;
202 return CRL_APB_GEM1_REF_CTRL;
204 return CRL_APB_GEM2_REF_CTRL;
206 return CRL_APB_GEM3_REF_CTRL;
208 return CRL_APB_UART0_REF_CTRL;
210 return CRL_APB_UART1_REF_CTRL;
212 return CRL_APB_SDIO0_REF_CTRL;
214 return CRL_APB_SDIO1_REF_CTRL;
216 return CRL_APB_SPI0_REF_CTRL;
218 return CRL_APB_SPI1_REF_CTRL;
220 return CRL_APB_NAND_REF_CTRL;
222 return CRL_APB_I2C0_REF_CTRL;
224 return CRL_APB_I2C1_REF_CTRL;
226 return CRL_APB_CAN0_REF_CTRL;
228 return CRL_APB_CAN1_REF_CTRL;
230 return CRL_APB_PL0_REF_CTRL;
232 return CRL_APB_PL1_REF_CTRL;
234 return CRL_APB_PL2_REF_CTRL;
236 return CRL_APB_PL3_REF_CTRL;
238 return CRF_APB_TOPSW_LSBUS_CTRL;
240 return CRL_APB_IOPLL_TO_FPD_CTRL;
242 debug("Invalid clk id%d\n", id);
247 static enum zynqmp_clk zynqmp_clk_get_cpu_pll(u32 clk_ctrl)
249 u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
250 CLK_CTRL_SRCSEL_SHIFT;
263 static enum zynqmp_clk zynqmp_clk_get_ddr_pll(u32 clk_ctrl)
265 u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
266 CLK_CTRL_SRCSEL_SHIFT;
277 static enum zynqmp_clk zynqmp_clk_get_peripheral_pll(u32 clk_ctrl)
279 u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
280 CLK_CTRL_SRCSEL_SHIFT;
293 static enum zynqmp_clk zynqmp_clk_get_wdt_pll(u32 clk_ctrl)
295 u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
296 CLK_CTRL_SRCSEL_SHIFT;
309 static ulong zynqmp_clk_get_pll_src(ulong clk_ctrl,
310 struct zynqmp_clk_priv *priv,
316 src_sel = (clk_ctrl & PLLCTRL_PRE_SRC_MASK) >>
317 PLLCTRL_PRE_SRC_SHFT;
319 src_sel = (clk_ctrl & PLLCTRL_POST_SRC_MASK) >>
320 PLLCTRL_POST_SRC_SHFT;
324 return priv->video_clk;
326 return priv->pss_alt_ref_clk;
328 return priv->aux_ref_clk;
330 return priv->gt_crx_ref_clk;
333 return priv->ps_clk_freq;
337 static ulong zynqmp_clk_get_pll_rate(struct zynqmp_clk_priv *priv,
340 u32 clk_ctrl, reset, mul;
344 ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl);
346 printf("%s mio read fail\n", __func__);
350 if (clk_ctrl & PLLCTRL_BYPASS_MASK)
351 freq = zynqmp_clk_get_pll_src(clk_ctrl, priv, 0);
353 freq = zynqmp_clk_get_pll_src(clk_ctrl, priv, 1);
355 reset = (clk_ctrl & PLLCTRL_RESET_MASK) >> PLLCTRL_RESET_SHIFT;
356 if (reset && !(clk_ctrl & PLLCTRL_BYPASS_MASK))
359 mul = (clk_ctrl & PLLCTRL_FBDIV_MASK) >> PLLCTRL_FBDIV_SHIFT;
363 if (clk_ctrl & (1 << 16))
369 static ulong zynqmp_clk_get_cpu_rate(struct zynqmp_clk_priv *priv,
375 unsigned long pllrate;
377 ret = zynqmp_mmio_read(CRF_APB_ACPU_CTRL, &clk_ctrl);
379 printf("%s mio read fail\n", __func__);
383 div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
385 pll = zynqmp_clk_get_cpu_pll(clk_ctrl);
386 pllrate = zynqmp_clk_get_pll_rate(priv, pll);
387 if (IS_ERR_VALUE(pllrate))
390 return DIV_ROUND_CLOSEST(pllrate, div);
393 static ulong zynqmp_clk_get_ddr_rate(struct zynqmp_clk_priv *priv)
400 ret = zynqmp_mmio_read(CRF_APB_DDR_CTRL, &clk_ctrl);
402 printf("%s mio read fail\n", __func__);
406 div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
408 pll = zynqmp_clk_get_ddr_pll(clk_ctrl);
409 pllrate = zynqmp_clk_get_pll_rate(priv, pll);
410 if (IS_ERR_VALUE(pllrate))
413 return DIV_ROUND_CLOSEST(pllrate, div);
416 static ulong zynqmp_clk_get_peripheral_rate(struct zynqmp_clk_priv *priv,
417 enum zynqmp_clk id, bool two_divs)
425 ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl);
427 printf("%s mio read fail\n", __func__);
431 div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
436 div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;
441 pll = zynqmp_clk_get_peripheral_pll(clk_ctrl);
442 pllrate = zynqmp_clk_get_pll_rate(priv, pll);
443 if (IS_ERR_VALUE(pllrate))
448 DIV_ROUND_CLOSEST(pllrate, div0), div1);
451 static ulong zynqmp_clk_get_wdt_rate(struct zynqmp_clk_priv *priv,
452 enum zynqmp_clk id, bool two_divs)
460 ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl);
462 printf("%d %s mio read fail\n", __LINE__, __func__);
466 div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
470 pll = zynqmp_clk_get_wdt_pll(clk_ctrl);
472 ret = zynqmp_mmio_read(zynqmp_clk_get_register(pll), &clk_ctrl);
474 printf("%d %s mio read fail\n", __LINE__, __func__);
477 div1 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
482 if (pll == iopll_to_fpd)
485 pllrate = zynqmp_clk_get_pll_rate(priv, pll);
486 if (IS_ERR_VALUE(pllrate))
491 DIV_ROUND_CLOSEST(pllrate, div0), div1);
494 static unsigned long zynqmp_clk_calc_peripheral_two_divs(ulong rate,
496 u32 *div0, u32 *div1)
498 long new_err, best_err = (long)(~0UL >> 1);
499 ulong new_rate, best_rate = 0;
502 for (d0 = 1; d0 <= ZYNQ_CLK_MAXDIV; d0++) {
503 for (d1 = 1; d1 <= ZYNQ_CLK_MAXDIV >> 1; d1++) {
504 new_rate = DIV_ROUND_CLOSEST(
505 DIV_ROUND_CLOSEST(pll_rate, d0), d1);
506 new_err = abs(new_rate - rate);
508 if (new_err < best_err) {
512 best_rate = new_rate;
520 static ulong zynqmp_clk_set_peripheral_rate(struct zynqmp_clk_priv *priv,
521 enum zynqmp_clk id, ulong rate,
525 u32 clk_ctrl, div0 = 0, div1 = 0;
526 ulong pll_rate, new_rate;
531 reg = zynqmp_clk_get_register(id);
532 ret = zynqmp_mmio_read(reg, &clk_ctrl);
534 printf("%s mio read fail\n", __func__);
538 pll = zynqmp_clk_get_peripheral_pll(clk_ctrl);
539 pll_rate = zynqmp_clk_get_pll_rate(priv, pll);
540 if (IS_ERR_VALUE(pll_rate))
543 clk_ctrl &= ~CLK_CTRL_DIV0_MASK;
545 clk_ctrl &= ~CLK_CTRL_DIV1_MASK;
546 new_rate = zynqmp_clk_calc_peripheral_two_divs(rate, pll_rate,
548 clk_ctrl |= div1 << CLK_CTRL_DIV1_SHIFT;
550 div0 = DIV_ROUND_CLOSEST(pll_rate, rate);
551 if (div0 > ZYNQ_CLK_MAXDIV)
552 div0 = ZYNQ_CLK_MAXDIV;
553 new_rate = DIV_ROUND_CLOSEST(rate, div0);
555 clk_ctrl |= div0 << CLK_CTRL_DIV0_SHIFT;
557 mask = (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT) |
558 (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT);
560 ret = zynqmp_mmio_write(reg, mask, clk_ctrl);
562 printf("%s mio write fail\n", __func__);
569 static ulong zynqmp_clk_get_rate(struct clk *clk)
571 struct zynqmp_clk_priv *priv = dev_get_priv(clk->dev);
572 enum zynqmp_clk id = clk->id;
573 bool two_divs = false;
577 return zynqmp_clk_get_pll_rate(priv, id);
579 return zynqmp_clk_get_cpu_rate(priv, id);
581 return zynqmp_clk_get_ddr_rate(priv);
582 case gem0_ref ... gem3_ref:
583 case qspi_ref ... can1_ref:
586 return zynqmp_clk_get_peripheral_rate(priv, id, two_divs);
589 return zynqmp_clk_get_wdt_rate(priv, id, two_divs);
595 static ulong zynqmp_clk_set_rate(struct clk *clk, ulong rate)
597 struct zynqmp_clk_priv *priv = dev_get_priv(clk->dev);
598 enum zynqmp_clk id = clk->id;
599 bool two_divs = true;
602 case gem0_ref ... gem3_ref:
603 case qspi_ref ... can1_ref:
604 return zynqmp_clk_set_peripheral_rate(priv, id,
611 int soc_clk_dump(void)
616 ret = uclass_get_device_by_driver(UCLASS_CLK,
617 DM_GET_DRIVER(zynqmp_clk), &dev);
621 printf("clk\t\tfrequency\n");
622 for (i = 0; i < clk_max; i++) {
623 const char *name = clk_names[i];
629 ret = clk_request(dev, &clk);
633 rate = clk_get_rate(&clk);
637 if ((rate == (unsigned long)-ENOSYS) ||
638 (rate == (unsigned long)-ENXIO) ||
639 (rate == (unsigned long)-EIO))
640 printf("%10s%20s\n", name, "unknown");
642 printf("%10s%20lu\n", name, rate);
649 static int zynqmp_get_freq_by_name(char *name, struct udevice *dev, ulong *freq)
654 ret = clk_get_by_name(dev, name, &clk);
656 dev_err(dev, "failed to get %s\n", name);
660 *freq = clk_get_rate(&clk);
661 if (IS_ERR_VALUE(*freq)) {
662 dev_err(dev, "failed to get rate %s\n", name);
668 static int zynqmp_clk_probe(struct udevice *dev)
671 struct zynqmp_clk_priv *priv = dev_get_priv(dev);
673 debug("%s\n", __func__);
674 ret = zynqmp_get_freq_by_name("pss_ref_clk", dev, &priv->ps_clk_freq);
678 ret = zynqmp_get_freq_by_name("video_clk", dev, &priv->video_clk);
682 ret = zynqmp_get_freq_by_name("pss_alt_ref_clk", dev,
683 &priv->pss_alt_ref_clk);
687 ret = zynqmp_get_freq_by_name("aux_ref_clk", dev, &priv->aux_ref_clk);
691 ret = zynqmp_get_freq_by_name("gt_crx_ref_clk", dev,
692 &priv->gt_crx_ref_clk);
699 static struct clk_ops zynqmp_clk_ops = {
700 .set_rate = zynqmp_clk_set_rate,
701 .get_rate = zynqmp_clk_get_rate,
704 static const struct udevice_id zynqmp_clk_ids[] = {
705 { .compatible = "xlnx,zynqmp-clk" },
709 U_BOOT_DRIVER(zynqmp_clk) = {
710 .name = "zynqmp-clk",
712 .of_match = zynqmp_clk_ids,
713 .probe = zynqmp_clk_probe,
714 .ops = &zynqmp_clk_ops,
715 .priv_auto_alloc_size = sizeof(struct zynqmp_clk_priv),