drivers/clk/clk_zynqmp.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * ZynqMP clock driver
   4  *
   5  * Copyright (C) 2016 Xilinx, Inc.
   6  */
   7
   8 #include <common.h>
   9 #include <malloc.h>
  10 #include <dm/device_compat.h>
  11 #include <linux/bitops.h>
  12 #include <clk-uclass.h>
  13 #include <clk.h>
  14 #include <asm/arch/sys_proto.h>
  15 #include <dm.h>
  16 #include <linux/err.h>
  17
  18 static const resource_size_t zynqmp_crf_apb_clkc_base = 0xfd1a0020;
  19 static const resource_size_t zynqmp_crl_apb_clkc_base = 0xff5e0020;
  20
  21 /* Full power domain clocks */
  22 #define CRF_APB_APLL_CTRL               (zynqmp_crf_apb_clkc_base + 0x00)
  23 #define CRF_APB_DPLL_CTRL               (zynqmp_crf_apb_clkc_base + 0x0c)
  24 #define CRF_APB_VPLL_CTRL               (zynqmp_crf_apb_clkc_base + 0x18)
  25 #define CRF_APB_PLL_STATUS              (zynqmp_crf_apb_clkc_base + 0x24)
  26 #define CRF_APB_APLL_TO_LPD_CTRL        (zynqmp_crf_apb_clkc_base + 0x28)
  27 #define CRF_APB_DPLL_TO_LPD_CTRL        (zynqmp_crf_apb_clkc_base + 0x2c)
  28 #define CRF_APB_VPLL_TO_LPD_CTRL        (zynqmp_crf_apb_clkc_base + 0x30)
  29 /* Peripheral clocks */
  30 #define CRF_APB_ACPU_CTRL               (zynqmp_crf_apb_clkc_base + 0x40)
  31 #define CRF_APB_DBG_TRACE_CTRL          (zynqmp_crf_apb_clkc_base + 0x44)
  32 #define CRF_APB_DBG_FPD_CTRL            (zynqmp_crf_apb_clkc_base + 0x48)
  33 #define CRF_APB_DP_VIDEO_REF_CTRL       (zynqmp_crf_apb_clkc_base + 0x50)
  34 #define CRF_APB_DP_AUDIO_REF_CTRL       (zynqmp_crf_apb_clkc_base + 0x54)
  35 #define CRF_APB_DP_STC_REF_CTRL         (zynqmp_crf_apb_clkc_base + 0x5c)
  36 #define CRF_APB_DDR_CTRL                (zynqmp_crf_apb_clkc_base + 0x60)
  37 #define CRF_APB_GPU_REF_CTRL            (zynqmp_crf_apb_clkc_base + 0x64)
  38 #define CRF_APB_SATA_REF_CTRL           (zynqmp_crf_apb_clkc_base + 0x80)
  39 #define CRF_APB_PCIE_REF_CTRL           (zynqmp_crf_apb_clkc_base + 0x94)
  40 #define CRF_APB_GDMA_REF_CTRL           (zynqmp_crf_apb_clkc_base + 0x98)
  41 #define CRF_APB_DPDMA_REF_CTRL          (zynqmp_crf_apb_clkc_base + 0x9c)
  42 #define CRF_APB_TOPSW_MAIN_CTRL         (zynqmp_crf_apb_clkc_base + 0xa0)
  43 #define CRF_APB_TOPSW_LSBUS_CTRL        (zynqmp_crf_apb_clkc_base + 0xa4)
  44 #define CRF_APB_GTGREF0_REF_CTRL        (zynqmp_crf_apb_clkc_base + 0xa8)
  45 #define CRF_APB_DBG_TSTMP_CTRL          (zynqmp_crf_apb_clkc_base + 0xd8)
  46
  47 /* Low power domain clocks */
  48 #define CRL_APB_IOPLL_CTRL              (zynqmp_crl_apb_clkc_base + 0x00)
  49 #define CRL_APB_RPLL_CTRL               (zynqmp_crl_apb_clkc_base + 0x10)
  50 #define CRL_APB_PLL_STATUS              (zynqmp_crl_apb_clkc_base + 0x20)
  51 #define CRL_APB_IOPLL_TO_FPD_CTRL       (zynqmp_crl_apb_clkc_base + 0x24)
  52 #define CRL_APB_RPLL_TO_FPD_CTRL        (zynqmp_crl_apb_clkc_base + 0x28)
  53 /* Peripheral clocks */
  54 #define CRL_APB_USB3_DUAL_REF_CTRL      (zynqmp_crl_apb_clkc_base + 0x2c)
  55 #define CRL_APB_GEM0_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x30)
  56 #define CRL_APB_GEM1_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x34)
  57 #define CRL_APB_GEM2_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x38)
  58 #define CRL_APB_GEM3_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x3c)
  59 #define CRL_APB_USB0_BUS_REF_CTRL       (zynqmp_crl_apb_clkc_base + 0x40)
  60 #define CRL_APB_USB1_BUS_REF_CTRL       (zynqmp_crl_apb_clkc_base + 0x44)
  61 #define CRL_APB_QSPI_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x48)
  62 #define CRL_APB_SDIO0_REF_CTRL          (zynqmp_crl_apb_clkc_base + 0x4c)
  63 #define CRL_APB_SDIO1_REF_CTRL          (zynqmp_crl_apb_clkc_base + 0x50)
  64 #define CRL_APB_UART0_REF_CTRL          (zynqmp_crl_apb_clkc_base + 0x54)
  65 #define CRL_APB_UART1_REF_CTRL          (zynqmp_crl_apb_clkc_base + 0x58)
  66 #define CRL_APB_SPI0_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x5c)
  67 #define CRL_APB_SPI1_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x60)
  68 #define CRL_APB_CAN0_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x64)
  69 #define CRL_APB_CAN1_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x68)
  70 #define CRL_APB_CPU_R5_CTRL             (zynqmp_crl_apb_clkc_base + 0x70)
  71 #define CRL_APB_IOU_SWITCH_CTRL         (zynqmp_crl_apb_clkc_base + 0x7c)
  72 #define CRL_APB_CSU_PLL_CTRL            (zynqmp_crl_apb_clkc_base + 0x80)
  73 #define CRL_APB_PCAP_CTRL               (zynqmp_crl_apb_clkc_base + 0x84)
  74 #define CRL_APB_LPD_SWITCH_CTRL         (zynqmp_crl_apb_clkc_base + 0x88)
  75 #define CRL_APB_LPD_LSBUS_CTRL          (zynqmp_crl_apb_clkc_base + 0x8c)
  76 #define CRL_APB_DBG_LPD_CTRL            (zynqmp_crl_apb_clkc_base + 0x90)
  77 #define CRL_APB_NAND_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x94)
  78 #define CRL_APB_ADMA_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x98)
  79 #define CRL_APB_PL0_REF_CTRL            (zynqmp_crl_apb_clkc_base + 0xa0)
  80 #define CRL_APB_PL1_REF_CTRL            (zynqmp_crl_apb_clkc_base + 0xa4)
  81 #define CRL_APB_PL2_REF_CTRL            (zynqmp_crl_apb_clkc_base + 0xa8)
  82 #define CRL_APB_PL3_REF_CTRL            (zynqmp_crl_apb_clkc_base + 0xac)
  83 #define CRL_APB_PL0_THR_CNT             (zynqmp_crl_apb_clkc_base + 0xb4)
  84 #define CRL_APB_PL1_THR_CNT             (zynqmp_crl_apb_clkc_base + 0xbc)
  85 #define CRL_APB_PL2_THR_CNT             (zynqmp_crl_apb_clkc_base + 0xc4)
  86 #define CRL_APB_PL3_THR_CNT             (zynqmp_crl_apb_clkc_base + 0xdc)
  87 #define CRL_APB_GEM_TSU_REF_CTRL        (zynqmp_crl_apb_clkc_base + 0xe0)
  88 #define CRL_APB_DLL_REF_CTRL            (zynqmp_crl_apb_clkc_base + 0xe4)
  89 #define CRL_APB_AMS_REF_CTRL            (zynqmp_crl_apb_clkc_base + 0xe8)
  90 #define CRL_APB_I2C0_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x100)
  91 #define CRL_APB_I2C1_REF_CTRL           (zynqmp_crl_apb_clkc_base + 0x104)
  92 #define CRL_APB_TIMESTAMP_REF_CTRL      (zynqmp_crl_apb_clkc_base + 0x108)
  93
  94 #define ZYNQ_CLK_MAXDIV         0x3f
  95 #define CLK_CTRL_DIV1_SHIFT     16
  96 #define CLK_CTRL_DIV1_MASK      (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT)
  97 #define CLK_CTRL_DIV0_SHIFT     8
  98 #define CLK_CTRL_DIV0_MASK      (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT)
  99 #define CLK_CTRL_SRCSEL_SHIFT   0
 100 #define CLK_CTRL_SRCSEL_MASK    (0x3 << CLK_CTRL_SRCSEL_SHIFT)
 101 #define PLLCTRL_FBDIV_MASK      0x7f00
 102 #define PLLCTRL_FBDIV_SHIFT     8
 103 #define PLLCTRL_RESET_MASK      1
 104 #define PLLCTRL_RESET_SHIFT     0
 105 #define PLLCTRL_BYPASS_MASK     0x8
 106 #define PLLCTRL_BYPASS_SHFT     3
 107 #define PLLCTRL_POST_SRC_SHFT   24
 108 #define PLLCTRL_POST_SRC_MASK   (0x7 << PLLCTRL_POST_SRC_SHFT)
 109 #define PLLCTRL_PRE_SRC_SHFT    20
 110 #define PLLCTRL_PRE_SRC_MASK    (0x7 << PLLCTRL_PRE_SRC_SHFT)
 111
 112
 113 #define NUM_MIO_PINS    77
 114
 115 enum zynqmp_clk {
 116         iopll, rpll,
 117         apll, dpll, vpll,
 118         iopll_to_fpd, rpll_to_fpd, apll_to_lpd, dpll_to_lpd, vpll_to_lpd,
 119         acpu, acpu_half,
 120         dbg_fpd, dbg_lpd, dbg_trace, dbg_tstmp,
 121         dp_video_ref, dp_audio_ref,
 122         dp_stc_ref, gdma_ref, dpdma_ref,
 123         ddr_ref, sata_ref, pcie_ref,
 124         gpu_ref, gpu_pp0_ref, gpu_pp1_ref,
 125         topsw_main, topsw_lsbus,
 126         gtgref0_ref,
 127         lpd_switch, lpd_lsbus,
 128         usb0_bus_ref, usb1_bus_ref, usb3_dual_ref, usb0, usb1,
 129         cpu_r5, cpu_r5_core,
 130         csu_spb, csu_pll, pcap,
 131         iou_switch,
 132         gem_tsu_ref, gem_tsu,
 133         gem0_ref, gem1_ref, gem2_ref, gem3_ref,
 134         gem0_rx, gem1_rx, gem2_rx, gem3_rx,
 135         qspi_ref,
 136         sdio0_ref, sdio1_ref,
 137         uart0_ref, uart1_ref,
 138         spi0_ref, spi1_ref,
 139         nand_ref,
 140         i2c0_ref, i2c1_ref, can0_ref, can1_ref, can0, can1,
 141         dll_ref,
 142         adma_ref,
 143         timestamp_ref,
 144         ams_ref,
 145         pl0, pl1, pl2, pl3,
 146         wdt,
 147         clk_max,
 148 };
 149
 150 static const char * const clk_names[clk_max] = {
 151         "iopll", "rpll", "apll", "dpll",
 152         "vpll", "iopll_to_fpd", "rpll_to_fpd",
 153         "apll_to_lpd", "dpll_to_lpd", "vpll_to_lpd",
 154         "acpu", "acpu_half", "dbf_fpd", "dbf_lpd",
 155         "dbg_trace", "dbg_tstmp", "dp_video_ref",
 156         "dp_audio_ref", "dp_stc_ref", "gdma_ref",
 157         "dpdma_ref", "ddr_ref", "sata_ref", "pcie_ref",
 158         "gpu_ref", "gpu_pp0_ref", "gpu_pp1_ref",
 159         "topsw_main", "topsw_lsbus", "gtgref0_ref",
 160         "lpd_switch", "lpd_lsbus", "usb0_bus_ref",
 161         "usb1_bus_ref", "usb3_dual_ref", "usb0",
 162         "usb1", "cpu_r5", "cpu_r5_core", "csu_spb",
 163         "csu_pll", "pcap", "iou_switch", "gem_tsu_ref",
 164         "gem_tsu", "gem0_ref", "gem1_ref", "gem2_ref",
 165         "gem3_ref", "gem0_tx", "gem1_tx", "gem2_tx",
 166         "gem3_tx", "qspi_ref", "sdio0_ref", "sdio1_ref",
 167         "uart0_ref", "uart1_ref", "spi0_ref",
 168         "spi1_ref", "nand_ref", "i2c0_ref", "i2c1_ref",
 169         "can0_ref", "can1_ref", "can0", "can1",
 170         "dll_ref", "adma_ref", "timestamp_ref",
 171         "ams_ref", "pl0", "pl1", "pl2", "pl3", "wdt"
 172 };
 173
 174 struct zynqmp_clk_priv {
 175         unsigned long ps_clk_freq;
 176         unsigned long video_clk;
 177         unsigned long pss_alt_ref_clk;
 178         unsigned long gt_crx_ref_clk;
 179         unsigned long aux_ref_clk;
 180 };
 181
 182 static u32 zynqmp_clk_get_register(enum zynqmp_clk id)
 183 {
 184         switch (id) {
 185         case iopll:
 186                 return CRL_APB_IOPLL_CTRL;
 187         case rpll:
 188                 return CRL_APB_RPLL_CTRL;
 189         case apll:
 190                 return CRF_APB_APLL_CTRL;
 191         case dpll:
 192                 return CRF_APB_DPLL_CTRL;
 193         case vpll:
 194                 return CRF_APB_VPLL_CTRL;
 195         case acpu:
 196                 return CRF_APB_ACPU_CTRL;
 197         case ddr_ref:
 198                 return CRF_APB_DDR_CTRL;
 199         case qspi_ref:
 200                 return CRL_APB_QSPI_REF_CTRL;
 201         case gem0_ref:
 202                 return CRL_APB_GEM0_REF_CTRL;
 203         case gem1_ref:
 204                 return CRL_APB_GEM1_REF_CTRL;
 205         case gem2_ref:
 206                 return CRL_APB_GEM2_REF_CTRL;
 207         case gem3_ref:
 208                 return CRL_APB_GEM3_REF_CTRL;
 209         case uart0_ref:
 210                 return CRL_APB_UART0_REF_CTRL;
 211         case uart1_ref:
 212                 return CRL_APB_UART1_REF_CTRL;
 213         case sdio0_ref:
 214                 return CRL_APB_SDIO0_REF_CTRL;
 215         case sdio1_ref:
 216                 return CRL_APB_SDIO1_REF_CTRL;
 217         case spi0_ref:
 218                 return CRL_APB_SPI0_REF_CTRL;
 219         case spi1_ref:
 220                 return CRL_APB_SPI1_REF_CTRL;
 221         case nand_ref:
 222                 return CRL_APB_NAND_REF_CTRL;
 223         case i2c0_ref:
 224                 return CRL_APB_I2C0_REF_CTRL;
 225         case i2c1_ref:
 226                 return CRL_APB_I2C1_REF_CTRL;
 227         case can0_ref:
 228                 return CRL_APB_CAN0_REF_CTRL;
 229         case can1_ref:
 230                 return CRL_APB_CAN1_REF_CTRL;
 231         case pl0:
 232                 return CRL_APB_PL0_REF_CTRL;
 233         case pl1:
 234                 return CRL_APB_PL1_REF_CTRL;
 235         case pl2:
 236                 return CRL_APB_PL2_REF_CTRL;
 237         case pl3:
 238                 return CRL_APB_PL3_REF_CTRL;
 239         case wdt:
 240                 return CRF_APB_TOPSW_LSBUS_CTRL;
 241         case iopll_to_fpd:
 242                 return CRL_APB_IOPLL_TO_FPD_CTRL;
 243         default:
 244                 debug("Invalid clk id%d\n", id);
 245         }
 246         return 0;
 247 }
 248
 249 static enum zynqmp_clk zynqmp_clk_get_cpu_pll(u32 clk_ctrl)
 250 {
 251         u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
 252                       CLK_CTRL_SRCSEL_SHIFT;
 253
 254         switch (srcsel) {
 255         case 2:
 256                 return dpll;
 257         case 3:
 258                 return vpll;
 259         case 0 ... 1:
 260         default:
 261                 return apll;
 262         }
 263 }
 264
 265 static enum zynqmp_clk zynqmp_clk_get_ddr_pll(u32 clk_ctrl)
 266 {
 267         u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
 268                       CLK_CTRL_SRCSEL_SHIFT;
 269
 270         switch (srcsel) {
 271         case 1:
 272                 return vpll;
 273         case 0:
 274         default:
 275                 return dpll;
 276         }
 277 }
 278
 279 static enum zynqmp_clk zynqmp_clk_get_peripheral_pll(u32 clk_ctrl)
 280 {
 281         u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
 282                       CLK_CTRL_SRCSEL_SHIFT;
 283
 284         switch (srcsel) {
 285         case 2:
 286                 return rpll;
 287         case 3:
 288                 return dpll;
 289         case 0 ... 1:
 290         default:
 291                 return iopll;
 292         }
 293 }
 294
 295 static enum zynqmp_clk zynqmp_clk_get_wdt_pll(u32 clk_ctrl)
 296 {
 297         u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
 298                       CLK_CTRL_SRCSEL_SHIFT;
 299
 300         switch (srcsel) {
 301         case 2:
 302                 return iopll_to_fpd;
 303         case 3:
 304                 return dpll;
 305         case 0 ... 1:
 306         default:
 307                 return apll;
 308         }
 309 }
 310
 311 static ulong zynqmp_clk_get_pll_src(ulong clk_ctrl,
 312                                     struct zynqmp_clk_priv *priv,
 313                                     bool is_pre_src)
 314 {
 315         u32 src_sel;
 316
 317         if (is_pre_src)
 318                 src_sel = (clk_ctrl & PLLCTRL_PRE_SRC_MASK) >>
 319                            PLLCTRL_PRE_SRC_SHFT;
 320         else
 321                 src_sel = (clk_ctrl & PLLCTRL_POST_SRC_MASK) >>
 322                            PLLCTRL_POST_SRC_SHFT;
 323
 324         switch (src_sel) {
 325         case 4:
 326                 return priv->video_clk;
 327         case 5:
 328                 return priv->pss_alt_ref_clk;
 329         case 6:
 330                 return priv->aux_ref_clk;
 331         case 7:
 332                 return priv->gt_crx_ref_clk;
 333         case 0 ... 3:
 334         default:
 335         return priv->ps_clk_freq;
 336         }
 337 }
 338
 339 static ulong zynqmp_clk_get_pll_rate(struct zynqmp_clk_priv *priv,
 340                                      enum zynqmp_clk id)
 341 {
 342         u32 clk_ctrl, reset, mul;
 343         ulong freq;
 344         int ret;
 345
 346         ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl);
 347         if (ret) {
 348                 printf("%s mio read fail\n", __func__);
 349                 return -EIO;
 350         }
 351
 352         if (clk_ctrl & PLLCTRL_BYPASS_MASK)
 353                 freq = zynqmp_clk_get_pll_src(clk_ctrl, priv, 0);
 354         else
 355                 freq = zynqmp_clk_get_pll_src(clk_ctrl, priv, 1);
 356
 357         reset = (clk_ctrl & PLLCTRL_RESET_MASK) >> PLLCTRL_RESET_SHIFT;
 358         if (reset && !(clk_ctrl & PLLCTRL_BYPASS_MASK))
 359                 return 0;
 360
 361         mul = (clk_ctrl & PLLCTRL_FBDIV_MASK) >> PLLCTRL_FBDIV_SHIFT;
 362
 363         freq *= mul;
 364
 365         if (clk_ctrl & (1 << 16))
 366                 freq /= 2;
 367
 368         return freq;
 369 }
 370
 371 static ulong zynqmp_clk_get_cpu_rate(struct zynqmp_clk_priv *priv,
 372                                      enum zynqmp_clk id)
 373 {
 374         u32 clk_ctrl, div;
 375         enum zynqmp_clk pll;
 376         int ret;
 377         unsigned long pllrate;
 378
 379         ret = zynqmp_mmio_read(CRF_APB_ACPU_CTRL, &clk_ctrl);
 380         if (ret) {
 381                 printf("%s mio read fail\n", __func__);
 382                 return -EIO;
 383         }
 384
 385         div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
 386
 387         pll = zynqmp_clk_get_cpu_pll(clk_ctrl);
 388         pllrate = zynqmp_clk_get_pll_rate(priv, pll);
 389         if (IS_ERR_VALUE(pllrate))
 390                 return pllrate;
 391
 392         return DIV_ROUND_CLOSEST(pllrate, div);
 393 }
 394
 395 static ulong zynqmp_clk_get_ddr_rate(struct zynqmp_clk_priv *priv)
 396 {
 397         u32 clk_ctrl, div;
 398         enum zynqmp_clk pll;
 399         int ret;
 400         ulong pllrate;
 401
 402         ret = zynqmp_mmio_read(CRF_APB_DDR_CTRL, &clk_ctrl);
 403         if (ret) {
 404                 printf("%s mio read fail\n", __func__);
 405                 return -EIO;
 406         }
 407
 408         div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
 409
 410         pll = zynqmp_clk_get_ddr_pll(clk_ctrl);
 411         pllrate = zynqmp_clk_get_pll_rate(priv, pll);
 412         if (IS_ERR_VALUE(pllrate))
 413                 return pllrate;
 414
 415         return DIV_ROUND_CLOSEST(pllrate, div);
 416 }
 417
 418 static ulong zynqmp_clk_get_peripheral_rate(struct zynqmp_clk_priv *priv,
 419                                           enum zynqmp_clk id, bool two_divs)
 420 {
 421         enum zynqmp_clk pll;
 422         u32 clk_ctrl, div0;
 423         u32 div1 = 1;
 424         int ret;
 425         ulong pllrate;
 426
 427         ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl);
 428         if (ret) {
 429                 printf("%s mio read fail\n", __func__);
 430                 return -EIO;
 431         }
 432
 433         div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
 434         if (!div0)
 435                 div0 = 1;
 436
 437         if (two_divs) {
 438                 div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;
 439                 if (!div1)
 440                         div1 = 1;
 441         }
 442
 443         pll = zynqmp_clk_get_peripheral_pll(clk_ctrl);
 444         pllrate = zynqmp_clk_get_pll_rate(priv, pll);
 445         if (IS_ERR_VALUE(pllrate))
 446                 return pllrate;
 447
 448         return
 449                 DIV_ROUND_CLOSEST(
 450                         DIV_ROUND_CLOSEST(pllrate, div0), div1);
 451 }
 452
 453 static ulong zynqmp_clk_get_wdt_rate(struct zynqmp_clk_priv *priv,
 454                                      enum zynqmp_clk id, bool two_divs)
 455 {
 456         enum zynqmp_clk pll;
 457         u32 clk_ctrl, div0;
 458         u32 div1 = 1;
 459         int ret;
 460         ulong pllrate;
 461
 462         ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl);
 463         if (ret) {
 464                 printf("%d %s mio read fail\n", __LINE__, __func__);
 465                 return -EIO;
 466         }
 467
 468         div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
 469         if (!div0)
 470                 div0 = 1;
 471
 472         pll = zynqmp_clk_get_wdt_pll(clk_ctrl);
 473         if (two_divs) {
 474                 ret = zynqmp_mmio_read(zynqmp_clk_get_register(pll), &clk_ctrl);
 475                 if (ret) {
 476                         printf("%d %s mio read fail\n", __LINE__, __func__);
 477                         return -EIO;
 478                 }
 479                 div1 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
 480                 if (!div1)
 481                         div1 = 1;
 482         }
 483
 484         if (pll == iopll_to_fpd)
 485                 pll = iopll;
 486
 487         pllrate = zynqmp_clk_get_pll_rate(priv, pll);
 488         if (IS_ERR_VALUE(pllrate))
 489                 return pllrate;
 490
 491         return
 492                 DIV_ROUND_CLOSEST(
 493                         DIV_ROUND_CLOSEST(pllrate, div0), div1);
 494 }
 495
 496 static unsigned long zynqmp_clk_calc_peripheral_two_divs(ulong rate,
 497                                                        ulong pll_rate,
 498                                                        u32 *div0, u32 *div1)
 499 {
 500         long new_err, best_err = (long)(~0UL >> 1);
 501         ulong new_rate, best_rate = 0;
 502         u32 d0, d1;
 503
 504         for (d0 = 1; d0 <= ZYNQ_CLK_MAXDIV; d0++) {
 505                 for (d1 = 1; d1 <= ZYNQ_CLK_MAXDIV >> 1; d1++) {
 506                         new_rate = DIV_ROUND_CLOSEST(
 507                                         DIV_ROUND_CLOSEST(pll_rate, d0), d1);
 508                         new_err = abs(new_rate - rate);
 509
 510                         if (new_err < best_err) {
 511                                 *div0 = d0;
 512                                 *div1 = d1;
 513                                 best_err = new_err;
 514                                 best_rate = new_rate;
 515                         }
 516                 }
 517         }
 518
 519         return best_rate;
 520 }
 521
 522 static ulong zynqmp_clk_set_peripheral_rate(struct zynqmp_clk_priv *priv,
 523                                           enum zynqmp_clk id, ulong rate,
 524                                           bool two_divs)
 525 {
 526         enum zynqmp_clk pll;
 527         u32 clk_ctrl, div0 = 0, div1 = 0;
 528         ulong pll_rate, new_rate;
 529         u32 reg;
 530         int ret;
 531         u32 mask;
 532
 533         reg = zynqmp_clk_get_register(id);
 534         ret = zynqmp_mmio_read(reg, &clk_ctrl);
 535         if (ret) {
 536                 printf("%s mio read fail\n", __func__);
 537                 return -EIO;
 538         }
 539
 540         pll = zynqmp_clk_get_peripheral_pll(clk_ctrl);
 541         pll_rate = zynqmp_clk_get_pll_rate(priv, pll);
 542         if (IS_ERR_VALUE(pll_rate))
 543                 return pll_rate;
 544
 545         clk_ctrl &= ~CLK_CTRL_DIV0_MASK;
 546         if (two_divs) {
 547                 clk_ctrl &= ~CLK_CTRL_DIV1_MASK;
 548                 new_rate = zynqmp_clk_calc_peripheral_two_divs(rate, pll_rate,
 549                                 &div0, &div1);
 550                 clk_ctrl |= div1 << CLK_CTRL_DIV1_SHIFT;
 551         } else {
 552                 div0 = DIV_ROUND_CLOSEST(pll_rate, rate);
 553                 if (div0 > ZYNQ_CLK_MAXDIV)
 554                         div0 = ZYNQ_CLK_MAXDIV;
 555                 new_rate = DIV_ROUND_CLOSEST(rate, div0);
 556         }
 557         clk_ctrl |= div0 << CLK_CTRL_DIV0_SHIFT;
 558
 559         mask = (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT) |
 560                (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT);
 561
 562         ret = zynqmp_mmio_write(reg, mask, clk_ctrl);
 563         if (ret) {
 564                 printf("%s mio write fail\n", __func__);
 565                 return -EIO;
 566         }
 567
 568         return new_rate;
 569 }
 570
 571 static ulong zynqmp_clk_get_rate(struct clk *clk)
 572 {
 573         struct zynqmp_clk_priv *priv = dev_get_priv(clk->dev);
 574         enum zynqmp_clk id = clk->id;
 575         bool two_divs = false;
 576
 577         switch (id) {
 578         case iopll ... vpll:
 579                 return zynqmp_clk_get_pll_rate(priv, id);
 580         case acpu:
 581                 return zynqmp_clk_get_cpu_rate(priv, id);
 582         case ddr_ref:
 583                 return zynqmp_clk_get_ddr_rate(priv);
 584         case gem0_ref ... gem3_ref:
 585         case qspi_ref ... can1_ref:
 586         case pl0 ... pl3:
 587                 two_divs = true;
 588                 return zynqmp_clk_get_peripheral_rate(priv, id, two_divs);
 589         case wdt:
 590                 two_divs = true;
 591                 return zynqmp_clk_get_wdt_rate(priv, id, two_divs);
 592         default:
 593                 return -ENXIO;
 594         }
 595 }
 596
 597 static ulong zynqmp_clk_set_rate(struct clk *clk, ulong rate)
 598 {
 599         struct zynqmp_clk_priv *priv = dev_get_priv(clk->dev);
 600         enum zynqmp_clk id = clk->id;
 601         bool two_divs = true;
 602
 603         switch (id) {
 604         case gem0_ref ... gem3_ref:
 605         case qspi_ref ... can1_ref:
 606                 return zynqmp_clk_set_peripheral_rate(priv, id,
 607                                                       rate, two_divs);
 608         default:
 609                 return -ENXIO;
 610         }
 611 }
 612
 613 int soc_clk_dump(void)
 614 {
 615         struct udevice *dev;
 616         int i, ret;
 617
 618         ret = uclass_get_device_by_driver(UCLASS_CLK,
 619                 DM_GET_DRIVER(zynqmp_clk), &dev);
 620         if (ret)
 621                 return ret;
 622
 623         printf("clk\t\tfrequency\n");
 624         for (i = 0; i < clk_max; i++) {
 625                 const char *name = clk_names[i];
 626                 if (name) {
 627                         struct clk clk;
 628                         unsigned long rate;
 629
 630                         clk.id = i;
 631                         ret = clk_request(dev, &clk);
 632                         if (ret < 0)
 633                                 return ret;
 634
 635                         rate = clk_get_rate(&clk);
 636
 637                         clk_free(&clk);
 638
 639                         if ((rate == (unsigned long)-ENOSYS) ||
 640                             (rate == (unsigned long)-ENXIO) ||
 641                             (rate == (unsigned long)-EIO))
 642                                 printf("%10s%20s\n", name, "unknown");
 643                         else
 644                                 printf("%10s%20lu\n", name, rate);
 645                 }
 646         }
 647
 648         return 0;
 649 }
 650
 651 static int zynqmp_get_freq_by_name(char *name, struct udevice *dev, ulong *freq)
 652 {
 653         struct clk clk;
 654         int ret;
 655
 656         ret = clk_get_by_name(dev, name, &clk);
 657         if (ret < 0) {
 658                 dev_err(dev, "failed to get %s\n", name);
 659                 return ret;
 660         }
 661
 662         *freq = clk_get_rate(&clk);
 663         if (IS_ERR_VALUE(*freq)) {
 664                 dev_err(dev, "failed to get rate %s\n", name);
 665                 return -EINVAL;
 666         }
 667
 668         return 0;
 669 }
 670 static int zynqmp_clk_probe(struct udevice *dev)
 671 {
 672         int ret;
 673         struct zynqmp_clk_priv *priv = dev_get_priv(dev);
 674
 675         debug("%s\n", __func__);
 676         ret = zynqmp_get_freq_by_name("pss_ref_clk", dev, &priv->ps_clk_freq);
 677         if (ret < 0)
 678                 return -EINVAL;
 679
 680         ret = zynqmp_get_freq_by_name("video_clk", dev, &priv->video_clk);
 681         if (ret < 0)
 682                 return -EINVAL;
 683
 684         ret = zynqmp_get_freq_by_name("pss_alt_ref_clk", dev,
 685                                       &priv->pss_alt_ref_clk);
 686         if (ret < 0)
 687                 return -EINVAL;
 688
 689         ret = zynqmp_get_freq_by_name("aux_ref_clk", dev, &priv->aux_ref_clk);
 690         if (ret < 0)
 691                 return -EINVAL;
 692
 693         ret = zynqmp_get_freq_by_name("gt_crx_ref_clk", dev,
 694                                       &priv->gt_crx_ref_clk);
 695         if (ret < 0)
 696                 return -EINVAL;
 697
 698         return 0;
 699 }
 700
 701 static struct clk_ops zynqmp_clk_ops = {
 702         .set_rate = zynqmp_clk_set_rate,
 703         .get_rate = zynqmp_clk_get_rate,
 704 };
 705
 706 static const struct udevice_id zynqmp_clk_ids[] = {
 707         { .compatible = "xlnx,zynqmp-clk" },
 708         { }
 709 };
 710
 711 U_BOOT_DRIVER(zynqmp_clk) = {
 712         .name = "zynqmp-clk",
 713         .id = UCLASS_CLK,
 714         .of_match = zynqmp_clk_ids,
 715         .probe = zynqmp_clk_probe,
 716         .ops = &zynqmp_clk_ops,
 717         .priv_auto_alloc_size = sizeof(struct zynqmp_clk_priv),
 718 };