drivers/clk/clk_stm32mp1.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   4  */
   5
   6 #include <common.h>
   7 #include <clk-uclass.h>
   8 #include <div64.h>
   9 #include <dm.h>
  10 #include <regmap.h>
  11 #include <spl.h>
  12 #include <syscon.h>
  13 #include <linux/io.h>
  14 #include <linux/iopoll.h>
  15 #include <dt-bindings/clock/stm32mp1-clks.h>
  16 #include <dt-bindings/clock/stm32mp1-clksrc.h>
  17
  18 #ifndef CONFIG_STM32MP1_TRUSTED
  19 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
  20 /* activate clock tree initialization in the driver */
  21 #define STM32MP1_CLOCK_TREE_INIT
  22 #endif
  23 #endif
  24
  25 #define MAX_HSI_HZ              64000000
  26
  27 /* TIMEOUT */
  28 #define TIMEOUT_200MS           200000
  29 #define TIMEOUT_1S              1000000
  30
  31 /* STGEN registers */
  32 #define STGENC_CNTCR            0x00
  33 #define STGENC_CNTSR            0x04
  34 #define STGENC_CNTCVL           0x08
  35 #define STGENC_CNTCVU           0x0C
  36 #define STGENC_CNTFID0          0x20
  37
  38 #define STGENC_CNTCR_EN         BIT(0)
  39
  40 /* RCC registers */
  41 #define RCC_OCENSETR            0x0C
  42 #define RCC_OCENCLRR            0x10
  43 #define RCC_HSICFGR             0x18
  44 #define RCC_MPCKSELR            0x20
  45 #define RCC_ASSCKSELR           0x24
  46 #define RCC_RCK12SELR           0x28
  47 #define RCC_MPCKDIVR            0x2C
  48 #define RCC_AXIDIVR             0x30
  49 #define RCC_APB4DIVR            0x3C
  50 #define RCC_APB5DIVR            0x40
  51 #define RCC_RTCDIVR             0x44
  52 #define RCC_MSSCKSELR           0x48
  53 #define RCC_PLL1CR              0x80
  54 #define RCC_PLL1CFGR1           0x84
  55 #define RCC_PLL1CFGR2           0x88
  56 #define RCC_PLL1FRACR           0x8C
  57 #define RCC_PLL1CSGR            0x90
  58 #define RCC_PLL2CR              0x94
  59 #define RCC_PLL2CFGR1           0x98
  60 #define RCC_PLL2CFGR2           0x9C
  61 #define RCC_PLL2FRACR           0xA0
  62 #define RCC_PLL2CSGR            0xA4
  63 #define RCC_I2C46CKSELR         0xC0
  64 #define RCC_CPERCKSELR          0xD0
  65 #define RCC_STGENCKSELR         0xD4
  66 #define RCC_DDRITFCR            0xD8
  67 #define RCC_BDCR                0x140
  68 #define RCC_RDLSICR             0x144
  69 #define RCC_MP_APB4ENSETR       0x200
  70 #define RCC_MP_APB5ENSETR       0x208
  71 #define RCC_MP_AHB5ENSETR       0x210
  72 #define RCC_MP_AHB6ENSETR       0x218
  73 #define RCC_OCRDYR              0x808
  74 #define RCC_DBGCFGR             0x80C
  75 #define RCC_RCK3SELR            0x820
  76 #define RCC_RCK4SELR            0x824
  77 #define RCC_MCUDIVR             0x830
  78 #define RCC_APB1DIVR            0x834
  79 #define RCC_APB2DIVR            0x838
  80 #define RCC_APB3DIVR            0x83C
  81 #define RCC_PLL3CR              0x880
  82 #define RCC_PLL3CFGR1           0x884
  83 #define RCC_PLL3CFGR2           0x888
  84 #define RCC_PLL3FRACR           0x88C
  85 #define RCC_PLL3CSGR            0x890
  86 #define RCC_PLL4CR              0x894
  87 #define RCC_PLL4CFGR1           0x898
  88 #define RCC_PLL4CFGR2           0x89C
  89 #define RCC_PLL4FRACR           0x8A0
  90 #define RCC_PLL4CSGR            0x8A4
  91 #define RCC_I2C12CKSELR         0x8C0
  92 #define RCC_I2C35CKSELR         0x8C4
  93 #define RCC_SPI2S1CKSELR        0x8D8
  94 #define RCC_UART6CKSELR         0x8E4
  95 #define RCC_UART24CKSELR        0x8E8
  96 #define RCC_UART35CKSELR        0x8EC
  97 #define RCC_UART78CKSELR        0x8F0
  98 #define RCC_SDMMC12CKSELR       0x8F4
  99 #define RCC_SDMMC3CKSELR        0x8F8
 100 #define RCC_ETHCKSELR           0x8FC
 101 #define RCC_QSPICKSELR          0x900
 102 #define RCC_FMCCKSELR           0x904
 103 #define RCC_USBCKSELR           0x91C
 104 #define RCC_DSICKSELR           0x924
 105 #define RCC_ADCCKSELR           0x928
 106 #define RCC_MP_APB1ENSETR       0xA00
 107 #define RCC_MP_APB2ENSETR       0XA08
 108 #define RCC_MP_APB3ENSETR       0xA10
 109 #define RCC_MP_AHB2ENSETR       0xA18
 110 #define RCC_MP_AHB3ENSETR       0xA20
 111 #define RCC_MP_AHB4ENSETR       0xA28
 112
 113 /* used for most of SELR register */
 114 #define RCC_SELR_SRC_MASK       GENMASK(2, 0)
 115 #define RCC_SELR_SRCRDY         BIT(31)
 116
 117 /* Values of RCC_MPCKSELR register */
 118 #define RCC_MPCKSELR_HSI        0
 119 #define RCC_MPCKSELR_HSE        1
 120 #define RCC_MPCKSELR_PLL        2
 121 #define RCC_MPCKSELR_PLL_MPUDIV 3
 122
 123 /* Values of RCC_ASSCKSELR register */
 124 #define RCC_ASSCKSELR_HSI       0
 125 #define RCC_ASSCKSELR_HSE       1
 126 #define RCC_ASSCKSELR_PLL       2
 127
 128 /* Values of RCC_MSSCKSELR register */
 129 #define RCC_MSSCKSELR_HSI       0
 130 #define RCC_MSSCKSELR_HSE       1
 131 #define RCC_MSSCKSELR_CSI       2
 132 #define RCC_MSSCKSELR_PLL       3
 133
 134 /* Values of RCC_CPERCKSELR register */
 135 #define RCC_CPERCKSELR_HSI      0
 136 #define RCC_CPERCKSELR_CSI      1
 137 #define RCC_CPERCKSELR_HSE      2
 138
 139 /* used for most of DIVR register : max div for RTC */
 140 #define RCC_DIVR_DIV_MASK       GENMASK(5, 0)
 141 #define RCC_DIVR_DIVRDY         BIT(31)
 142
 143 /* Masks for specific DIVR registers */
 144 #define RCC_APBXDIV_MASK        GENMASK(2, 0)
 145 #define RCC_MPUDIV_MASK         GENMASK(2, 0)
 146 #define RCC_AXIDIV_MASK         GENMASK(2, 0)
 147 #define RCC_MCUDIV_MASK         GENMASK(3, 0)
 148
 149 /*  offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
 150 #define RCC_MP_ENCLRR_OFFSET    4
 151
 152 /* Fields of RCC_BDCR register */
 153 #define RCC_BDCR_LSEON          BIT(0)
 154 #define RCC_BDCR_LSEBYP         BIT(1)
 155 #define RCC_BDCR_LSERDY         BIT(2)
 156 #define RCC_BDCR_DIGBYP         BIT(3)
 157 #define RCC_BDCR_LSEDRV_MASK    GENMASK(5, 4)
 158 #define RCC_BDCR_LSEDRV_SHIFT   4
 159 #define RCC_BDCR_LSECSSON       BIT(8)
 160 #define RCC_BDCR_RTCCKEN        BIT(20)
 161 #define RCC_BDCR_RTCSRC_MASK    GENMASK(17, 16)
 162 #define RCC_BDCR_RTCSRC_SHIFT   16
 163
 164 /* Fields of RCC_RDLSICR register */
 165 #define RCC_RDLSICR_LSION       BIT(0)
 166 #define RCC_RDLSICR_LSIRDY      BIT(1)
 167
 168 /* used for ALL PLLNCR registers */
 169 #define RCC_PLLNCR_PLLON        BIT(0)
 170 #define RCC_PLLNCR_PLLRDY       BIT(1)
 171 #define RCC_PLLNCR_SSCG_CTRL    BIT(2)
 172 #define RCC_PLLNCR_DIVPEN       BIT(4)
 173 #define RCC_PLLNCR_DIVQEN       BIT(5)
 174 #define RCC_PLLNCR_DIVREN       BIT(6)
 175 #define RCC_PLLNCR_DIVEN_SHIFT  4
 176
 177 /* used for ALL PLLNCFGR1 registers */
 178 #define RCC_PLLNCFGR1_DIVM_SHIFT        16
 179 #define RCC_PLLNCFGR1_DIVM_MASK         GENMASK(21, 16)
 180 #define RCC_PLLNCFGR1_DIVN_SHIFT        0
 181 #define RCC_PLLNCFGR1_DIVN_MASK         GENMASK(8, 0)
 182 /* only for PLL3 and PLL4 */
 183 #define RCC_PLLNCFGR1_IFRGE_SHIFT       24
 184 #define RCC_PLLNCFGR1_IFRGE_MASK        GENMASK(25, 24)
 185
 186 /* used for ALL PLLNCFGR2 registers , using stm32mp1_div_id */
 187 #define RCC_PLLNCFGR2_SHIFT(div_id)     ((div_id) * 8)
 188 #define RCC_PLLNCFGR2_DIVX_MASK         GENMASK(6, 0)
 189 #define RCC_PLLNCFGR2_DIVP_SHIFT        RCC_PLLNCFGR2_SHIFT(_DIV_P)
 190 #define RCC_PLLNCFGR2_DIVP_MASK         GENMASK(6, 0)
 191 #define RCC_PLLNCFGR2_DIVQ_SHIFT        RCC_PLLNCFGR2_SHIFT(_DIV_Q)
 192 #define RCC_PLLNCFGR2_DIVQ_MASK         GENMASK(14, 8)
 193 #define RCC_PLLNCFGR2_DIVR_SHIFT        RCC_PLLNCFGR2_SHIFT(_DIV_R)
 194 #define RCC_PLLNCFGR2_DIVR_MASK         GENMASK(22, 16)
 195
 196 /* used for ALL PLLNFRACR registers */
 197 #define RCC_PLLNFRACR_FRACV_SHIFT       3
 198 #define RCC_PLLNFRACR_FRACV_MASK        GENMASK(15, 3)
 199 #define RCC_PLLNFRACR_FRACLE            BIT(16)
 200
 201 /* used for ALL PLLNCSGR registers */
 202 #define RCC_PLLNCSGR_INC_STEP_SHIFT     16
 203 #define RCC_PLLNCSGR_INC_STEP_MASK      GENMASK(30, 16)
 204 #define RCC_PLLNCSGR_MOD_PER_SHIFT      0
 205 #define RCC_PLLNCSGR_MOD_PER_MASK       GENMASK(12, 0)
 206 #define RCC_PLLNCSGR_SSCG_MODE_SHIFT    15
 207 #define RCC_PLLNCSGR_SSCG_MODE_MASK     BIT(15)
 208
 209 /* used for RCC_OCENSETR and RCC_OCENCLRR registers */
 210 #define RCC_OCENR_HSION                 BIT(0)
 211 #define RCC_OCENR_CSION                 BIT(4)
 212 #define RCC_OCENR_DIGBYP                BIT(7)
 213 #define RCC_OCENR_HSEON                 BIT(8)
 214 #define RCC_OCENR_HSEBYP                BIT(10)
 215 #define RCC_OCENR_HSECSSON              BIT(11)
 216
 217 /* Fields of RCC_OCRDYR register */
 218 #define RCC_OCRDYR_HSIRDY               BIT(0)
 219 #define RCC_OCRDYR_HSIDIVRDY            BIT(2)
 220 #define RCC_OCRDYR_CSIRDY               BIT(4)
 221 #define RCC_OCRDYR_HSERDY               BIT(8)
 222
 223 /* Fields of DDRITFCR register */
 224 #define RCC_DDRITFCR_DDRCKMOD_MASK      GENMASK(22, 20)
 225 #define RCC_DDRITFCR_DDRCKMOD_SHIFT     20
 226 #define RCC_DDRITFCR_DDRCKMOD_SSR       0
 227
 228 /* Fields of RCC_HSICFGR register */
 229 #define RCC_HSICFGR_HSIDIV_MASK         GENMASK(1, 0)
 230
 231 /* used for MCO related operations */
 232 #define RCC_MCOCFG_MCOON                BIT(12)
 233 #define RCC_MCOCFG_MCODIV_MASK          GENMASK(7, 4)
 234 #define RCC_MCOCFG_MCODIV_SHIFT         4
 235 #define RCC_MCOCFG_MCOSRC_MASK          GENMASK(2, 0)
 236
 237 enum stm32mp1_parent_id {
 238 /*
 239  * _HSI, _HSE, _CSI, _LSI, _LSE should not be moved
 240  * they are used as index in osc[] as entry point
 241  */
 242         _HSI,
 243         _HSE,
 244         _CSI,
 245         _LSI,
 246         _LSE,
 247         _I2S_CKIN,
 248         NB_OSC,
 249
 250 /* other parent source */
 251         _HSI_KER = NB_OSC,
 252         _HSE_KER,
 253         _HSE_KER_DIV2,
 254         _CSI_KER,
 255         _PLL1_P,
 256         _PLL1_Q,
 257         _PLL1_R,
 258         _PLL2_P,
 259         _PLL2_Q,
 260         _PLL2_R,
 261         _PLL3_P,
 262         _PLL3_Q,
 263         _PLL3_R,
 264         _PLL4_P,
 265         _PLL4_Q,
 266         _PLL4_R,
 267         _ACLK,
 268         _PCLK1,
 269         _PCLK2,
 270         _PCLK3,
 271         _PCLK4,
 272         _PCLK5,
 273         _HCLK6,
 274         _HCLK2,
 275         _CK_PER,
 276         _CK_MPU,
 277         _CK_MCU,
 278         _DSI_PHY,
 279         _USB_PHY_48,
 280         _PARENT_NB,
 281         _UNKNOWN_ID = 0xff,
 282 };
 283
 284 enum stm32mp1_parent_sel {
 285         _I2C12_SEL,
 286         _I2C35_SEL,
 287         _I2C46_SEL,
 288         _UART6_SEL,
 289         _UART24_SEL,
 290         _UART35_SEL,
 291         _UART78_SEL,
 292         _SDMMC12_SEL,
 293         _SDMMC3_SEL,
 294         _ETH_SEL,
 295         _QSPI_SEL,
 296         _FMC_SEL,
 297         _USBPHY_SEL,
 298         _USBO_SEL,
 299         _STGEN_SEL,
 300         _DSI_SEL,
 301         _ADC12_SEL,
 302         _SPI1_SEL,
 303         _RTC_SEL,
 304         _PARENT_SEL_NB,
 305         _UNKNOWN_SEL = 0xff,
 306 };
 307
 308 enum stm32mp1_pll_id {
 309         _PLL1,
 310         _PLL2,
 311         _PLL3,
 312         _PLL4,
 313         _PLL_NB
 314 };
 315
 316 enum stm32mp1_div_id {
 317         _DIV_P,
 318         _DIV_Q,
 319         _DIV_R,
 320         _DIV_NB,
 321 };
 322
 323 enum stm32mp1_clksrc_id {
 324         CLKSRC_MPU,
 325         CLKSRC_AXI,
 326         CLKSRC_MCU,
 327         CLKSRC_PLL12,
 328         CLKSRC_PLL3,
 329         CLKSRC_PLL4,
 330         CLKSRC_RTC,
 331         CLKSRC_MCO1,
 332         CLKSRC_MCO2,
 333         CLKSRC_NB
 334 };
 335
 336 enum stm32mp1_clkdiv_id {
 337         CLKDIV_MPU,
 338         CLKDIV_AXI,
 339         CLKDIV_MCU,
 340         CLKDIV_APB1,
 341         CLKDIV_APB2,
 342         CLKDIV_APB3,
 343         CLKDIV_APB4,
 344         CLKDIV_APB5,
 345         CLKDIV_RTC,
 346         CLKDIV_MCO1,
 347         CLKDIV_MCO2,
 348         CLKDIV_NB
 349 };
 350
 351 enum stm32mp1_pllcfg {
 352         PLLCFG_M,
 353         PLLCFG_N,
 354         PLLCFG_P,
 355         PLLCFG_Q,
 356         PLLCFG_R,
 357         PLLCFG_O,
 358         PLLCFG_NB
 359 };
 360
 361 enum stm32mp1_pllcsg {
 362         PLLCSG_MOD_PER,
 363         PLLCSG_INC_STEP,
 364         PLLCSG_SSCG_MODE,
 365         PLLCSG_NB
 366 };
 367
 368 enum stm32mp1_plltype {
 369         PLL_800,
 370         PLL_1600,
 371         PLL_TYPE_NB
 372 };
 373
 374 struct stm32mp1_pll {
 375         u8 refclk_min;
 376         u8 refclk_max;
 377         u8 divn_max;
 378 };
 379
 380 struct stm32mp1_clk_gate {
 381         u16 offset;
 382         u8 bit;
 383         u8 index;
 384         u8 set_clr;
 385         u8 sel;
 386         u8 fixed;
 387 };
 388
 389 struct stm32mp1_clk_sel {
 390         u16 offset;
 391         u8 src;
 392         u8 msk;
 393         u8 nb_parent;
 394         const u8 *parent;
 395 };
 396
 397 #define REFCLK_SIZE 4
 398 struct stm32mp1_clk_pll {
 399         enum stm32mp1_plltype plltype;
 400         u16 rckxselr;
 401         u16 pllxcfgr1;
 402         u16 pllxcfgr2;
 403         u16 pllxfracr;
 404         u16 pllxcr;
 405         u16 pllxcsgr;
 406         u8 refclk[REFCLK_SIZE];
 407 };
 408
 409 struct stm32mp1_clk_data {
 410         const struct stm32mp1_clk_gate *gate;
 411         const struct stm32mp1_clk_sel *sel;
 412         const struct stm32mp1_clk_pll *pll;
 413         const int nb_gate;
 414 };
 415
 416 struct stm32mp1_clk_priv {
 417         fdt_addr_t base;
 418         const struct stm32mp1_clk_data *data;
 419         ulong osc[NB_OSC];
 420         struct udevice *osc_dev[NB_OSC];
 421 };
 422
 423 #define STM32MP1_CLK(off, b, idx, s)            \
 424         {                                       \
 425                 .offset = (off),                \
 426                 .bit = (b),                     \
 427                 .index = (idx),                 \
 428                 .set_clr = 0,                   \
 429                 .sel = (s),                     \
 430                 .fixed = _UNKNOWN_ID,           \
 431         }
 432
 433 #define STM32MP1_CLK_F(off, b, idx, f)          \
 434         {                                       \
 435                 .offset = (off),                \
 436                 .bit = (b),                     \
 437                 .index = (idx),                 \
 438                 .set_clr = 0,                   \
 439                 .sel = _UNKNOWN_SEL,            \
 440                 .fixed = (f),                   \
 441         }
 442
 443 #define STM32MP1_CLK_SET_CLR(off, b, idx, s)    \
 444         {                                       \
 445                 .offset = (off),                \
 446                 .bit = (b),                     \
 447                 .index = (idx),                 \
 448                 .set_clr = 1,                   \
 449                 .sel = (s),                     \
 450                 .fixed = _UNKNOWN_ID,           \
 451         }
 452
 453 #define STM32MP1_CLK_SET_CLR_F(off, b, idx, f)  \
 454         {                                       \
 455                 .offset = (off),                \
 456                 .bit = (b),                     \
 457                 .index = (idx),                 \
 458                 .set_clr = 1,                   \
 459                 .sel = _UNKNOWN_SEL,            \
 460                 .fixed = (f),                   \
 461         }
 462
 463 #define STM32MP1_CLK_PARENT(idx, off, s, m, p)   \
 464         [(idx)] = {                             \
 465                 .offset = (off),                \
 466                 .src = (s),                     \
 467                 .msk = (m),                     \
 468                 .parent = (p),                  \
 469                 .nb_parent = ARRAY_SIZE((p))    \
 470         }
 471
 472 #define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, off4, off5, off6,\
 473                         p1, p2, p3, p4) \
 474         [(idx)] = {                             \
 475                 .plltype = (type),                      \
 476                 .rckxselr = (off1),             \
 477                 .pllxcfgr1 = (off2),            \
 478                 .pllxcfgr2 = (off3),            \
 479                 .pllxfracr = (off4),            \
 480                 .pllxcr = (off5),               \
 481                 .pllxcsgr = (off6),             \
 482                 .refclk[0] = (p1),              \
 483                 .refclk[1] = (p2),              \
 484                 .refclk[2] = (p3),              \
 485                 .refclk[3] = (p4),              \
 486         }
 487
 488 static const u8 stm32mp1_clks[][2] = {
 489         {CK_PER, _CK_PER},
 490         {CK_MPU, _CK_MPU},
 491         {CK_AXI, _ACLK},
 492         {CK_MCU, _CK_MCU},
 493         {CK_HSE, _HSE},
 494         {CK_CSI, _CSI},
 495         {CK_LSI, _LSI},
 496         {CK_LSE, _LSE},
 497         {CK_HSI, _HSI},
 498         {CK_HSE_DIV2, _HSE_KER_DIV2},
 499 };
 500
 501 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
 502         STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL),
 503         STM32MP1_CLK(RCC_DDRITFCR, 1, DDRC1LP, _UNKNOWN_SEL),
 504         STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL),
 505         STM32MP1_CLK(RCC_DDRITFCR, 3, DDRC2LP, _UNKNOWN_SEL),
 506         STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
 507         STM32MP1_CLK(RCC_DDRITFCR, 5, DDRPHYCLP, _UNKNOWN_SEL),
 508         STM32MP1_CLK(RCC_DDRITFCR, 6, DDRCAPB, _UNKNOWN_SEL),
 509         STM32MP1_CLK(RCC_DDRITFCR, 7, DDRCAPBLP, _UNKNOWN_SEL),
 510         STM32MP1_CLK(RCC_DDRITFCR, 8, AXIDCG, _UNKNOWN_SEL),
 511         STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL),
 512         STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL),
 513
 514         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
 515         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
 516         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
 517         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL),
 518         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL),
 519         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL),
 520         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL),
 521         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL),
 522         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL),
 523         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
 524
 525         STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 8, SPI1_K, _SPI1_SEL),
 526         STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
 527
 528         STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3),
 529
 530         STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 0, LTDC_PX, _PLL4_Q),
 531         STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 4, DSI_PX, _PLL4_Q),
 532         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 4, DSI_K, _DSI_SEL),
 533         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
 534         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
 535         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
 536
 537         STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
 538         STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5),
 539         STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
 540
 541         STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB2ENSETR, 5, ADC12, _HCLK2),
 542         STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 5, ADC12_K, _ADC12_SEL),
 543         STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
 544         STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
 545
 546         STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 11, HSEM, _UNKNOWN_SEL),
 547         STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 12, IPCC, _UNKNOWN_SEL),
 548
 549         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
 550         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
 551         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
 552         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL),
 553         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL),
 554         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL),
 555         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL),
 556         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL),
 557         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL),
 558         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL),
 559         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
 560
 561         STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
 562
 563         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK_K, _ETH_SEL),
 564         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL),
 565         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL),
 566         STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK),
 567         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
 568         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
 569         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL),
 570         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL),
 571         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL),
 572
 573         STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
 574
 575         STM32MP1_CLK(RCC_BDCR, 20, RTC, _RTC_SEL),
 576 };
 577
 578 static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
 579 static const u8 i2c35_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
 580 static const u8 i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER};
 581 static const u8 uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
 582                                         _HSE_KER};
 583 static const u8 uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 584                                          _HSE_KER};
 585 static const u8 uart35_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 586                                          _HSE_KER};
 587 static const u8 uart78_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 588                                          _HSE_KER};
 589 static const u8 sdmmc12_parents[] = {_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER};
 590 static const u8 sdmmc3_parents[] = {_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER};
 591 static const u8 eth_parents[] = {_PLL4_P, _PLL3_Q};
 592 static const u8 qspi_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
 593 static const u8 fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
 594 static const u8 usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2};
 595 static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48};
 596 static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER};
 597 static const u8 dsi_parents[] = {_DSI_PHY, _PLL4_P};
 598 static const u8 adc_parents[] = {_PLL4_R, _CK_PER, _PLL3_Q};
 599 static const u8 spi_parents[] = {_PLL4_P, _PLL3_Q, _I2S_CKIN, _CK_PER,
 600                                  _PLL3_R};
 601 static const u8 rtc_parents[] = {_UNKNOWN_ID, _LSE, _LSI, _HSE};
 602
 603 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
 604         STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents),
 605         STM32MP1_CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents),
 606         STM32MP1_CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents),
 607         STM32MP1_CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents),
 608         STM32MP1_CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7,
 609                             uart24_parents),
 610         STM32MP1_CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7,
 611                             uart35_parents),
 612         STM32MP1_CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7,
 613                             uart78_parents),
 614         STM32MP1_CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7,
 615                             sdmmc12_parents),
 616         STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7,
 617                             sdmmc3_parents),
 618         STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents),
 619         STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents),
 620         STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents),
 621         STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents),
 622         STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
 623         STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
 624         STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents),
 625         STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x1, adc_parents),
 626         STM32MP1_CLK_PARENT(_SPI1_SEL, RCC_SPI2S1CKSELR, 0, 0x7, spi_parents),
 627         STM32MP1_CLK_PARENT(_RTC_SEL, RCC_BDCR, RCC_BDCR_RTCSRC_SHIFT,
 628                             (RCC_BDCR_RTCSRC_MASK >> RCC_BDCR_RTCSRC_SHIFT),
 629                             rtc_parents),
 630 };
 631
 632 #ifdef STM32MP1_CLOCK_TREE_INIT
 633 /* define characteristic of PLL according type */
 634 #define DIVN_MIN        24
 635 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
 636         [PLL_800] = {
 637                 .refclk_min = 4,
 638                 .refclk_max = 16,
 639                 .divn_max = 99,
 640                 },
 641         [PLL_1600] = {
 642                 .refclk_min = 8,
 643                 .refclk_max = 16,
 644                 .divn_max = 199,
 645                 },
 646 };
 647 #endif /* STM32MP1_CLOCK_TREE_INIT */
 648
 649 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = {
 650         STM32MP1_CLK_PLL(_PLL1, PLL_1600,
 651                          RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2,
 652                          RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR,
 653                          _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
 654         STM32MP1_CLK_PLL(_PLL2, PLL_1600,
 655                          RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2,
 656                          RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR,
 657                          _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
 658         STM32MP1_CLK_PLL(_PLL3, PLL_800,
 659                          RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2,
 660                          RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR,
 661                          _HSI, _HSE, _CSI, _UNKNOWN_ID),
 662         STM32MP1_CLK_PLL(_PLL4, PLL_800,
 663                          RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2,
 664                          RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR,
 665                          _HSI, _HSE, _CSI, _I2S_CKIN),
 666 };
 667
 668 /* Prescaler table lookups for clock computation */
 669 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */
 670 static const u8 stm32mp1_mcu_div[16] = {
 671         0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9
 672 };
 673
 674 /* div = /1 /2 /4 /8 /16 : same divider for pmu and apbx*/
 675 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div
 676 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div
 677 static const u8 stm32mp1_mpu_apbx_div[8] = {
 678         0, 1, 2, 3, 4, 4, 4, 4
 679 };
 680
 681 /* div = /1 /2 /3 /4 */
 682 static const u8 stm32mp1_axi_div[8] = {
 683         1, 2, 3, 4, 4, 4, 4, 4
 684 };
 685
 686 static const __maybe_unused
 687 char * const stm32mp1_clk_parent_name[_PARENT_NB] = {
 688         [_HSI] = "HSI",
 689         [_HSE] = "HSE",
 690         [_CSI] = "CSI",
 691         [_LSI] = "LSI",
 692         [_LSE] = "LSE",
 693         [_I2S_CKIN] = "I2S_CKIN",
 694         [_HSI_KER] = "HSI_KER",
 695         [_HSE_KER] = "HSE_KER",
 696         [_HSE_KER_DIV2] = "HSE_KER_DIV2",
 697         [_CSI_KER] = "CSI_KER",
 698         [_PLL1_P] = "PLL1_P",
 699         [_PLL1_Q] = "PLL1_Q",
 700         [_PLL1_R] = "PLL1_R",
 701         [_PLL2_P] = "PLL2_P",
 702         [_PLL2_Q] = "PLL2_Q",
 703         [_PLL2_R] = "PLL2_R",
 704         [_PLL3_P] = "PLL3_P",
 705         [_PLL3_Q] = "PLL3_Q",
 706         [_PLL3_R] = "PLL3_R",
 707         [_PLL4_P] = "PLL4_P",
 708         [_PLL4_Q] = "PLL4_Q",
 709         [_PLL4_R] = "PLL4_R",
 710         [_ACLK] = "ACLK",
 711         [_PCLK1] = "PCLK1",
 712         [_PCLK2] = "PCLK2",
 713         [_PCLK3] = "PCLK3",
 714         [_PCLK4] = "PCLK4",
 715         [_PCLK5] = "PCLK5",
 716         [_HCLK6] = "KCLK6",
 717         [_HCLK2] = "HCLK2",
 718         [_CK_PER] = "CK_PER",
 719         [_CK_MPU] = "CK_MPU",
 720         [_CK_MCU] = "CK_MCU",
 721         [_USB_PHY_48] = "USB_PHY_48",
 722         [_DSI_PHY] = "DSI_PHY_PLL",
 723 };
 724
 725 static const __maybe_unused
 726 char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
 727         [_I2C12_SEL] = "I2C12",
 728         [_I2C35_SEL] = "I2C35",
 729         [_I2C46_SEL] = "I2C46",
 730         [_UART6_SEL] = "UART6",
 731         [_UART24_SEL] = "UART24",
 732         [_UART35_SEL] = "UART35",
 733         [_UART78_SEL] = "UART78",
 734         [_SDMMC12_SEL] = "SDMMC12",
 735         [_SDMMC3_SEL] = "SDMMC3",
 736         [_ETH_SEL] = "ETH",
 737         [_QSPI_SEL] = "QSPI",
 738         [_FMC_SEL] = "FMC",
 739         [_USBPHY_SEL] = "USBPHY",
 740         [_USBO_SEL] = "USBO",
 741         [_STGEN_SEL] = "STGEN",
 742         [_DSI_SEL] = "DSI",
 743         [_ADC12_SEL] = "ADC12",
 744         [_SPI1_SEL] = "SPI1",
 745         [_RTC_SEL] = "RTC",
 746 };
 747
 748 static const struct stm32mp1_clk_data stm32mp1_data = {
 749         .gate = stm32mp1_clk_gate,
 750         .sel = stm32mp1_clk_sel,
 751         .pll = stm32mp1_clk_pll,
 752         .nb_gate = ARRAY_SIZE(stm32mp1_clk_gate),
 753 };
 754
 755 static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx)
 756 {
 757         if (idx >= NB_OSC) {
 758                 debug("%s: clk id %d not found\n", __func__, idx);
 759                 return 0;
 760         }
 761
 762         debug("%s: clk id %d = %x : %ld kHz\n", __func__, idx,
 763               (u32)priv->osc[idx], priv->osc[idx] / 1000);
 764
 765         return priv->osc[idx];
 766 }
 767
 768 static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id)
 769 {
 770         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 771         int i, nb_clks = priv->data->nb_gate;
 772
 773         for (i = 0; i < nb_clks; i++) {
 774                 if (gate[i].index == id)
 775                         break;
 776         }
 777
 778         if (i == nb_clks) {
 779                 printf("%s: clk id %d not found\n", __func__, (u32)id);
 780                 return -EINVAL;
 781         }
 782
 783         return i;
 784 }
 785
 786 static int stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv,
 787                                 int i)
 788 {
 789         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 790
 791         if (gate[i].sel > _PARENT_SEL_NB) {
 792                 printf("%s: parents for clk id %d not found\n",
 793                        __func__, i);
 794                 return -EINVAL;
 795         }
 796
 797         return gate[i].sel;
 798 }
 799
 800 static int stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv *priv,
 801                                          int i)
 802 {
 803         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 804
 805         if (gate[i].fixed == _UNKNOWN_ID)
 806                 return -ENOENT;
 807
 808         return gate[i].fixed;
 809 }
 810
 811 static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv,
 812                                    unsigned long id)
 813 {
 814         const struct stm32mp1_clk_sel *sel = priv->data->sel;
 815         int i;
 816         int s, p;
 817         unsigned int idx;
 818
 819         for (idx = 0; idx < ARRAY_SIZE(stm32mp1_clks); idx++)
 820                 if (stm32mp1_clks[idx][0] == id)
 821                         return stm32mp1_clks[idx][1];
 822
 823         i = stm32mp1_clk_get_id(priv, id);
 824         if (i < 0)
 825                 return i;
 826
 827         p = stm32mp1_clk_get_fixed_parent(priv, i);
 828         if (p >= 0 && p < _PARENT_NB)
 829                 return p;
 830
 831         s = stm32mp1_clk_get_sel(priv, i);
 832         if (s < 0)
 833                 return s;
 834
 835         p = (readl(priv->base + sel[s].offset) >> sel[s].src) & sel[s].msk;
 836
 837         if (p < sel[s].nb_parent) {
 838 #ifdef DEBUG
 839                 debug("%s: %s clock is the parent %s of clk id %d\n", __func__,
 840                       stm32mp1_clk_parent_name[sel[s].parent[p]],
 841                       stm32mp1_clk_parent_sel_name[s],
 842                       (u32)id);
 843 #endif
 844                 return sel[s].parent[p];
 845         }
 846
 847         pr_err("%s: no parents defined for clk id %d\n",
 848                __func__, (u32)id);
 849
 850         return -EINVAL;
 851 }
 852
 853 static ulong  pll_get_fref_ck(struct stm32mp1_clk_priv *priv,
 854                               int pll_id)
 855 {
 856         const struct stm32mp1_clk_pll *pll = priv->data->pll;
 857         u32 selr;
 858         int src;
 859         ulong refclk;
 860
 861         /* Get current refclk */
 862         selr = readl(priv->base + pll[pll_id].rckxselr);
 863         src = selr & RCC_SELR_SRC_MASK;
 864
 865         refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]);
 866         debug("PLL%d : selr=%x refclk = %d kHz\n",
 867               pll_id, selr, (u32)(refclk / 1000));
 868
 869         return refclk;
 870 }
 871
 872 /*
 873  * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL
 874  * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1)
 875  * - PLL3 & PLL4 => return VCO     with Fpll_y_ck = FVCO / (DIVy + 1)
 876  * => in all the case Fpll_y_ck = pll_get_fvco() / (DIVy + 1)
 877  */
 878 static ulong pll_get_fvco(struct stm32mp1_clk_priv *priv,
 879                           int pll_id)
 880 {
 881         const struct stm32mp1_clk_pll *pll = priv->data->pll;
 882         int divm, divn;
 883         ulong refclk, fvco;
 884         u32 cfgr1, fracr;
 885
 886         cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1);
 887         fracr = readl(priv->base + pll[pll_id].pllxfracr);
 888
 889         divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
 890         divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
 891
 892         debug("PLL%d : cfgr1=%x fracr=%x DIVN=%d DIVM=%d\n",
 893               pll_id, cfgr1, fracr, divn, divm);
 894
 895         refclk = pll_get_fref_ck(priv, pll_id);
 896
 897         /* with FRACV :
 898          *   Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1)
 899          * without FRACV
 900          *   Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1)
 901          */
 902         if (fracr & RCC_PLLNFRACR_FRACLE) {
 903                 u32 fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK)
 904                             >> RCC_PLLNFRACR_FRACV_SHIFT;
 905                 fvco = (ulong)lldiv((unsigned long long)refclk *
 906                                      (((divn + 1) << 13) + fracv),
 907                                      ((unsigned long long)(divm + 1)) << 13);
 908         } else {
 909                 fvco = (ulong)(refclk * (divn + 1) / (divm + 1));
 910         }
 911         debug("PLL%d : %s = %ld\n", pll_id, __func__, fvco);
 912
 913         return fvco;
 914 }
 915
 916 static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
 917                                     int pll_id, int div_id)
 918 {
 919         const struct stm32mp1_clk_pll *pll = priv->data->pll;
 920         int divy;
 921         ulong dfout;
 922         u32 cfgr2;
 923
 924         debug("%s(%d, %d)\n", __func__, pll_id, div_id);
 925         if (div_id >= _DIV_NB)
 926                 return 0;
 927
 928         cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2);
 929         divy = (cfgr2 >> RCC_PLLNCFGR2_SHIFT(div_id)) & RCC_PLLNCFGR2_DIVX_MASK;
 930
 931         debug("PLL%d : cfgr2=%x DIVY=%d\n", pll_id, cfgr2, divy);
 932
 933         dfout = pll_get_fvco(priv, pll_id) / (divy + 1);
 934         debug("        => dfout = %d kHz\n", (u32)(dfout / 1000));
 935
 936         return dfout;
 937 }
 938
 939 static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
 940 {
 941         u32 reg;
 942         ulong clock = 0;
 943
 944         switch (p) {
 945         case _CK_MPU:
 946         /* MPU sub system */
 947                 reg = readl(priv->base + RCC_MPCKSELR);
 948                 switch (reg & RCC_SELR_SRC_MASK) {
 949                 case RCC_MPCKSELR_HSI:
 950                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
 951                         break;
 952                 case RCC_MPCKSELR_HSE:
 953                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
 954                         break;
 955                 case RCC_MPCKSELR_PLL:
 956                 case RCC_MPCKSELR_PLL_MPUDIV:
 957                         clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P);
 958                         if (p == RCC_MPCKSELR_PLL_MPUDIV) {
 959                                 reg = readl(priv->base + RCC_MPCKDIVR);
 960                                 clock /= stm32mp1_mpu_div[reg &
 961                                                           RCC_MPUDIV_MASK];
 962                         }
 963                         break;
 964                 }
 965                 break;
 966         /* AXI sub system */
 967         case _ACLK:
 968         case _HCLK2:
 969         case _HCLK6:
 970         case _PCLK4:
 971         case _PCLK5:
 972                 reg = readl(priv->base + RCC_ASSCKSELR);
 973                 switch (reg & RCC_SELR_SRC_MASK) {
 974                 case RCC_ASSCKSELR_HSI:
 975                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
 976                         break;
 977                 case RCC_ASSCKSELR_HSE:
 978                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
 979                         break;
 980                 case RCC_ASSCKSELR_PLL:
 981                         clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P);
 982                         break;
 983                 }
 984
 985                 /* System clock divider */
 986                 reg = readl(priv->base + RCC_AXIDIVR);
 987                 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK];
 988
 989                 switch (p) {
 990                 case _PCLK4:
 991                         reg = readl(priv->base + RCC_APB4DIVR);
 992                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
 993                         break;
 994                 case _PCLK5:
 995                         reg = readl(priv->base + RCC_APB5DIVR);
 996                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
 997                         break;
 998                 default:
 999                         break;
1000                 }
1001                 break;
1002         /* MCU sub system */
1003         case _CK_MCU:
1004         case _PCLK1:
1005         case _PCLK2:
1006         case _PCLK3:
1007                 reg = readl(priv->base + RCC_MSSCKSELR);
1008                 switch (reg & RCC_SELR_SRC_MASK) {
1009                 case RCC_MSSCKSELR_HSI:
1010                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
1011                         break;
1012                 case RCC_MSSCKSELR_HSE:
1013                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
1014                         break;
1015                 case RCC_MSSCKSELR_CSI:
1016                         clock = stm32mp1_clk_get_fixed(priv, _CSI);
1017                         break;
1018                 case RCC_MSSCKSELR_PLL:
1019                         clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_P);
1020                         break;
1021                 }
1022
1023                 /* MCU clock divider */
1024                 reg = readl(priv->base + RCC_MCUDIVR);
1025                 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK];
1026
1027                 switch (p) {
1028                 case _PCLK1:
1029                         reg = readl(priv->base + RCC_APB1DIVR);
1030                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1031                         break;
1032                 case _PCLK2:
1033                         reg = readl(priv->base + RCC_APB2DIVR);
1034                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1035                         break;
1036                 case _PCLK3:
1037                         reg = readl(priv->base + RCC_APB3DIVR);
1038                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1039                         break;
1040                 case _CK_MCU:
1041                 default:
1042                         break;
1043                 }
1044                 break;
1045         case _CK_PER:
1046                 reg = readl(priv->base + RCC_CPERCKSELR);
1047                 switch (reg & RCC_SELR_SRC_MASK) {
1048                 case RCC_CPERCKSELR_HSI:
1049                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
1050                         break;
1051                 case RCC_CPERCKSELR_HSE:
1052                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
1053                         break;
1054                 case RCC_CPERCKSELR_CSI:
1055                         clock = stm32mp1_clk_get_fixed(priv, _CSI);
1056                         break;
1057                 }
1058                 break;
1059         case _HSI:
1060         case _HSI_KER:
1061                 clock = stm32mp1_clk_get_fixed(priv, _HSI);
1062                 break;
1063         case _CSI:
1064         case _CSI_KER:
1065                 clock = stm32mp1_clk_get_fixed(priv, _CSI);
1066                 break;
1067         case _HSE:
1068         case _HSE_KER:
1069         case _HSE_KER_DIV2:
1070                 clock = stm32mp1_clk_get_fixed(priv, _HSE);
1071                 if (p == _HSE_KER_DIV2)
1072                         clock >>= 1;
1073                 break;
1074         case _LSI:
1075                 clock = stm32mp1_clk_get_fixed(priv, _LSI);
1076                 break;
1077         case _LSE:
1078                 clock = stm32mp1_clk_get_fixed(priv, _LSE);
1079                 break;
1080         /* PLL */
1081         case _PLL1_P:
1082         case _PLL1_Q:
1083         case _PLL1_R:
1084                 clock = stm32mp1_read_pll_freq(priv, _PLL1, p - _PLL1_P);
1085                 break;
1086         case _PLL2_P:
1087         case _PLL2_Q:
1088         case _PLL2_R:
1089                 clock = stm32mp1_read_pll_freq(priv, _PLL2, p - _PLL2_P);
1090                 break;
1091         case _PLL3_P:
1092         case _PLL3_Q:
1093         case _PLL3_R:
1094                 clock = stm32mp1_read_pll_freq(priv, _PLL3, p - _PLL3_P);
1095                 break;
1096         case _PLL4_P:
1097         case _PLL4_Q:
1098         case _PLL4_R:
1099                 clock = stm32mp1_read_pll_freq(priv, _PLL4, p - _PLL4_P);
1100                 break;
1101         /* other */
1102         case _USB_PHY_48:
1103                 clock = 48000000;
1104                 break;
1105         case _DSI_PHY:
1106         {
1107                 struct clk clk;
1108                 struct udevice *dev = NULL;
1109
1110                 if (!uclass_get_device_by_name(UCLASS_CLK, "ck_dsi_phy",
1111                                                &dev)) {
1112                         if (clk_request(dev, &clk)) {
1113                                 pr_err("ck_dsi_phy request");
1114                         } else {
1115                                 clk.id = 0;
1116                                 clock = clk_get_rate(&clk);
1117                         }
1118                 }
1119                 break;
1120         }
1121         default:
1122                 break;
1123         }
1124
1125         debug("%s(%d) clock = %lx : %ld kHz\n",
1126               __func__, p, clock, clock / 1000);
1127
1128         return clock;
1129 }
1130
1131 static int stm32mp1_clk_enable(struct clk *clk)
1132 {
1133         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1134         const struct stm32mp1_clk_gate *gate = priv->data->gate;
1135         int i = stm32mp1_clk_get_id(priv, clk->id);
1136
1137         if (i < 0)
1138                 return i;
1139
1140         if (gate[i].set_clr)
1141                 writel(BIT(gate[i].bit), priv->base + gate[i].offset);
1142         else
1143                 setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1144
1145         debug("%s: id clock %d has been enabled\n", __func__, (u32)clk->id);
1146
1147         return 0;
1148 }
1149
1150 static int stm32mp1_clk_disable(struct clk *clk)
1151 {
1152         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1153         const struct stm32mp1_clk_gate *gate = priv->data->gate;
1154         int i = stm32mp1_clk_get_id(priv, clk->id);
1155
1156         if (i < 0)
1157                 return i;
1158
1159         if (gate[i].set_clr)
1160                 writel(BIT(gate[i].bit),
1161                        priv->base + gate[i].offset
1162                        + RCC_MP_ENCLRR_OFFSET);
1163         else
1164                 clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1165
1166         debug("%s: id clock %d has been disabled\n", __func__, (u32)clk->id);
1167
1168         return 0;
1169 }
1170
1171 static ulong stm32mp1_clk_get_rate(struct clk *clk)
1172 {
1173         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1174         int p = stm32mp1_clk_get_parent(priv, clk->id);
1175         ulong rate;
1176
1177         if (p < 0)
1178                 return 0;
1179
1180         rate = stm32mp1_clk_get(priv, p);
1181
1182 #ifdef DEBUG
1183         debug("%s: computed rate for id clock %d is %d (parent is %s)\n",
1184               __func__, (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]);
1185 #endif
1186         return rate;
1187 }
1188
1189 #ifdef STM32MP1_CLOCK_TREE_INIT
1190 static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset,
1191                                 u32 mask_on)
1192 {
1193         u32 address = rcc + offset;
1194
1195         if (enable)
1196                 setbits_le32(address, mask_on);
1197         else
1198                 clrbits_le32(address, mask_on);
1199 }
1200
1201 static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on)
1202 {
1203         writel(mask_on, rcc + (enable ? RCC_OCENSETR : RCC_OCENCLRR));
1204 }
1205
1206 static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset,
1207                              u32 mask_rdy)
1208 {
1209         u32 mask_test = 0;
1210         u32 address = rcc + offset;
1211         u32 val;
1212         int ret;
1213
1214         if (enable)
1215                 mask_test = mask_rdy;
1216
1217         ret = readl_poll_timeout(address, val,
1218                                  (val & mask_rdy) == mask_test,
1219                                  TIMEOUT_1S);
1220
1221         if (ret)
1222                 pr_err("OSC %x @ %x timeout for enable=%d : 0x%x\n",
1223                        mask_rdy, address, enable, readl(address));
1224
1225         return ret;
1226 }
1227
1228 static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int digbyp,
1229                                 int lsedrv)
1230 {
1231         u32 value;
1232
1233         if (digbyp)
1234                 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_DIGBYP);
1235
1236         if (bypass || digbyp)
1237                 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP);
1238
1239         /*
1240          * warning: not recommended to switch directly from "high drive"
1241          * to "medium low drive", and vice-versa.
1242          */
1243         value = (readl(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK)
1244                 >> RCC_BDCR_LSEDRV_SHIFT;
1245
1246         while (value != lsedrv) {
1247                 if (value > lsedrv)
1248                         value--;
1249                 else
1250                         value++;
1251
1252                 clrsetbits_le32(rcc + RCC_BDCR,
1253                                 RCC_BDCR_LSEDRV_MASK,
1254                                 value << RCC_BDCR_LSEDRV_SHIFT);
1255         }
1256
1257         stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON);
1258 }
1259
1260 static void stm32mp1_lse_wait(fdt_addr_t rcc)
1261 {
1262         stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY);
1263 }
1264
1265 static void stm32mp1_lsi_set(fdt_addr_t rcc, int enable)
1266 {
1267         stm32mp1_ls_osc_set(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSION);
1268         stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY);
1269 }
1270
1271 static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int digbyp, int css)
1272 {
1273         if (digbyp)
1274                 writel(RCC_OCENR_DIGBYP, rcc + RCC_OCENSETR);
1275         if (bypass || digbyp)
1276                 writel(RCC_OCENR_HSEBYP, rcc + RCC_OCENSETR);
1277
1278         stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON);
1279         stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY);
1280
1281         if (css)
1282                 writel(RCC_OCENR_HSECSSON, rcc + RCC_OCENSETR);
1283 }
1284
1285 static void stm32mp1_csi_set(fdt_addr_t rcc, int enable)
1286 {
1287         stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_CSION);
1288         stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY);
1289 }
1290
1291 static void stm32mp1_hsi_set(fdt_addr_t rcc, int enable)
1292 {
1293         stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_HSION);
1294         stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_HSIRDY);
1295 }
1296
1297 static int stm32mp1_set_hsidiv(fdt_addr_t rcc, u8 hsidiv)
1298 {
1299         u32 address = rcc + RCC_OCRDYR;
1300         u32 val;
1301         int ret;
1302
1303         clrsetbits_le32(rcc + RCC_HSICFGR,
1304                         RCC_HSICFGR_HSIDIV_MASK,
1305                         RCC_HSICFGR_HSIDIV_MASK & hsidiv);
1306
1307         ret = readl_poll_timeout(address, val,
1308                                  val & RCC_OCRDYR_HSIDIVRDY,
1309                                  TIMEOUT_200MS);
1310         if (ret)
1311                 pr_err("HSIDIV failed @ 0x%x: 0x%x\n",
1312                        address, readl(address));
1313
1314         return ret;
1315 }
1316
1317 static int stm32mp1_hsidiv(fdt_addr_t rcc, ulong hsifreq)
1318 {
1319         u8 hsidiv;
1320         u32 hsidivfreq = MAX_HSI_HZ;
1321
1322         for (hsidiv = 0; hsidiv < 4; hsidiv++,
1323              hsidivfreq = hsidivfreq / 2)
1324                 if (hsidivfreq == hsifreq)
1325                         break;
1326
1327         if (hsidiv == 4) {
1328                 pr_err("clk-hsi frequency invalid");
1329                 return -1;
1330         }
1331
1332         if (hsidiv > 0)
1333                 return stm32mp1_set_hsidiv(rcc, hsidiv);
1334
1335         return 0;
1336 }
1337
1338 static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id)
1339 {
1340         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1341
1342         clrsetbits_le32(priv->base + pll[pll_id].pllxcr,
1343                         RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN |
1344                         RCC_PLLNCR_DIVREN,
1345                         RCC_PLLNCR_PLLON);
1346 }
1347
1348 static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output)
1349 {
1350         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1351         u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1352         u32 val;
1353         int ret;
1354
1355         ret = readl_poll_timeout(pllxcr, val, val & RCC_PLLNCR_PLLRDY,
1356                                  TIMEOUT_200MS);
1357
1358         if (ret) {
1359                 pr_err("PLL%d start failed @ 0x%x: 0x%x\n",
1360                        pll_id, pllxcr, readl(pllxcr));
1361                 return ret;
1362         }
1363
1364         /* start the requested output */
1365         setbits_le32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT);
1366
1367         return 0;
1368 }
1369
1370 static int pll_stop(struct stm32mp1_clk_priv *priv, int pll_id)
1371 {
1372         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1373         u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1374         u32 val;
1375
1376         /* stop all output */
1377         clrbits_le32(pllxcr,
1378                      RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN);
1379
1380         /* stop PLL */
1381         clrbits_le32(pllxcr, RCC_PLLNCR_PLLON);
1382
1383         /* wait PLL stopped */
1384         return readl_poll_timeout(pllxcr, val, (val & RCC_PLLNCR_PLLRDY) == 0,
1385                                   TIMEOUT_200MS);
1386 }
1387
1388 static void pll_config_output(struct stm32mp1_clk_priv *priv,
1389                               int pll_id, u32 *pllcfg)
1390 {
1391         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1392         fdt_addr_t rcc = priv->base;
1393         u32 value;
1394
1395         value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT)
1396                 & RCC_PLLNCFGR2_DIVP_MASK;
1397         value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT)
1398                  & RCC_PLLNCFGR2_DIVQ_MASK;
1399         value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT)
1400                  & RCC_PLLNCFGR2_DIVR_MASK;
1401         writel(value, rcc + pll[pll_id].pllxcfgr2);
1402 }
1403
1404 static int pll_config(struct stm32mp1_clk_priv *priv, int pll_id,
1405                       u32 *pllcfg, u32 fracv)
1406 {
1407         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1408         fdt_addr_t rcc = priv->base;
1409         enum stm32mp1_plltype type = pll[pll_id].plltype;
1410         int src;
1411         ulong refclk;
1412         u8 ifrge = 0;
1413         u32 value;
1414
1415         src = readl(priv->base + pll[pll_id].rckxselr) & RCC_SELR_SRC_MASK;
1416
1417         refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]) /
1418                  (pllcfg[PLLCFG_M] + 1);
1419
1420         if (refclk < (stm32mp1_pll[type].refclk_min * 1000000) ||
1421             refclk > (stm32mp1_pll[type].refclk_max * 1000000)) {
1422                 debug("invalid refclk = %x\n", (u32)refclk);
1423                 return -EINVAL;
1424         }
1425         if (type == PLL_800 && refclk >= 8000000)
1426                 ifrge = 1;
1427
1428         value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT)
1429                  & RCC_PLLNCFGR1_DIVN_MASK;
1430         value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT)
1431                  & RCC_PLLNCFGR1_DIVM_MASK;
1432         value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT)
1433                  & RCC_PLLNCFGR1_IFRGE_MASK;
1434         writel(value, rcc + pll[pll_id].pllxcfgr1);
1435
1436         /* fractional configuration: load sigma-delta modulator (SDM) */
1437
1438         /* Write into FRACV the new fractional value , and FRACLE to 0 */
1439         writel(fracv << RCC_PLLNFRACR_FRACV_SHIFT,
1440                rcc + pll[pll_id].pllxfracr);
1441
1442         /* Write FRACLE to 1 : FRACV value is loaded into the SDM */
1443         setbits_le32(rcc + pll[pll_id].pllxfracr,
1444                      RCC_PLLNFRACR_FRACLE);
1445
1446         pll_config_output(priv, pll_id, pllcfg);
1447
1448         return 0;
1449 }
1450
1451 static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg)
1452 {
1453         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1454         u32 pllxcsg;
1455
1456         pllxcsg = ((csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) &
1457                     RCC_PLLNCSGR_MOD_PER_MASK) |
1458                   ((csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) &
1459                     RCC_PLLNCSGR_INC_STEP_MASK) |
1460                   ((csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) &
1461                     RCC_PLLNCSGR_SSCG_MODE_MASK);
1462
1463         writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr);
1464
1465         setbits_le32(priv->base + pll[pll_id].pllxcr, RCC_PLLNCR_SSCG_CTRL);
1466 }
1467
1468 static  __maybe_unused int pll_set_rate(struct udevice *dev,
1469                                         int pll_id,
1470                                         int div_id,
1471                                         unsigned long clk_rate)
1472 {
1473         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1474         unsigned int pllcfg[PLLCFG_NB];
1475         ofnode plloff;
1476         char name[12];
1477         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1478         enum stm32mp1_plltype type = pll[pll_id].plltype;
1479         int divm, divn, divy;
1480         int ret;
1481         ulong fck_ref;
1482         u32 fracv;
1483         u64 value;
1484
1485         if (div_id > _DIV_NB)
1486                 return -EINVAL;
1487
1488         sprintf(name, "st,pll@%d", pll_id);
1489         plloff = dev_read_subnode(dev, name);
1490         if (!ofnode_valid(plloff))
1491                 return -FDT_ERR_NOTFOUND;
1492
1493         ret = ofnode_read_u32_array(plloff, "cfg",
1494                                     pllcfg, PLLCFG_NB);
1495         if (ret < 0)
1496                 return -FDT_ERR_NOTFOUND;
1497
1498         fck_ref = pll_get_fref_ck(priv, pll_id);
1499
1500         divm = pllcfg[PLLCFG_M];
1501         /* select output divider = 0: for _DIV_P, 1:_DIV_Q 2:_DIV_R */
1502         divy = pllcfg[PLLCFG_P + div_id];
1503
1504         /* For: PLL1 & PLL2 => VCO is * 2 but ck_pll_y is also / 2
1505          * So same final result than PLL2 et 4
1506          * with FRACV
1507          * Fck_pll_y = Fck_ref * ((DIVN + 1) + FRACV / 2^13)
1508          *             / (DIVy + 1) * (DIVM + 1)
1509          * value = (DIVN + 1) * 2^13 + FRACV / 2^13
1510          *       = Fck_pll_y (DIVy + 1) * (DIVM + 1) * 2^13 / Fck_ref
1511          */
1512         value = ((u64)clk_rate * (divy + 1) * (divm + 1)) << 13;
1513         value = lldiv(value, fck_ref);
1514
1515         divn = (value >> 13) - 1;
1516         if (divn < DIVN_MIN ||
1517             divn > stm32mp1_pll[type].divn_max) {
1518                 pr_err("divn invalid = %d", divn);
1519                 return -EINVAL;
1520         }
1521         fracv = value - ((divn + 1) << 13);
1522         pllcfg[PLLCFG_N] = divn;
1523
1524         /* reconfigure PLL */
1525         pll_stop(priv, pll_id);
1526         pll_config(priv, pll_id, pllcfg, fracv);
1527         pll_start(priv, pll_id);
1528         pll_output(priv, pll_id, pllcfg[PLLCFG_O]);
1529
1530         return 0;
1531 }
1532
1533 static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc)
1534 {
1535         u32 address = priv->base + (clksrc >> 4);
1536         u32 val;
1537         int ret;
1538
1539         clrsetbits_le32(address, RCC_SELR_SRC_MASK, clksrc & RCC_SELR_SRC_MASK);
1540         ret = readl_poll_timeout(address, val, val & RCC_SELR_SRCRDY,
1541                                  TIMEOUT_200MS);
1542         if (ret)
1543                 pr_err("CLKSRC %x start failed @ 0x%x: 0x%x\n",
1544                        clksrc, address, readl(address));
1545
1546         return ret;
1547 }
1548
1549 static void stgen_config(struct stm32mp1_clk_priv *priv)
1550 {
1551         int p;
1552         u32 stgenc, cntfid0;
1553         ulong rate;
1554
1555         stgenc = STM32_STGEN_BASE;
1556         cntfid0 = readl(stgenc + STGENC_CNTFID0);
1557         p = stm32mp1_clk_get_parent(priv, STGEN_K);
1558         rate = stm32mp1_clk_get(priv, p);
1559
1560         if (cntfid0 != rate) {
1561                 u64 counter;
1562
1563                 pr_debug("System Generic Counter (STGEN) update\n");
1564                 clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1565                 counter = (u64)readl(stgenc + STGENC_CNTCVL);
1566                 counter |= ((u64)(readl(stgenc + STGENC_CNTCVU))) << 32;
1567                 counter = lldiv(counter * (u64)rate, cntfid0);
1568                 writel((u32)counter, stgenc + STGENC_CNTCVL);
1569                 writel((u32)(counter >> 32), stgenc + STGENC_CNTCVU);
1570                 writel(rate, stgenc + STGENC_CNTFID0);
1571                 setbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1572
1573                 __asm__ volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (rate));
1574
1575                 /* need to update gd->arch.timer_rate_hz with new frequency */
1576                 timer_init();
1577                 pr_debug("gd->arch.timer_rate_hz = %x\n",
1578                          (u32)gd->arch.timer_rate_hz);
1579                 pr_debug("Tick = %x\n", (u32)(get_ticks()));
1580         }
1581 }
1582
1583 static int set_clkdiv(unsigned int clkdiv, u32 address)
1584 {
1585         u32 val;
1586         int ret;
1587
1588         clrsetbits_le32(address, RCC_DIVR_DIV_MASK, clkdiv & RCC_DIVR_DIV_MASK);
1589         ret = readl_poll_timeout(address, val, val & RCC_DIVR_DIVRDY,
1590                                  TIMEOUT_200MS);
1591         if (ret)
1592                 pr_err("CLKDIV %x start failed @ 0x%x: 0x%x\n",
1593                        clkdiv, address, readl(address));
1594
1595         return ret;
1596 }
1597
1598 static void stm32mp1_mco_csg(struct stm32mp1_clk_priv *priv,
1599                              u32 clksrc, u32 clkdiv)
1600 {
1601         u32 address = priv->base + (clksrc >> 4);
1602
1603         /*
1604          * binding clksrc : bit15-4 offset
1605          *                  bit3:   disable
1606          *                  bit2-0: MCOSEL[2:0]
1607          */
1608         if (clksrc & 0x8) {
1609                 clrbits_le32(address, RCC_MCOCFG_MCOON);
1610         } else {
1611                 clrsetbits_le32(address,
1612                                 RCC_MCOCFG_MCOSRC_MASK,
1613                                 clksrc & RCC_MCOCFG_MCOSRC_MASK);
1614                 clrsetbits_le32(address,
1615                                 RCC_MCOCFG_MCODIV_MASK,
1616                                 clkdiv << RCC_MCOCFG_MCODIV_SHIFT);
1617                 setbits_le32(address, RCC_MCOCFG_MCOON);
1618         }
1619 }
1620
1621 static void set_rtcsrc(struct stm32mp1_clk_priv *priv,
1622                        unsigned int clksrc,
1623                        int lse_css)
1624 {
1625         u32 address = priv->base + RCC_BDCR;
1626
1627         if (readl(address) & RCC_BDCR_RTCCKEN)
1628                 goto skip_rtc;
1629
1630         if (clksrc == CLK_RTC_DISABLED)
1631                 goto skip_rtc;
1632
1633         clrsetbits_le32(address,
1634                         RCC_BDCR_RTCSRC_MASK,
1635                         clksrc << RCC_BDCR_RTCSRC_SHIFT);
1636
1637         setbits_le32(address, RCC_BDCR_RTCCKEN);
1638
1639 skip_rtc:
1640         if (lse_css)
1641                 setbits_le32(address, RCC_BDCR_LSECSSON);
1642 }
1643
1644 static void pkcs_config(struct stm32mp1_clk_priv *priv, u32 pkcs)
1645 {
1646         u32 address = priv->base + ((pkcs >> 4) & 0xFFF);
1647         u32 value = pkcs & 0xF;
1648         u32 mask = 0xF;
1649
1650         if (pkcs & BIT(31)) {
1651                 mask <<= 4;
1652                 value <<= 4;
1653         }
1654         clrsetbits_le32(address, mask, value);
1655 }
1656
1657 static int stm32mp1_clktree(struct udevice *dev)
1658 {
1659         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1660         fdt_addr_t rcc = priv->base;
1661         unsigned int clksrc[CLKSRC_NB];
1662         unsigned int clkdiv[CLKDIV_NB];
1663         unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
1664         ofnode plloff[_PLL_NB];
1665         int ret;
1666         int i, len;
1667         int lse_css = 0;
1668         const u32 *pkcs_cell;
1669
1670         /* check mandatory field */
1671         ret = dev_read_u32_array(dev, "st,clksrc", clksrc, CLKSRC_NB);
1672         if (ret < 0) {
1673                 debug("field st,clksrc invalid: error %d\n", ret);
1674                 return -FDT_ERR_NOTFOUND;
1675         }
1676
1677         ret = dev_read_u32_array(dev, "st,clkdiv", clkdiv, CLKDIV_NB);
1678         if (ret < 0) {
1679                 debug("field st,clkdiv invalid: error %d\n", ret);
1680                 return -FDT_ERR_NOTFOUND;
1681         }
1682
1683         /* check mandatory field in each pll */
1684         for (i = 0; i < _PLL_NB; i++) {
1685                 char name[12];
1686
1687                 sprintf(name, "st,pll@%d", i);
1688                 plloff[i] = dev_read_subnode(dev, name);
1689                 if (!ofnode_valid(plloff[i]))
1690                         continue;
1691                 ret = ofnode_read_u32_array(plloff[i], "cfg",
1692                                             pllcfg[i], PLLCFG_NB);
1693                 if (ret < 0) {
1694                         debug("field cfg invalid: error %d\n", ret);
1695                         return -FDT_ERR_NOTFOUND;
1696                 }
1697         }
1698
1699         debug("configuration MCO\n");
1700         stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]);
1701         stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]);
1702
1703         debug("switch ON osillator\n");
1704         /*
1705          * switch ON oscillator found in device-tree,
1706          * HSI already ON after bootrom
1707          */
1708         if (priv->osc[_LSI])
1709                 stm32mp1_lsi_set(rcc, 1);
1710
1711         if (priv->osc[_LSE]) {
1712                 int bypass, digbyp, lsedrv;
1713                 struct udevice *dev = priv->osc_dev[_LSE];
1714
1715                 bypass = dev_read_bool(dev, "st,bypass");
1716                 digbyp = dev_read_bool(dev, "st,digbypass");
1717                 lse_css = dev_read_bool(dev, "st,css");
1718                 lsedrv = dev_read_u32_default(dev, "st,drive",
1719                                               LSEDRV_MEDIUM_HIGH);
1720
1721                 stm32mp1_lse_enable(rcc, bypass, digbyp, lsedrv);
1722         }
1723
1724         if (priv->osc[_HSE]) {
1725                 int bypass, digbyp, css;
1726                 struct udevice *dev = priv->osc_dev[_HSE];
1727
1728                 bypass = dev_read_bool(dev, "st,bypass");
1729                 digbyp = dev_read_bool(dev, "st,digbypass");
1730                 css = dev_read_bool(dev, "st,css");
1731
1732                 stm32mp1_hse_enable(rcc, bypass, digbyp, css);
1733         }
1734         /* CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR)
1735          * => switch on CSI even if node is not present in device tree
1736          */
1737         stm32mp1_csi_set(rcc, 1);
1738
1739         /* come back to HSI */
1740         debug("come back to HSI\n");
1741         set_clksrc(priv, CLK_MPU_HSI);
1742         set_clksrc(priv, CLK_AXI_HSI);
1743         set_clksrc(priv, CLK_MCU_HSI);
1744
1745         debug("pll stop\n");
1746         for (i = 0; i < _PLL_NB; i++)
1747                 pll_stop(priv, i);
1748
1749         /* configure HSIDIV */
1750         debug("configure HSIDIV\n");
1751         if (priv->osc[_HSI]) {
1752                 stm32mp1_hsidiv(rcc, priv->osc[_HSI]);
1753                 stgen_config(priv);
1754         }
1755
1756         /* select DIV */
1757         debug("select DIV\n");
1758         /* no ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */
1759         writel(clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK, rcc + RCC_MPCKDIVR);
1760         set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR);
1761         set_clkdiv(clkdiv[CLKDIV_APB4], rcc + RCC_APB4DIVR);
1762         set_clkdiv(clkdiv[CLKDIV_APB5], rcc + RCC_APB5DIVR);
1763         set_clkdiv(clkdiv[CLKDIV_MCU], rcc + RCC_MCUDIVR);
1764         set_clkdiv(clkdiv[CLKDIV_APB1], rcc + RCC_APB1DIVR);
1765         set_clkdiv(clkdiv[CLKDIV_APB2], rcc + RCC_APB2DIVR);
1766         set_clkdiv(clkdiv[CLKDIV_APB3], rcc + RCC_APB3DIVR);
1767
1768         /* no ready bit for RTC */
1769         writel(clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK, rcc + RCC_RTCDIVR);
1770
1771         /* configure PLLs source */
1772         debug("configure PLLs source\n");
1773         set_clksrc(priv, clksrc[CLKSRC_PLL12]);
1774         set_clksrc(priv, clksrc[CLKSRC_PLL3]);
1775         set_clksrc(priv, clksrc[CLKSRC_PLL4]);
1776
1777         /* configure and start PLLs */
1778         debug("configure PLLs\n");
1779         for (i = 0; i < _PLL_NB; i++) {
1780                 u32 fracv;
1781                 u32 csg[PLLCSG_NB];
1782
1783                 debug("configure PLL %d @ %d\n", i,
1784                       ofnode_to_offset(plloff[i]));
1785                 if (!ofnode_valid(plloff[i]))
1786                         continue;
1787
1788                 fracv = ofnode_read_u32_default(plloff[i], "frac", 0);
1789                 pll_config(priv, i, pllcfg[i], fracv);
1790                 ret = ofnode_read_u32_array(plloff[i], "csg", csg, PLLCSG_NB);
1791                 if (!ret) {
1792                         pll_csg(priv, i, csg);
1793                 } else if (ret != -FDT_ERR_NOTFOUND) {
1794                         debug("invalid csg node for pll@%d res=%d\n", i, ret);
1795                         return ret;
1796                 }
1797                 pll_start(priv, i);
1798         }
1799
1800         /* wait and start PLLs ouptut when ready */
1801         for (i = 0; i < _PLL_NB; i++) {
1802                 if (!ofnode_valid(plloff[i]))
1803                         continue;
1804                 debug("output PLL %d\n", i);
1805                 pll_output(priv, i, pllcfg[i][PLLCFG_O]);
1806         }
1807
1808         /* wait LSE ready before to use it */
1809         if (priv->osc[_LSE])
1810                 stm32mp1_lse_wait(rcc);
1811
1812         /* configure with expected clock source */
1813         debug("CLKSRC\n");
1814         set_clksrc(priv, clksrc[CLKSRC_MPU]);
1815         set_clksrc(priv, clksrc[CLKSRC_AXI]);
1816         set_clksrc(priv, clksrc[CLKSRC_MCU]);
1817         set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css);
1818
1819         /* configure PKCK */
1820         debug("PKCK\n");
1821         pkcs_cell = dev_read_prop(dev, "st,pkcs", &len);
1822         if (pkcs_cell) {
1823                 bool ckper_disabled = false;
1824
1825                 for (i = 0; i < len / sizeof(u32); i++) {
1826                         u32 pkcs = (u32)fdt32_to_cpu(pkcs_cell[i]);
1827
1828                         if (pkcs == CLK_CKPER_DISABLED) {
1829                                 ckper_disabled = true;
1830                                 continue;
1831                         }
1832                         pkcs_config(priv, pkcs);
1833                 }
1834                 /* CKPER is source for some peripheral clock
1835                  * (FMC-NAND / QPSI-NOR) and switching source is allowed
1836                  * only if previous clock is still ON
1837                  * => deactivated CKPER only after switching clock
1838                  */
1839                 if (ckper_disabled)
1840                         pkcs_config(priv, CLK_CKPER_DISABLED);
1841         }
1842
1843         /* STGEN clock source can change with CLK_STGEN_XXX */
1844         stgen_config(priv);
1845
1846         debug("oscillator off\n");
1847         /* switch OFF HSI if not found in device-tree */
1848         if (!priv->osc[_HSI])
1849                 stm32mp1_hsi_set(rcc, 0);
1850
1851         /* Software Self-Refresh mode (SSR) during DDR initilialization */
1852         clrsetbits_le32(priv->base + RCC_DDRITFCR,
1853                         RCC_DDRITFCR_DDRCKMOD_MASK,
1854                         RCC_DDRITFCR_DDRCKMOD_SSR <<
1855                         RCC_DDRITFCR_DDRCKMOD_SHIFT);
1856
1857         return 0;
1858 }
1859 #endif /* STM32MP1_CLOCK_TREE_INIT */
1860
1861 static int pll_set_output_rate(struct udevice *dev,
1862                                int pll_id,
1863                                int div_id,
1864                                unsigned long clk_rate)
1865 {
1866         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1867         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1868         u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1869         int div;
1870         ulong fvco;
1871
1872         if (div_id > _DIV_NB)
1873                 return -EINVAL;
1874
1875         fvco = pll_get_fvco(priv, pll_id);
1876
1877         if (fvco <= clk_rate)
1878                 div = 1;
1879         else
1880                 div = DIV_ROUND_UP(fvco, clk_rate);
1881
1882         if (div > 128)
1883                 div = 128;
1884
1885         debug("fvco = %ld, clk_rate = %ld, div=%d\n", fvco, clk_rate, div);
1886         /* stop the requested output */
1887         clrbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
1888         /* change divider */
1889         clrsetbits_le32(priv->base + pll[pll_id].pllxcfgr2,
1890                         RCC_PLLNCFGR2_DIVX_MASK << RCC_PLLNCFGR2_SHIFT(div_id),
1891                         (div - 1) << RCC_PLLNCFGR2_SHIFT(div_id));
1892         /* start the requested output */
1893         setbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
1894
1895         return 0;
1896 }
1897
1898 static ulong stm32mp1_clk_set_rate(struct clk *clk, unsigned long clk_rate)
1899 {
1900         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1901         int p;
1902
1903         switch (clk->id) {
1904 #if defined(STM32MP1_CLOCK_TREE_INIT) && \
1905         defined(CONFIG_STM32MP1_DDR_INTERACTIVE)
1906         case DDRPHYC:
1907                 break;
1908 #endif
1909         case LTDC_PX:
1910         case DSI_PX:
1911                 break;
1912         default:
1913                 pr_err("not supported");
1914                 return -EINVAL;
1915         }
1916
1917         p = stm32mp1_clk_get_parent(priv, clk->id);
1918         if (p < 0)
1919                 return -EINVAL;
1920
1921         switch (p) {
1922 #if defined(STM32MP1_CLOCK_TREE_INIT) && \
1923         defined(CONFIG_STM32MP1_DDR_INTERACTIVE)
1924         case _PLL2_R: /* DDRPHYC */
1925         {
1926                 /* only for change DDR clock in interactive mode */
1927                 ulong result;
1928
1929                 set_clksrc(priv, CLK_AXI_HSI);
1930                 result = pll_set_rate(clk->dev,  _PLL2, _DIV_R, clk_rate);
1931                 set_clksrc(priv, CLK_AXI_PLL2P);
1932                 return result;
1933         }
1934 #endif
1935         case _PLL4_Q:
1936                 /* for LTDC_PX and DSI_PX case */
1937                 return pll_set_output_rate(clk->dev, _PLL4, _DIV_Q, clk_rate);
1938         }
1939
1940         return -EINVAL;
1941 }
1942
1943 static void stm32mp1_osc_clk_init(const char *name,
1944                                   struct stm32mp1_clk_priv *priv,
1945                                   int index)
1946 {
1947         struct clk clk;
1948         struct udevice *dev = NULL;
1949
1950         priv->osc[index] = 0;
1951         clk.id = 0;
1952         if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) {
1953                 if (clk_request(dev, &clk))
1954                         pr_err("%s request", name);
1955                 else
1956                         priv->osc[index] = clk_get_rate(&clk);
1957         }
1958         priv->osc_dev[index] = dev;
1959 }
1960
1961 static void stm32mp1_osc_init(struct udevice *dev)
1962 {
1963         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1964         int i;
1965         const char *name[NB_OSC] = {
1966                 [_LSI] = "clk-lsi",
1967                 [_LSE] = "clk-lse",
1968                 [_HSI] = "clk-hsi",
1969                 [_HSE] = "clk-hse",
1970                 [_CSI] = "clk-csi",
1971                 [_I2S_CKIN] = "i2s_ckin",
1972         };
1973
1974         for (i = 0; i < NB_OSC; i++) {
1975                 stm32mp1_osc_clk_init(name[i], priv, i);
1976                 debug("%d: %s => %x\n", i, name[i], (u32)priv->osc[i]);
1977         }
1978 }
1979
1980 static void  __maybe_unused stm32mp1_clk_dump(struct stm32mp1_clk_priv *priv)
1981 {
1982         char buf[32];
1983         int i, s, p;
1984
1985         printf("Clocks:\n");
1986         for (i = 0; i < _PARENT_NB; i++) {
1987                 printf("- %s : %s MHz\n",
1988                        stm32mp1_clk_parent_name[i],
1989                        strmhz(buf, stm32mp1_clk_get(priv, i)));
1990         }
1991         printf("Source Clocks:\n");
1992         for (i = 0; i < _PARENT_SEL_NB; i++) {
1993                 p = (readl(priv->base + priv->data->sel[i].offset) >>
1994                      priv->data->sel[i].src) & priv->data->sel[i].msk;
1995                 if (p < priv->data->sel[i].nb_parent) {
1996                         s = priv->data->sel[i].parent[p];
1997                         printf("- %s(%d) => parent %s(%d)\n",
1998                                stm32mp1_clk_parent_sel_name[i], i,
1999                                stm32mp1_clk_parent_name[s], s);
2000                 } else {
2001                         printf("- %s(%d) => parent index %d is invalid\n",
2002                                stm32mp1_clk_parent_sel_name[i], i, p);
2003                 }
2004         }
2005 }
2006
2007 #ifdef CONFIG_CMD_CLK
2008 int soc_clk_dump(void)
2009 {
2010         struct udevice *dev;
2011         struct stm32mp1_clk_priv *priv;
2012         int ret;
2013
2014         ret = uclass_get_device_by_driver(UCLASS_CLK,
2015                                           DM_GET_DRIVER(stm32mp1_clock),
2016                                           &dev);
2017         if (ret)
2018                 return ret;
2019
2020         priv = dev_get_priv(dev);
2021
2022         stm32mp1_clk_dump(priv);
2023
2024         return 0;
2025 }
2026 #endif
2027
2028 static int stm32mp1_clk_probe(struct udevice *dev)
2029 {
2030         int result = 0;
2031         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
2032
2033         priv->base = dev_read_addr(dev->parent);
2034         if (priv->base == FDT_ADDR_T_NONE)
2035                 return -EINVAL;
2036
2037         priv->data = (void *)&stm32mp1_data;
2038
2039         if (!priv->data->gate || !priv->data->sel ||
2040             !priv->data->pll)
2041                 return -EINVAL;
2042
2043         stm32mp1_osc_init(dev);
2044
2045 #ifdef STM32MP1_CLOCK_TREE_INIT
2046         /* clock tree init is done only one time, before relocation */
2047         if (!(gd->flags & GD_FLG_RELOC))
2048                 result = stm32mp1_clktree(dev);
2049 #endif
2050
2051 #ifndef CONFIG_SPL_BUILD
2052 #if defined(DEBUG)
2053         /* display debug information for probe after relocation */
2054         if (gd->flags & GD_FLG_RELOC)
2055                 stm32mp1_clk_dump(priv);
2056 #endif
2057
2058 #if defined(CONFIG_DISPLAY_CPUINFO)
2059         if (gd->flags & GD_FLG_RELOC) {
2060                 char buf[32];
2061
2062                 printf("Clocks:\n");
2063                 printf("- MPU : %s MHz\n",
2064                        strmhz(buf, stm32mp1_clk_get(priv, _CK_MPU)));
2065                 printf("- MCU : %s MHz\n",
2066                        strmhz(buf, stm32mp1_clk_get(priv, _CK_MCU)));
2067                 printf("- AXI : %s MHz\n",
2068                        strmhz(buf, stm32mp1_clk_get(priv, _ACLK)));
2069                 printf("- PER : %s MHz\n",
2070                        strmhz(buf, stm32mp1_clk_get(priv, _CK_PER)));
2071                 /* DDRPHYC father */
2072                 printf("- DDR : %s MHz\n",
2073                        strmhz(buf, stm32mp1_clk_get(priv, _PLL2_R)));
2074         }
2075 #endif /* CONFIG_DISPLAY_CPUINFO */
2076 #endif
2077
2078         return result;
2079 }
2080
2081 static const struct clk_ops stm32mp1_clk_ops = {
2082         .enable = stm32mp1_clk_enable,
2083         .disable = stm32mp1_clk_disable,
2084         .get_rate = stm32mp1_clk_get_rate,
2085         .set_rate = stm32mp1_clk_set_rate,
2086 };
2087
2088 U_BOOT_DRIVER(stm32mp1_clock) = {
2089         .name = "stm32mp1_clk",
2090         .id = UCLASS_CLK,
2091         .ops = &stm32mp1_clk_ops,
2092         .priv_auto_alloc_size = sizeof(struct stm32mp1_clk_priv),
2093         .probe = stm32mp1_clk_probe,
2094 };