drivers/clk/clk_stm32mp1.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   4  */
   5
   6 #include <common.h>
   7 #include <clk-uclass.h>
   8 #include <div64.h>
   9 #include <dm.h>
  10 #include <regmap.h>
  11 #include <spl.h>
  12 #include <syscon.h>
  13 #include <linux/io.h>
  14 #include <linux/iopoll.h>
  15 #include <dt-bindings/clock/stm32mp1-clks.h>
  16 #include <dt-bindings/clock/stm32mp1-clksrc.h>
  17
  18 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
  19 /* activate clock tree initialization in the driver */
  20 #define STM32MP1_CLOCK_TREE_INIT
  21 #endif
  22
  23 #define MAX_HSI_HZ              64000000
  24
  25 /* TIMEOUT */
  26 #define TIMEOUT_200MS           200000
  27 #define TIMEOUT_1S              1000000
  28
  29 /* STGEN registers */
  30 #define STGENC_CNTCR            0x00
  31 #define STGENC_CNTSR            0x04
  32 #define STGENC_CNTCVL           0x08
  33 #define STGENC_CNTCVU           0x0C
  34 #define STGENC_CNTFID0          0x20
  35
  36 #define STGENC_CNTCR_EN         BIT(0)
  37
  38 /* RCC registers */
  39 #define RCC_OCENSETR            0x0C
  40 #define RCC_OCENCLRR            0x10
  41 #define RCC_HSICFGR             0x18
  42 #define RCC_MPCKSELR            0x20
  43 #define RCC_ASSCKSELR           0x24
  44 #define RCC_RCK12SELR           0x28
  45 #define RCC_MPCKDIVR            0x2C
  46 #define RCC_AXIDIVR             0x30
  47 #define RCC_APB4DIVR            0x3C
  48 #define RCC_APB5DIVR            0x40
  49 #define RCC_RTCDIVR             0x44
  50 #define RCC_MSSCKSELR           0x48
  51 #define RCC_PLL1CR              0x80
  52 #define RCC_PLL1CFGR1           0x84
  53 #define RCC_PLL1CFGR2           0x88
  54 #define RCC_PLL1FRACR           0x8C
  55 #define RCC_PLL1CSGR            0x90
  56 #define RCC_PLL2CR              0x94
  57 #define RCC_PLL2CFGR1           0x98
  58 #define RCC_PLL2CFGR2           0x9C
  59 #define RCC_PLL2FRACR           0xA0
  60 #define RCC_PLL2CSGR            0xA4
  61 #define RCC_I2C46CKSELR         0xC0
  62 #define RCC_CPERCKSELR          0xD0
  63 #define RCC_STGENCKSELR         0xD4
  64 #define RCC_DDRITFCR            0xD8
  65 #define RCC_BDCR                0x140
  66 #define RCC_RDLSICR             0x144
  67 #define RCC_MP_APB4ENSETR       0x200
  68 #define RCC_MP_APB5ENSETR       0x208
  69 #define RCC_MP_AHB5ENSETR       0x210
  70 #define RCC_MP_AHB6ENSETR       0x218
  71 #define RCC_OCRDYR              0x808
  72 #define RCC_DBGCFGR             0x80C
  73 #define RCC_RCK3SELR            0x820
  74 #define RCC_RCK4SELR            0x824
  75 #define RCC_MCUDIVR             0x830
  76 #define RCC_APB1DIVR            0x834
  77 #define RCC_APB2DIVR            0x838
  78 #define RCC_APB3DIVR            0x83C
  79 #define RCC_PLL3CR              0x880
  80 #define RCC_PLL3CFGR1           0x884
  81 #define RCC_PLL3CFGR2           0x888
  82 #define RCC_PLL3FRACR           0x88C
  83 #define RCC_PLL3CSGR            0x890
  84 #define RCC_PLL4CR              0x894
  85 #define RCC_PLL4CFGR1           0x898
  86 #define RCC_PLL4CFGR2           0x89C
  87 #define RCC_PLL4FRACR           0x8A0
  88 #define RCC_PLL4CSGR            0x8A4
  89 #define RCC_I2C12CKSELR         0x8C0
  90 #define RCC_I2C35CKSELR         0x8C4
  91 #define RCC_UART6CKSELR         0x8E4
  92 #define RCC_UART24CKSELR        0x8E8
  93 #define RCC_UART35CKSELR        0x8EC
  94 #define RCC_UART78CKSELR        0x8F0
  95 #define RCC_SDMMC12CKSELR       0x8F4
  96 #define RCC_SDMMC3CKSELR        0x8F8
  97 #define RCC_ETHCKSELR           0x8FC
  98 #define RCC_QSPICKSELR          0x900
  99 #define RCC_FMCCKSELR           0x904
 100 #define RCC_USBCKSELR           0x91C
 101 #define RCC_DSICKSELR           0x924
 102 #define RCC_ADCCKSELR           0x928
 103 #define RCC_MP_APB1ENSETR       0xA00
 104 #define RCC_MP_APB2ENSETR       0XA08
 105 #define RCC_MP_APB3ENSETR       0xA10
 106 #define RCC_MP_AHB2ENSETR       0xA18
 107 #define RCC_MP_AHB3ENSETR       0xA20
 108 #define RCC_MP_AHB4ENSETR       0xA28
 109
 110 /* used for most of SELR register */
 111 #define RCC_SELR_SRC_MASK       GENMASK(2, 0)
 112 #define RCC_SELR_SRCRDY         BIT(31)
 113
 114 /* Values of RCC_MPCKSELR register */
 115 #define RCC_MPCKSELR_HSI        0
 116 #define RCC_MPCKSELR_HSE        1
 117 #define RCC_MPCKSELR_PLL        2
 118 #define RCC_MPCKSELR_PLL_MPUDIV 3
 119
 120 /* Values of RCC_ASSCKSELR register */
 121 #define RCC_ASSCKSELR_HSI       0
 122 #define RCC_ASSCKSELR_HSE       1
 123 #define RCC_ASSCKSELR_PLL       2
 124
 125 /* Values of RCC_MSSCKSELR register */
 126 #define RCC_MSSCKSELR_HSI       0
 127 #define RCC_MSSCKSELR_HSE       1
 128 #define RCC_MSSCKSELR_CSI       2
 129 #define RCC_MSSCKSELR_PLL       3
 130
 131 /* Values of RCC_CPERCKSELR register */
 132 #define RCC_CPERCKSELR_HSI      0
 133 #define RCC_CPERCKSELR_CSI      1
 134 #define RCC_CPERCKSELR_HSE      2
 135
 136 /* used for most of DIVR register : max div for RTC */
 137 #define RCC_DIVR_DIV_MASK       GENMASK(5, 0)
 138 #define RCC_DIVR_DIVRDY         BIT(31)
 139
 140 /* Masks for specific DIVR registers */
 141 #define RCC_APBXDIV_MASK        GENMASK(2, 0)
 142 #define RCC_MPUDIV_MASK         GENMASK(2, 0)
 143 #define RCC_AXIDIV_MASK         GENMASK(2, 0)
 144 #define RCC_MCUDIV_MASK         GENMASK(3, 0)
 145
 146 /*  offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
 147 #define RCC_MP_ENCLRR_OFFSET    4
 148
 149 /* Fields of RCC_BDCR register */
 150 #define RCC_BDCR_LSEON          BIT(0)
 151 #define RCC_BDCR_LSEBYP         BIT(1)
 152 #define RCC_BDCR_LSERDY         BIT(2)
 153 #define RCC_BDCR_DIGBYP         BIT(3)
 154 #define RCC_BDCR_LSEDRV_MASK    GENMASK(5, 4)
 155 #define RCC_BDCR_LSEDRV_SHIFT   4
 156 #define RCC_BDCR_LSECSSON       BIT(8)
 157 #define RCC_BDCR_RTCCKEN        BIT(20)
 158 #define RCC_BDCR_RTCSRC_MASK    GENMASK(17, 16)
 159 #define RCC_BDCR_RTCSRC_SHIFT   16
 160
 161 /* Fields of RCC_RDLSICR register */
 162 #define RCC_RDLSICR_LSION       BIT(0)
 163 #define RCC_RDLSICR_LSIRDY      BIT(1)
 164
 165 /* used for ALL PLLNCR registers */
 166 #define RCC_PLLNCR_PLLON        BIT(0)
 167 #define RCC_PLLNCR_PLLRDY       BIT(1)
 168 #define RCC_PLLNCR_DIVPEN       BIT(4)
 169 #define RCC_PLLNCR_DIVQEN       BIT(5)
 170 #define RCC_PLLNCR_DIVREN       BIT(6)
 171 #define RCC_PLLNCR_DIVEN_SHIFT  4
 172
 173 /* used for ALL PLLNCFGR1 registers */
 174 #define RCC_PLLNCFGR1_DIVM_SHIFT        16
 175 #define RCC_PLLNCFGR1_DIVM_MASK         GENMASK(21, 16)
 176 #define RCC_PLLNCFGR1_DIVN_SHIFT        0
 177 #define RCC_PLLNCFGR1_DIVN_MASK         GENMASK(8, 0)
 178 /* only for PLL3 and PLL4 */
 179 #define RCC_PLLNCFGR1_IFRGE_SHIFT       24
 180 #define RCC_PLLNCFGR1_IFRGE_MASK        GENMASK(25, 24)
 181
 182 /* used for ALL PLLNCFGR2 registers , using stm32mp1_div_id */
 183 #define RCC_PLLNCFGR2_SHIFT(div_id)     ((div_id) * 8)
 184 #define RCC_PLLNCFGR2_DIVX_MASK         GENMASK(6, 0)
 185 #define RCC_PLLNCFGR2_DIVP_SHIFT        RCC_PLLNCFGR2_SHIFT(_DIV_P)
 186 #define RCC_PLLNCFGR2_DIVP_MASK         GENMASK(6, 0)
 187 #define RCC_PLLNCFGR2_DIVQ_SHIFT        RCC_PLLNCFGR2_SHIFT(_DIV_Q)
 188 #define RCC_PLLNCFGR2_DIVQ_MASK         GENMASK(14, 8)
 189 #define RCC_PLLNCFGR2_DIVR_SHIFT        RCC_PLLNCFGR2_SHIFT(_DIV_R)
 190 #define RCC_PLLNCFGR2_DIVR_MASK         GENMASK(22, 16)
 191
 192 /* used for ALL PLLNFRACR registers */
 193 #define RCC_PLLNFRACR_FRACV_SHIFT       3
 194 #define RCC_PLLNFRACR_FRACV_MASK        GENMASK(15, 3)
 195 #define RCC_PLLNFRACR_FRACLE            BIT(16)
 196
 197 /* used for ALL PLLNCSGR registers */
 198 #define RCC_PLLNCSGR_INC_STEP_SHIFT     16
 199 #define RCC_PLLNCSGR_INC_STEP_MASK      GENMASK(30, 16)
 200 #define RCC_PLLNCSGR_MOD_PER_SHIFT      0
 201 #define RCC_PLLNCSGR_MOD_PER_MASK       GENMASK(12, 0)
 202 #define RCC_PLLNCSGR_SSCG_MODE_SHIFT    15
 203 #define RCC_PLLNCSGR_SSCG_MODE_MASK     BIT(15)
 204
 205 /* used for RCC_OCENSETR and RCC_OCENCLRR registers */
 206 #define RCC_OCENR_HSION                 BIT(0)
 207 #define RCC_OCENR_CSION                 BIT(4)
 208 #define RCC_OCENR_DIGBYP                BIT(7)
 209 #define RCC_OCENR_HSEON                 BIT(8)
 210 #define RCC_OCENR_HSEBYP                BIT(10)
 211 #define RCC_OCENR_HSECSSON              BIT(11)
 212
 213 /* Fields of RCC_OCRDYR register */
 214 #define RCC_OCRDYR_HSIRDY               BIT(0)
 215 #define RCC_OCRDYR_HSIDIVRDY            BIT(2)
 216 #define RCC_OCRDYR_CSIRDY               BIT(4)
 217 #define RCC_OCRDYR_HSERDY               BIT(8)
 218
 219 /* Fields of DDRITFCR register */
 220 #define RCC_DDRITFCR_DDRCKMOD_MASK      GENMASK(22, 20)
 221 #define RCC_DDRITFCR_DDRCKMOD_SHIFT     20
 222 #define RCC_DDRITFCR_DDRCKMOD_SSR       0
 223
 224 /* Fields of RCC_HSICFGR register */
 225 #define RCC_HSICFGR_HSIDIV_MASK         GENMASK(1, 0)
 226
 227 /* used for MCO related operations */
 228 #define RCC_MCOCFG_MCOON                BIT(12)
 229 #define RCC_MCOCFG_MCODIV_MASK          GENMASK(7, 4)
 230 #define RCC_MCOCFG_MCODIV_SHIFT         4
 231 #define RCC_MCOCFG_MCOSRC_MASK          GENMASK(2, 0)
 232
 233 enum stm32mp1_parent_id {
 234 /*
 235  * _HSI, _HSE, _CSI, _LSI, _LSE should not be moved
 236  * they are used as index in osc[] as entry point
 237  */
 238         _HSI,
 239         _HSE,
 240         _CSI,
 241         _LSI,
 242         _LSE,
 243         _I2S_CKIN,
 244         NB_OSC,
 245
 246 /* other parent source */
 247         _HSI_KER = NB_OSC,
 248         _HSE_KER,
 249         _HSE_KER_DIV2,
 250         _CSI_KER,
 251         _PLL1_P,
 252         _PLL1_Q,
 253         _PLL1_R,
 254         _PLL2_P,
 255         _PLL2_Q,
 256         _PLL2_R,
 257         _PLL3_P,
 258         _PLL3_Q,
 259         _PLL3_R,
 260         _PLL4_P,
 261         _PLL4_Q,
 262         _PLL4_R,
 263         _ACLK,
 264         _PCLK1,
 265         _PCLK2,
 266         _PCLK3,
 267         _PCLK4,
 268         _PCLK5,
 269         _HCLK6,
 270         _HCLK2,
 271         _CK_PER,
 272         _CK_MPU,
 273         _CK_MCU,
 274         _DSI_PHY,
 275         _USB_PHY_48,
 276         _PARENT_NB,
 277         _UNKNOWN_ID = 0xff,
 278 };
 279
 280 enum stm32mp1_parent_sel {
 281         _I2C12_SEL,
 282         _I2C35_SEL,
 283         _I2C46_SEL,
 284         _UART6_SEL,
 285         _UART24_SEL,
 286         _UART35_SEL,
 287         _UART78_SEL,
 288         _SDMMC12_SEL,
 289         _SDMMC3_SEL,
 290         _ETH_SEL,
 291         _QSPI_SEL,
 292         _FMC_SEL,
 293         _USBPHY_SEL,
 294         _USBO_SEL,
 295         _STGEN_SEL,
 296         _DSI_SEL,
 297         _ADC12_SEL,
 298         _PARENT_SEL_NB,
 299         _UNKNOWN_SEL = 0xff,
 300 };
 301
 302 enum stm32mp1_pll_id {
 303         _PLL1,
 304         _PLL2,
 305         _PLL3,
 306         _PLL4,
 307         _PLL_NB
 308 };
 309
 310 enum stm32mp1_div_id {
 311         _DIV_P,
 312         _DIV_Q,
 313         _DIV_R,
 314         _DIV_NB,
 315 };
 316
 317 enum stm32mp1_clksrc_id {
 318         CLKSRC_MPU,
 319         CLKSRC_AXI,
 320         CLKSRC_MCU,
 321         CLKSRC_PLL12,
 322         CLKSRC_PLL3,
 323         CLKSRC_PLL4,
 324         CLKSRC_RTC,
 325         CLKSRC_MCO1,
 326         CLKSRC_MCO2,
 327         CLKSRC_NB
 328 };
 329
 330 enum stm32mp1_clkdiv_id {
 331         CLKDIV_MPU,
 332         CLKDIV_AXI,
 333         CLKDIV_MCU,
 334         CLKDIV_APB1,
 335         CLKDIV_APB2,
 336         CLKDIV_APB3,
 337         CLKDIV_APB4,
 338         CLKDIV_APB5,
 339         CLKDIV_RTC,
 340         CLKDIV_MCO1,
 341         CLKDIV_MCO2,
 342         CLKDIV_NB
 343 };
 344
 345 enum stm32mp1_pllcfg {
 346         PLLCFG_M,
 347         PLLCFG_N,
 348         PLLCFG_P,
 349         PLLCFG_Q,
 350         PLLCFG_R,
 351         PLLCFG_O,
 352         PLLCFG_NB
 353 };
 354
 355 enum stm32mp1_pllcsg {
 356         PLLCSG_MOD_PER,
 357         PLLCSG_INC_STEP,
 358         PLLCSG_SSCG_MODE,
 359         PLLCSG_NB
 360 };
 361
 362 enum stm32mp1_plltype {
 363         PLL_800,
 364         PLL_1600,
 365         PLL_TYPE_NB
 366 };
 367
 368 struct stm32mp1_pll {
 369         u8 refclk_min;
 370         u8 refclk_max;
 371         u8 divn_max;
 372 };
 373
 374 struct stm32mp1_clk_gate {
 375         u16 offset;
 376         u8 bit;
 377         u8 index;
 378         u8 set_clr;
 379         u8 sel;
 380         u8 fixed;
 381 };
 382
 383 struct stm32mp1_clk_sel {
 384         u16 offset;
 385         u8 src;
 386         u8 msk;
 387         u8 nb_parent;
 388         const u8 *parent;
 389 };
 390
 391 #define REFCLK_SIZE 4
 392 struct stm32mp1_clk_pll {
 393         enum stm32mp1_plltype plltype;
 394         u16 rckxselr;
 395         u16 pllxcfgr1;
 396         u16 pllxcfgr2;
 397         u16 pllxfracr;
 398         u16 pllxcr;
 399         u16 pllxcsgr;
 400         u8 refclk[REFCLK_SIZE];
 401 };
 402
 403 struct stm32mp1_clk_data {
 404         const struct stm32mp1_clk_gate *gate;
 405         const struct stm32mp1_clk_sel *sel;
 406         const struct stm32mp1_clk_pll *pll;
 407         const int nb_gate;
 408 };
 409
 410 struct stm32mp1_clk_priv {
 411         fdt_addr_t base;
 412         const struct stm32mp1_clk_data *data;
 413         ulong osc[NB_OSC];
 414         struct udevice *osc_dev[NB_OSC];
 415 };
 416
 417 #define STM32MP1_CLK(off, b, idx, s)            \
 418         {                                       \
 419                 .offset = (off),                \
 420                 .bit = (b),                     \
 421                 .index = (idx),                 \
 422                 .set_clr = 0,                   \
 423                 .sel = (s),                     \
 424                 .fixed = _UNKNOWN_ID,           \
 425         }
 426
 427 #define STM32MP1_CLK_F(off, b, idx, f)          \
 428         {                                       \
 429                 .offset = (off),                \
 430                 .bit = (b),                     \
 431                 .index = (idx),                 \
 432                 .set_clr = 0,                   \
 433                 .sel = _UNKNOWN_SEL,            \
 434                 .fixed = (f),                   \
 435         }
 436
 437 #define STM32MP1_CLK_SET_CLR(off, b, idx, s)    \
 438         {                                       \
 439                 .offset = (off),                \
 440                 .bit = (b),                     \
 441                 .index = (idx),                 \
 442                 .set_clr = 1,                   \
 443                 .sel = (s),                     \
 444                 .fixed = _UNKNOWN_ID,           \
 445         }
 446
 447 #define STM32MP1_CLK_SET_CLR_F(off, b, idx, f)  \
 448         {                                       \
 449                 .offset = (off),                \
 450                 .bit = (b),                     \
 451                 .index = (idx),                 \
 452                 .set_clr = 1,                   \
 453                 .sel = _UNKNOWN_SEL,            \
 454                 .fixed = (f),                   \
 455         }
 456
 457 #define STM32MP1_CLK_PARENT(idx, off, s, m, p)   \
 458         [(idx)] = {                             \
 459                 .offset = (off),                \
 460                 .src = (s),                     \
 461                 .msk = (m),                     \
 462                 .parent = (p),                  \
 463                 .nb_parent = ARRAY_SIZE((p))    \
 464         }
 465
 466 #define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, off4, off5, off6,\
 467                         p1, p2, p3, p4) \
 468         [(idx)] = {                             \
 469                 .plltype = (type),                      \
 470                 .rckxselr = (off1),             \
 471                 .pllxcfgr1 = (off2),            \
 472                 .pllxcfgr2 = (off3),            \
 473                 .pllxfracr = (off4),            \
 474                 .pllxcr = (off5),               \
 475                 .pllxcsgr = (off6),             \
 476                 .refclk[0] = (p1),              \
 477                 .refclk[1] = (p2),              \
 478                 .refclk[2] = (p3),              \
 479                 .refclk[3] = (p4),              \
 480         }
 481
 482 static const u8 stm32mp1_clks[][2] = {
 483         {CK_PER, _CK_PER},
 484         {CK_MPU, _CK_MPU},
 485         {CK_AXI, _ACLK},
 486         {CK_MCU, _CK_MCU},
 487         {CK_HSE, _HSE},
 488         {CK_CSI, _CSI},
 489         {CK_LSI, _LSI},
 490         {CK_LSE, _LSE},
 491         {CK_HSI, _HSI},
 492         {CK_HSE_DIV2, _HSE_KER_DIV2},
 493 };
 494
 495 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
 496         STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL),
 497         STM32MP1_CLK(RCC_DDRITFCR, 1, DDRC1LP, _UNKNOWN_SEL),
 498         STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL),
 499         STM32MP1_CLK(RCC_DDRITFCR, 3, DDRC2LP, _UNKNOWN_SEL),
 500         STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
 501         STM32MP1_CLK(RCC_DDRITFCR, 5, DDRPHYCLP, _UNKNOWN_SEL),
 502         STM32MP1_CLK(RCC_DDRITFCR, 6, DDRCAPB, _UNKNOWN_SEL),
 503         STM32MP1_CLK(RCC_DDRITFCR, 7, DDRCAPBLP, _UNKNOWN_SEL),
 504         STM32MP1_CLK(RCC_DDRITFCR, 8, AXIDCG, _UNKNOWN_SEL),
 505         STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL),
 506         STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL),
 507
 508         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
 509         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
 510         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
 511         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL),
 512         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL),
 513         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL),
 514         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL),
 515         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL),
 516         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL),
 517         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
 518
 519         STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
 520
 521         STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3),
 522
 523         STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 0, LTDC_PX, _PLL4_Q),
 524         STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 4, DSI_PX, _PLL4_Q),
 525         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 4, DSI_K, _DSI_SEL),
 526         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
 527         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
 528         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
 529
 530         STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
 531         STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
 532
 533         STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB2ENSETR, 5, ADC12, _HCLK2),
 534         STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 5, ADC12_K, _ADC12_SEL),
 535         STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
 536         STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
 537
 538         STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 11, HSEM, _UNKNOWN_SEL),
 539         STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 12, IPCC, _UNKNOWN_SEL),
 540
 541         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
 542         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
 543         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
 544         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL),
 545         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL),
 546         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL),
 547         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL),
 548         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL),
 549         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL),
 550         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL),
 551         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
 552
 553         STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
 554
 555         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK, _ETH_SEL),
 556         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL),
 557         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL),
 558         STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK),
 559         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
 560         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
 561         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL),
 562         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL),
 563         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL),
 564
 565         STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
 566 };
 567
 568 static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
 569 static const u8 i2c35_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
 570 static const u8 i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER};
 571 static const u8 uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
 572                                         _HSE_KER};
 573 static const u8 uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 574                                          _HSE_KER};
 575 static const u8 uart35_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 576                                          _HSE_KER};
 577 static const u8 uart78_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 578                                          _HSE_KER};
 579 static const u8 sdmmc12_parents[] = {_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER};
 580 static const u8 sdmmc3_parents[] = {_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER};
 581 static const u8 eth_parents[] = {_PLL4_P, _PLL3_Q};
 582 static const u8 qspi_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
 583 static const u8 fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
 584 static const u8 usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2};
 585 static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48};
 586 static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER};
 587 static const u8 dsi_parents[] = {_DSI_PHY, _PLL4_P};
 588 static const u8 adc_parents[] = {_PLL4_R, _CK_PER, _PLL3_Q};
 589
 590 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
 591         STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents),
 592         STM32MP1_CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents),
 593         STM32MP1_CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents),
 594         STM32MP1_CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents),
 595         STM32MP1_CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7,
 596                             uart24_parents),
 597         STM32MP1_CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7,
 598                             uart35_parents),
 599         STM32MP1_CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7,
 600                             uart78_parents),
 601         STM32MP1_CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7,
 602                             sdmmc12_parents),
 603         STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7,
 604                             sdmmc3_parents),
 605         STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents),
 606         STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents),
 607         STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents),
 608         STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents),
 609         STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
 610         STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
 611         STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents),
 612         STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x1, adc_parents),
 613 };
 614
 615 #ifdef STM32MP1_CLOCK_TREE_INIT
 616 /* define characteristic of PLL according type */
 617 #define DIVN_MIN        24
 618 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
 619         [PLL_800] = {
 620                 .refclk_min = 4,
 621                 .refclk_max = 16,
 622                 .divn_max = 99,
 623                 },
 624         [PLL_1600] = {
 625                 .refclk_min = 8,
 626                 .refclk_max = 16,
 627                 .divn_max = 199,
 628                 },
 629 };
 630 #endif /* STM32MP1_CLOCK_TREE_INIT */
 631
 632 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = {
 633         STM32MP1_CLK_PLL(_PLL1, PLL_1600,
 634                          RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2,
 635                          RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR,
 636                          _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
 637         STM32MP1_CLK_PLL(_PLL2, PLL_1600,
 638                          RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2,
 639                          RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR,
 640                          _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
 641         STM32MP1_CLK_PLL(_PLL3, PLL_800,
 642                          RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2,
 643                          RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR,
 644                          _HSI, _HSE, _CSI, _UNKNOWN_ID),
 645         STM32MP1_CLK_PLL(_PLL4, PLL_800,
 646                          RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2,
 647                          RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR,
 648                          _HSI, _HSE, _CSI, _I2S_CKIN),
 649 };
 650
 651 /* Prescaler table lookups for clock computation */
 652 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */
 653 static const u8 stm32mp1_mcu_div[16] = {
 654         0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9
 655 };
 656
 657 /* div = /1 /2 /4 /8 /16 : same divider for pmu and apbx*/
 658 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div
 659 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div
 660 static const u8 stm32mp1_mpu_apbx_div[8] = {
 661         0, 1, 2, 3, 4, 4, 4, 4
 662 };
 663
 664 /* div = /1 /2 /3 /4 */
 665 static const u8 stm32mp1_axi_div[8] = {
 666         1, 2, 3, 4, 4, 4, 4, 4
 667 };
 668
 669 #ifdef DEBUG
 670 static const char * const stm32mp1_clk_parent_name[_PARENT_NB] = {
 671         [_HSI] = "HSI",
 672         [_HSE] = "HSE",
 673         [_CSI] = "CSI",
 674         [_LSI] = "LSI",
 675         [_LSE] = "LSE",
 676         [_I2S_CKIN] = "I2S_CKIN",
 677         [_HSI_KER] = "HSI_KER",
 678         [_HSE_KER] = "HSE_KER",
 679         [_HSE_KER_DIV2] = "HSE_KER_DIV2",
 680         [_CSI_KER] = "CSI_KER",
 681         [_PLL1_P] = "PLL1_P",
 682         [_PLL1_Q] = "PLL1_Q",
 683         [_PLL1_R] = "PLL1_R",
 684         [_PLL2_P] = "PLL2_P",
 685         [_PLL2_Q] = "PLL2_Q",
 686         [_PLL2_R] = "PLL2_R",
 687         [_PLL3_P] = "PLL3_P",
 688         [_PLL3_Q] = "PLL3_Q",
 689         [_PLL3_R] = "PLL3_R",
 690         [_PLL4_P] = "PLL4_P",
 691         [_PLL4_Q] = "PLL4_Q",
 692         [_PLL4_R] = "PLL4_R",
 693         [_ACLK] = "ACLK",
 694         [_PCLK1] = "PCLK1",
 695         [_PCLK2] = "PCLK2",
 696         [_PCLK3] = "PCLK3",
 697         [_PCLK4] = "PCLK4",
 698         [_PCLK5] = "PCLK5",
 699         [_HCLK6] = "KCLK6",
 700         [_HCLK2] = "HCLK2",
 701         [_CK_PER] = "CK_PER",
 702         [_CK_MPU] = "CK_MPU",
 703         [_CK_MCU] = "CK_MCU",
 704         [_USB_PHY_48] = "USB_PHY_48",
 705         [_DSI_PHY] = "DSI_PHY_PLL",
 706 };
 707
 708 static const char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
 709         [_I2C12_SEL] = "I2C12",
 710         [_I2C35_SEL] = "I2C35",
 711         [_I2C46_SEL] = "I2C46",
 712         [_UART6_SEL] = "UART6",
 713         [_UART24_SEL] = "UART24",
 714         [_UART35_SEL] = "UART35",
 715         [_UART78_SEL] = "UART78",
 716         [_SDMMC12_SEL] = "SDMMC12",
 717         [_SDMMC3_SEL] = "SDMMC3",
 718         [_ETH_SEL] = "ETH",
 719         [_QSPI_SEL] = "QSPI",
 720         [_FMC_SEL] = "FMC",
 721         [_USBPHY_SEL] = "USBPHY",
 722         [_USBO_SEL] = "USBO",
 723         [_STGEN_SEL] = "STGEN",
 724         [_DSI_SEL] = "DSI",
 725         [_ADC12_SEL] = "ADC12",
 726 };
 727 #endif
 728
 729 static const struct stm32mp1_clk_data stm32mp1_data = {
 730         .gate = stm32mp1_clk_gate,
 731         .sel = stm32mp1_clk_sel,
 732         .pll = stm32mp1_clk_pll,
 733         .nb_gate = ARRAY_SIZE(stm32mp1_clk_gate),
 734 };
 735
 736 static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx)
 737 {
 738         if (idx >= NB_OSC) {
 739                 debug("%s: clk id %d not found\n", __func__, idx);
 740                 return 0;
 741         }
 742
 743         debug("%s: clk id %d = %x : %ld kHz\n", __func__, idx,
 744               (u32)priv->osc[idx], priv->osc[idx] / 1000);
 745
 746         return priv->osc[idx];
 747 }
 748
 749 static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id)
 750 {
 751         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 752         int i, nb_clks = priv->data->nb_gate;
 753
 754         for (i = 0; i < nb_clks; i++) {
 755                 if (gate[i].index == id)
 756                         break;
 757         }
 758
 759         if (i == nb_clks) {
 760                 printf("%s: clk id %d not found\n", __func__, (u32)id);
 761                 return -EINVAL;
 762         }
 763
 764         return i;
 765 }
 766
 767 static int stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv,
 768                                 int i)
 769 {
 770         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 771
 772         if (gate[i].sel > _PARENT_SEL_NB) {
 773                 printf("%s: parents for clk id %d not found\n",
 774                        __func__, i);
 775                 return -EINVAL;
 776         }
 777
 778         return gate[i].sel;
 779 }
 780
 781 static int stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv *priv,
 782                                          int i)
 783 {
 784         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 785
 786         if (gate[i].fixed == _UNKNOWN_ID)
 787                 return -ENOENT;
 788
 789         return gate[i].fixed;
 790 }
 791
 792 static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv,
 793                                    unsigned long id)
 794 {
 795         const struct stm32mp1_clk_sel *sel = priv->data->sel;
 796         int i;
 797         int s, p;
 798
 799         for (i = 0; i < ARRAY_SIZE(stm32mp1_clks); i++)
 800                 if (stm32mp1_clks[i][0] == id)
 801                         return stm32mp1_clks[i][1];
 802
 803         i = stm32mp1_clk_get_id(priv, id);
 804         if (i < 0)
 805                 return i;
 806
 807         p = stm32mp1_clk_get_fixed_parent(priv, i);
 808         if (p >= 0 && p < _PARENT_NB)
 809                 return p;
 810
 811         s = stm32mp1_clk_get_sel(priv, i);
 812         if (s < 0)
 813                 return s;
 814
 815         p = (readl(priv->base + sel[s].offset) >> sel[s].src) & sel[s].msk;
 816
 817         if (p < sel[s].nb_parent) {
 818 #ifdef DEBUG
 819                 debug("%s: %s clock is the parent %s of clk id %d\n", __func__,
 820                       stm32mp1_clk_parent_name[sel[s].parent[p]],
 821                       stm32mp1_clk_parent_sel_name[s],
 822                       (u32)id);
 823 #endif
 824                 return sel[s].parent[p];
 825         }
 826
 827         pr_err("%s: no parents defined for clk id %d\n",
 828                __func__, (u32)id);
 829
 830         return -EINVAL;
 831 }
 832
 833 static ulong  pll_get_fref_ck(struct stm32mp1_clk_priv *priv,
 834                               int pll_id)
 835 {
 836         const struct stm32mp1_clk_pll *pll = priv->data->pll;
 837         u32 selr;
 838         int src;
 839         ulong refclk;
 840
 841         /* Get current refclk */
 842         selr = readl(priv->base + pll[pll_id].rckxselr);
 843         src = selr & RCC_SELR_SRC_MASK;
 844
 845         refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]);
 846         debug("PLL%d : selr=%x refclk = %d kHz\n",
 847               pll_id, selr, (u32)(refclk / 1000));
 848
 849         return refclk;
 850 }
 851
 852 /*
 853  * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL
 854  * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1)
 855  * - PLL3 & PLL4 => return VCO     with Fpll_y_ck = FVCO / (DIVy + 1)
 856  * => in all the case Fpll_y_ck = pll_get_fvco() / (DIVy + 1)
 857  */
 858 static ulong pll_get_fvco(struct stm32mp1_clk_priv *priv,
 859                           int pll_id)
 860 {
 861         const struct stm32mp1_clk_pll *pll = priv->data->pll;
 862         int divm, divn;
 863         ulong refclk, fvco;
 864         u32 cfgr1, fracr;
 865
 866         cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1);
 867         fracr = readl(priv->base + pll[pll_id].pllxfracr);
 868
 869         divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
 870         divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
 871
 872         debug("PLL%d : cfgr1=%x fracr=%x DIVN=%d DIVM=%d\n",
 873               pll_id, cfgr1, fracr, divn, divm);
 874
 875         refclk = pll_get_fref_ck(priv, pll_id);
 876
 877         /* with FRACV :
 878          *   Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1)
 879          * without FRACV
 880          *   Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1)
 881          */
 882         if (fracr & RCC_PLLNFRACR_FRACLE) {
 883                 u32 fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK)
 884                             >> RCC_PLLNFRACR_FRACV_SHIFT;
 885                 fvco = (ulong)lldiv((unsigned long long)refclk *
 886                                      (((divn + 1) << 13) + fracv),
 887                                      ((unsigned long long)(divm + 1)) << 13);
 888         } else {
 889                 fvco = (ulong)(refclk * (divn + 1) / (divm + 1));
 890         }
 891         debug("PLL%d : %s = %ld\n", pll_id, __func__, fvco);
 892
 893         return fvco;
 894 }
 895
 896 static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
 897                                     int pll_id, int div_id)
 898 {
 899         const struct stm32mp1_clk_pll *pll = priv->data->pll;
 900         int divy;
 901         ulong dfout;
 902         u32 cfgr2;
 903
 904         debug("%s(%d, %d)\n", __func__, pll_id, div_id);
 905         if (div_id >= _DIV_NB)
 906                 return 0;
 907
 908         cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2);
 909         divy = (cfgr2 >> RCC_PLLNCFGR2_SHIFT(div_id)) & RCC_PLLNCFGR2_DIVX_MASK;
 910
 911         debug("PLL%d : cfgr2=%x DIVY=%d\n", pll_id, cfgr2, divy);
 912
 913         dfout = pll_get_fvco(priv, pll_id) / (divy + 1);
 914         debug("        => dfout = %d kHz\n", (u32)(dfout / 1000));
 915
 916         return dfout;
 917 }
 918
 919 static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
 920 {
 921         u32 reg;
 922         ulong clock = 0;
 923
 924         switch (p) {
 925         case _CK_MPU:
 926         /* MPU sub system */
 927                 reg = readl(priv->base + RCC_MPCKSELR);
 928                 switch (reg & RCC_SELR_SRC_MASK) {
 929                 case RCC_MPCKSELR_HSI:
 930                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
 931                         break;
 932                 case RCC_MPCKSELR_HSE:
 933                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
 934                         break;
 935                 case RCC_MPCKSELR_PLL:
 936                 case RCC_MPCKSELR_PLL_MPUDIV:
 937                         clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P);
 938                         if (p == RCC_MPCKSELR_PLL_MPUDIV) {
 939                                 reg = readl(priv->base + RCC_MPCKDIVR);
 940                                 clock /= stm32mp1_mpu_div[reg &
 941                                                           RCC_MPUDIV_MASK];
 942                         }
 943                         break;
 944                 }
 945                 break;
 946         /* AXI sub system */
 947         case _ACLK:
 948         case _HCLK2:
 949         case _HCLK6:
 950         case _PCLK4:
 951         case _PCLK5:
 952                 reg = readl(priv->base + RCC_ASSCKSELR);
 953                 switch (reg & RCC_SELR_SRC_MASK) {
 954                 case RCC_ASSCKSELR_HSI:
 955                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
 956                         break;
 957                 case RCC_ASSCKSELR_HSE:
 958                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
 959                         break;
 960                 case RCC_ASSCKSELR_PLL:
 961                         clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P);
 962                         break;
 963                 }
 964
 965                 /* System clock divider */
 966                 reg = readl(priv->base + RCC_AXIDIVR);
 967                 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK];
 968
 969                 switch (p) {
 970                 case _PCLK4:
 971                         reg = readl(priv->base + RCC_APB4DIVR);
 972                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
 973                         break;
 974                 case _PCLK5:
 975                         reg = readl(priv->base + RCC_APB5DIVR);
 976                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
 977                         break;
 978                 default:
 979                         break;
 980                 }
 981                 break;
 982         /* MCU sub system */
 983         case _CK_MCU:
 984         case _PCLK1:
 985         case _PCLK2:
 986         case _PCLK3:
 987                 reg = readl(priv->base + RCC_MSSCKSELR);
 988                 switch (reg & RCC_SELR_SRC_MASK) {
 989                 case RCC_MSSCKSELR_HSI:
 990                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
 991                         break;
 992                 case RCC_MSSCKSELR_HSE:
 993                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
 994                         break;
 995                 case RCC_MSSCKSELR_CSI:
 996                         clock = stm32mp1_clk_get_fixed(priv, _CSI);
 997                         break;
 998                 case RCC_MSSCKSELR_PLL:
 999                         clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_P);
1000                         break;
1001                 }
1002
1003                 /* MCU clock divider */
1004                 reg = readl(priv->base + RCC_MCUDIVR);
1005                 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK];
1006
1007                 switch (p) {
1008                 case _PCLK1:
1009                         reg = readl(priv->base + RCC_APB1DIVR);
1010                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1011                         break;
1012                 case _PCLK2:
1013                         reg = readl(priv->base + RCC_APB2DIVR);
1014                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1015                         break;
1016                 case _PCLK3:
1017                         reg = readl(priv->base + RCC_APB3DIVR);
1018                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1019                         break;
1020                 case _CK_MCU:
1021                 default:
1022                         break;
1023                 }
1024                 break;
1025         case _CK_PER:
1026                 reg = readl(priv->base + RCC_CPERCKSELR);
1027                 switch (reg & RCC_SELR_SRC_MASK) {
1028                 case RCC_CPERCKSELR_HSI:
1029                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
1030                         break;
1031                 case RCC_CPERCKSELR_HSE:
1032                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
1033                         break;
1034                 case RCC_CPERCKSELR_CSI:
1035                         clock = stm32mp1_clk_get_fixed(priv, _CSI);
1036                         break;
1037                 }
1038                 break;
1039         case _HSI:
1040         case _HSI_KER:
1041                 clock = stm32mp1_clk_get_fixed(priv, _HSI);
1042                 break;
1043         case _CSI:
1044         case _CSI_KER:
1045                 clock = stm32mp1_clk_get_fixed(priv, _CSI);
1046                 break;
1047         case _HSE:
1048         case _HSE_KER:
1049         case _HSE_KER_DIV2:
1050                 clock = stm32mp1_clk_get_fixed(priv, _HSE);
1051                 if (p == _HSE_KER_DIV2)
1052                         clock >>= 1;
1053                 break;
1054         case _LSI:
1055                 clock = stm32mp1_clk_get_fixed(priv, _LSI);
1056                 break;
1057         case _LSE:
1058                 clock = stm32mp1_clk_get_fixed(priv, _LSE);
1059                 break;
1060         /* PLL */
1061         case _PLL1_P:
1062         case _PLL1_Q:
1063         case _PLL1_R:
1064                 clock = stm32mp1_read_pll_freq(priv, _PLL1, p - _PLL1_P);
1065                 break;
1066         case _PLL2_P:
1067         case _PLL2_Q:
1068         case _PLL2_R:
1069                 clock = stm32mp1_read_pll_freq(priv, _PLL2, p - _PLL2_P);
1070                 break;
1071         case _PLL3_P:
1072         case _PLL3_Q:
1073         case _PLL3_R:
1074                 clock = stm32mp1_read_pll_freq(priv, _PLL3, p - _PLL3_P);
1075                 break;
1076         case _PLL4_P:
1077         case _PLL4_Q:
1078         case _PLL4_R:
1079                 clock = stm32mp1_read_pll_freq(priv, _PLL4, p - _PLL4_P);
1080                 break;
1081         /* other */
1082         case _USB_PHY_48:
1083                 clock = 48000000;
1084                 break;
1085         case _DSI_PHY:
1086         {
1087                 struct clk clk;
1088                 struct udevice *dev = NULL;
1089
1090                 if (!uclass_get_device_by_name(UCLASS_CLK, "ck_dsi_phy",
1091                                                &dev)) {
1092                         if (clk_request(dev, &clk)) {
1093                                 pr_err("ck_dsi_phy request");
1094                         } else {
1095                                 clk.id = 0;
1096                                 clock = clk_get_rate(&clk);
1097                         }
1098                 }
1099                 break;
1100         }
1101         default:
1102                 break;
1103         }
1104
1105         debug("%s(%d) clock = %lx : %ld kHz\n",
1106               __func__, p, clock, clock / 1000);
1107
1108         return clock;
1109 }
1110
1111 static int stm32mp1_clk_enable(struct clk *clk)
1112 {
1113         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1114         const struct stm32mp1_clk_gate *gate = priv->data->gate;
1115         int i = stm32mp1_clk_get_id(priv, clk->id);
1116
1117         if (i < 0)
1118                 return i;
1119
1120         if (gate[i].set_clr)
1121                 writel(BIT(gate[i].bit), priv->base + gate[i].offset);
1122         else
1123                 setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1124
1125         debug("%s: id clock %d has been enabled\n", __func__, (u32)clk->id);
1126
1127         return 0;
1128 }
1129
1130 static int stm32mp1_clk_disable(struct clk *clk)
1131 {
1132         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1133         const struct stm32mp1_clk_gate *gate = priv->data->gate;
1134         int i = stm32mp1_clk_get_id(priv, clk->id);
1135
1136         if (i < 0)
1137                 return i;
1138
1139         if (gate[i].set_clr)
1140                 writel(BIT(gate[i].bit),
1141                        priv->base + gate[i].offset
1142                        + RCC_MP_ENCLRR_OFFSET);
1143         else
1144                 clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1145
1146         debug("%s: id clock %d has been disabled\n", __func__, (u32)clk->id);
1147
1148         return 0;
1149 }
1150
1151 static ulong stm32mp1_clk_get_rate(struct clk *clk)
1152 {
1153         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1154         int p = stm32mp1_clk_get_parent(priv, clk->id);
1155         ulong rate;
1156
1157         if (p < 0)
1158                 return 0;
1159
1160         rate = stm32mp1_clk_get(priv, p);
1161
1162 #ifdef DEBUG
1163         debug("%s: computed rate for id clock %d is %d (parent is %s)\n",
1164               __func__, (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]);
1165 #endif
1166         return rate;
1167 }
1168
1169 #ifdef STM32MP1_CLOCK_TREE_INIT
1170 static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset,
1171                                 u32 mask_on)
1172 {
1173         u32 address = rcc + offset;
1174
1175         if (enable)
1176                 setbits_le32(address, mask_on);
1177         else
1178                 clrbits_le32(address, mask_on);
1179 }
1180
1181 static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on)
1182 {
1183         if (enable)
1184                 setbits_le32(rcc + RCC_OCENSETR, mask_on);
1185         else
1186                 setbits_le32(rcc + RCC_OCENCLRR, mask_on);
1187 }
1188
1189 static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset,
1190                              u32 mask_rdy)
1191 {
1192         u32 mask_test = 0;
1193         u32 address = rcc + offset;
1194         u32 val;
1195         int ret;
1196
1197         if (enable)
1198                 mask_test = mask_rdy;
1199
1200         ret = readl_poll_timeout(address, val,
1201                                  (val & mask_rdy) == mask_test,
1202                                  TIMEOUT_1S);
1203
1204         if (ret)
1205                 pr_err("OSC %x @ %x timeout for enable=%d : 0x%x\n",
1206                        mask_rdy, address, enable, readl(address));
1207
1208         return ret;
1209 }
1210
1211 static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int digbyp,
1212                                 int lsedrv)
1213 {
1214         u32 value;
1215
1216         if (digbyp)
1217                 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_DIGBYP);
1218
1219         if (bypass || digbyp)
1220                 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP);
1221
1222         /*
1223          * warning: not recommended to switch directly from "high drive"
1224          * to "medium low drive", and vice-versa.
1225          */
1226         value = (readl(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK)
1227                 >> RCC_BDCR_LSEDRV_SHIFT;
1228
1229         while (value != lsedrv) {
1230                 if (value > lsedrv)
1231                         value--;
1232                 else
1233                         value++;
1234
1235                 clrsetbits_le32(rcc + RCC_BDCR,
1236                                 RCC_BDCR_LSEDRV_MASK,
1237                                 value << RCC_BDCR_LSEDRV_SHIFT);
1238         }
1239
1240         stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON);
1241 }
1242
1243 static void stm32mp1_lse_wait(fdt_addr_t rcc)
1244 {
1245         stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY);
1246 }
1247
1248 static void stm32mp1_lsi_set(fdt_addr_t rcc, int enable)
1249 {
1250         stm32mp1_ls_osc_set(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSION);
1251         stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY);
1252 }
1253
1254 static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int digbyp, int css)
1255 {
1256         if (digbyp)
1257                 setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_DIGBYP);
1258         if (bypass || digbyp)
1259                 setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_HSEBYP);
1260
1261         stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON);
1262         stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY);
1263
1264         if (css)
1265                 setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_HSECSSON);
1266 }
1267
1268 static void stm32mp1_csi_set(fdt_addr_t rcc, int enable)
1269 {
1270         stm32mp1_ls_osc_set(enable, rcc, RCC_OCENSETR, RCC_OCENR_CSION);
1271         stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY);
1272 }
1273
1274 static void stm32mp1_hsi_set(fdt_addr_t rcc, int enable)
1275 {
1276         stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_HSION);
1277         stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_HSIRDY);
1278 }
1279
1280 static int stm32mp1_set_hsidiv(fdt_addr_t rcc, u8 hsidiv)
1281 {
1282         u32 address = rcc + RCC_OCRDYR;
1283         u32 val;
1284         int ret;
1285
1286         clrsetbits_le32(rcc + RCC_HSICFGR,
1287                         RCC_HSICFGR_HSIDIV_MASK,
1288                         RCC_HSICFGR_HSIDIV_MASK & hsidiv);
1289
1290         ret = readl_poll_timeout(address, val,
1291                                  val & RCC_OCRDYR_HSIDIVRDY,
1292                                  TIMEOUT_200MS);
1293         if (ret)
1294                 pr_err("HSIDIV failed @ 0x%x: 0x%x\n",
1295                        address, readl(address));
1296
1297         return ret;
1298 }
1299
1300 static int stm32mp1_hsidiv(fdt_addr_t rcc, ulong hsifreq)
1301 {
1302         u8 hsidiv;
1303         u32 hsidivfreq = MAX_HSI_HZ;
1304
1305         for (hsidiv = 0; hsidiv < 4; hsidiv++,
1306              hsidivfreq = hsidivfreq / 2)
1307                 if (hsidivfreq == hsifreq)
1308                         break;
1309
1310         if (hsidiv == 4) {
1311                 pr_err("clk-hsi frequency invalid");
1312                 return -1;
1313         }
1314
1315         if (hsidiv > 0)
1316                 return stm32mp1_set_hsidiv(rcc, hsidiv);
1317
1318         return 0;
1319 }
1320
1321 static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id)
1322 {
1323         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1324
1325         writel(RCC_PLLNCR_PLLON, priv->base + pll[pll_id].pllxcr);
1326 }
1327
1328 static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output)
1329 {
1330         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1331         u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1332         u32 val;
1333         int ret;
1334
1335         ret = readl_poll_timeout(pllxcr, val, val & RCC_PLLNCR_PLLRDY,
1336                                  TIMEOUT_200MS);
1337
1338         if (ret) {
1339                 pr_err("PLL%d start failed @ 0x%x: 0x%x\n",
1340                        pll_id, pllxcr, readl(pllxcr));
1341                 return ret;
1342         }
1343
1344         /* start the requested output */
1345         setbits_le32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT);
1346
1347         return 0;
1348 }
1349
1350 static int pll_stop(struct stm32mp1_clk_priv *priv, int pll_id)
1351 {
1352         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1353         u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1354         u32 val;
1355
1356         /* stop all output */
1357         clrbits_le32(pllxcr,
1358                      RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN);
1359
1360         /* stop PLL */
1361         clrbits_le32(pllxcr, RCC_PLLNCR_PLLON);
1362
1363         /* wait PLL stopped */
1364         return readl_poll_timeout(pllxcr, val, (val & RCC_PLLNCR_PLLRDY) == 0,
1365                                   TIMEOUT_200MS);
1366 }
1367
1368 static void pll_config_output(struct stm32mp1_clk_priv *priv,
1369                               int pll_id, u32 *pllcfg)
1370 {
1371         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1372         fdt_addr_t rcc = priv->base;
1373         u32 value;
1374
1375         value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT)
1376                 & RCC_PLLNCFGR2_DIVP_MASK;
1377         value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT)
1378                  & RCC_PLLNCFGR2_DIVQ_MASK;
1379         value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT)
1380                  & RCC_PLLNCFGR2_DIVR_MASK;
1381         writel(value, rcc + pll[pll_id].pllxcfgr2);
1382 }
1383
1384 static int pll_config(struct stm32mp1_clk_priv *priv, int pll_id,
1385                       u32 *pllcfg, u32 fracv)
1386 {
1387         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1388         fdt_addr_t rcc = priv->base;
1389         enum stm32mp1_plltype type = pll[pll_id].plltype;
1390         int src;
1391         ulong refclk;
1392         u8 ifrge = 0;
1393         u32 value;
1394
1395         src = readl(priv->base + pll[pll_id].rckxselr) & RCC_SELR_SRC_MASK;
1396
1397         refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]) /
1398                  (pllcfg[PLLCFG_M] + 1);
1399
1400         if (refclk < (stm32mp1_pll[type].refclk_min * 1000000) ||
1401             refclk > (stm32mp1_pll[type].refclk_max * 1000000)) {
1402                 debug("invalid refclk = %x\n", (u32)refclk);
1403                 return -EINVAL;
1404         }
1405         if (type == PLL_800 && refclk >= 8000000)
1406                 ifrge = 1;
1407
1408         value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT)
1409                  & RCC_PLLNCFGR1_DIVN_MASK;
1410         value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT)
1411                  & RCC_PLLNCFGR1_DIVM_MASK;
1412         value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT)
1413                  & RCC_PLLNCFGR1_IFRGE_MASK;
1414         writel(value, rcc + pll[pll_id].pllxcfgr1);
1415
1416         /* fractional configuration: load sigma-delta modulator (SDM) */
1417
1418         /* Write into FRACV the new fractional value , and FRACLE to 0 */
1419         writel(fracv << RCC_PLLNFRACR_FRACV_SHIFT,
1420                rcc + pll[pll_id].pllxfracr);
1421
1422         /* Write FRACLE to 1 : FRACV value is loaded into the SDM */
1423         setbits_le32(rcc + pll[pll_id].pllxfracr,
1424                      RCC_PLLNFRACR_FRACLE);
1425
1426         pll_config_output(priv, pll_id, pllcfg);
1427
1428         return 0;
1429 }
1430
1431 static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg)
1432 {
1433         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1434         u32 pllxcsg;
1435
1436         pllxcsg = ((csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) &
1437                     RCC_PLLNCSGR_MOD_PER_MASK) |
1438                   ((csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) &
1439                     RCC_PLLNCSGR_INC_STEP_MASK) |
1440                   ((csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) &
1441                     RCC_PLLNCSGR_SSCG_MODE_MASK);
1442
1443         writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr);
1444 }
1445
1446 static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc)
1447 {
1448         u32 address = priv->base + (clksrc >> 4);
1449         u32 val;
1450         int ret;
1451
1452         clrsetbits_le32(address, RCC_SELR_SRC_MASK, clksrc & RCC_SELR_SRC_MASK);
1453         ret = readl_poll_timeout(address, val, val & RCC_SELR_SRCRDY,
1454                                  TIMEOUT_200MS);
1455         if (ret)
1456                 pr_err("CLKSRC %x start failed @ 0x%x: 0x%x\n",
1457                        clksrc, address, readl(address));
1458
1459         return ret;
1460 }
1461
1462 static void stgen_config(struct stm32mp1_clk_priv *priv)
1463 {
1464         int p;
1465         u32 stgenc, cntfid0;
1466         ulong rate;
1467
1468         stgenc = (u32)syscon_get_first_range(STM32MP_SYSCON_STGEN);
1469
1470         cntfid0 = readl(stgenc + STGENC_CNTFID0);
1471         p = stm32mp1_clk_get_parent(priv, STGEN_K);
1472         rate = stm32mp1_clk_get(priv, p);
1473
1474         if (cntfid0 != rate) {
1475                 pr_debug("System Generic Counter (STGEN) update\n");
1476                 clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1477                 writel(0x0, stgenc + STGENC_CNTCVL);
1478                 writel(0x0, stgenc + STGENC_CNTCVU);
1479                 writel(rate, stgenc + STGENC_CNTFID0);
1480                 setbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1481
1482                 __asm__ volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (rate));
1483
1484                 /* need to update gd->arch.timer_rate_hz with new frequency */
1485                 timer_init();
1486                 pr_debug("gd->arch.timer_rate_hz = %x\n",
1487                          (u32)gd->arch.timer_rate_hz);
1488                 pr_debug("Tick = %x\n", (u32)(get_ticks()));
1489         }
1490 }
1491
1492 static int set_clkdiv(unsigned int clkdiv, u32 address)
1493 {
1494         u32 val;
1495         int ret;
1496
1497         clrsetbits_le32(address, RCC_DIVR_DIV_MASK, clkdiv & RCC_DIVR_DIV_MASK);
1498         ret = readl_poll_timeout(address, val, val & RCC_DIVR_DIVRDY,
1499                                  TIMEOUT_200MS);
1500         if (ret)
1501                 pr_err("CLKDIV %x start failed @ 0x%x: 0x%x\n",
1502                        clkdiv, address, readl(address));
1503
1504         return ret;
1505 }
1506
1507 static void stm32mp1_mco_csg(struct stm32mp1_clk_priv *priv,
1508                              u32 clksrc, u32 clkdiv)
1509 {
1510         u32 address = priv->base + (clksrc >> 4);
1511
1512         /*
1513          * binding clksrc : bit15-4 offset
1514          *                  bit3:   disable
1515          *                  bit2-0: MCOSEL[2:0]
1516          */
1517         if (clksrc & 0x8) {
1518                 clrbits_le32(address, RCC_MCOCFG_MCOON);
1519         } else {
1520                 clrsetbits_le32(address,
1521                                 RCC_MCOCFG_MCOSRC_MASK,
1522                                 clksrc & RCC_MCOCFG_MCOSRC_MASK);
1523                 clrsetbits_le32(address,
1524                                 RCC_MCOCFG_MCODIV_MASK,
1525                                 clkdiv << RCC_MCOCFG_MCODIV_SHIFT);
1526                 setbits_le32(address, RCC_MCOCFG_MCOON);
1527         }
1528 }
1529
1530 static void set_rtcsrc(struct stm32mp1_clk_priv *priv,
1531                        unsigned int clksrc,
1532                        int lse_css)
1533 {
1534         u32 address = priv->base + RCC_BDCR;
1535
1536         if (readl(address) & RCC_BDCR_RTCCKEN)
1537                 goto skip_rtc;
1538
1539         if (clksrc == CLK_RTC_DISABLED)
1540                 goto skip_rtc;
1541
1542         clrsetbits_le32(address,
1543                         RCC_BDCR_RTCSRC_MASK,
1544                         clksrc << RCC_BDCR_RTCSRC_SHIFT);
1545
1546         setbits_le32(address, RCC_BDCR_RTCCKEN);
1547
1548 skip_rtc:
1549         if (lse_css)
1550                 setbits_le32(address, RCC_BDCR_LSECSSON);
1551 }
1552
1553 static void pkcs_config(struct stm32mp1_clk_priv *priv, u32 pkcs)
1554 {
1555         u32 address = priv->base + ((pkcs >> 4) & 0xFFF);
1556         u32 value = pkcs & 0xF;
1557         u32 mask = 0xF;
1558
1559         if (pkcs & BIT(31)) {
1560                 mask <<= 4;
1561                 value <<= 4;
1562         }
1563         clrsetbits_le32(address, mask, value);
1564 }
1565
1566 static int stm32mp1_clktree(struct udevice *dev)
1567 {
1568         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1569         fdt_addr_t rcc = priv->base;
1570         unsigned int clksrc[CLKSRC_NB];
1571         unsigned int clkdiv[CLKDIV_NB];
1572         unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
1573         ofnode plloff[_PLL_NB];
1574         int ret;
1575         int i, len;
1576         int lse_css = 0;
1577         const u32 *pkcs_cell;
1578
1579         /* check mandatory field */
1580         ret = dev_read_u32_array(dev, "st,clksrc", clksrc, CLKSRC_NB);
1581         if (ret < 0) {
1582                 debug("field st,clksrc invalid: error %d\n", ret);
1583                 return -FDT_ERR_NOTFOUND;
1584         }
1585
1586         ret = dev_read_u32_array(dev, "st,clkdiv", clkdiv, CLKDIV_NB);
1587         if (ret < 0) {
1588                 debug("field st,clkdiv invalid: error %d\n", ret);
1589                 return -FDT_ERR_NOTFOUND;
1590         }
1591
1592         /* check mandatory field in each pll */
1593         for (i = 0; i < _PLL_NB; i++) {
1594                 char name[12];
1595
1596                 sprintf(name, "st,pll@%d", i);
1597                 plloff[i] = dev_read_subnode(dev, name);
1598                 if (!ofnode_valid(plloff[i]))
1599                         continue;
1600                 ret = ofnode_read_u32_array(plloff[i], "cfg",
1601                                             pllcfg[i], PLLCFG_NB);
1602                 if (ret < 0) {
1603                         debug("field cfg invalid: error %d\n", ret);
1604                         return -FDT_ERR_NOTFOUND;
1605                 }
1606         }
1607
1608         debug("configuration MCO\n");
1609         stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]);
1610         stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]);
1611
1612         debug("switch ON osillator\n");
1613         /*
1614          * switch ON oscillator found in device-tree,
1615          * HSI already ON after bootrom
1616          */
1617         if (priv->osc[_LSI])
1618                 stm32mp1_lsi_set(rcc, 1);
1619
1620         if (priv->osc[_LSE]) {
1621                 int bypass, digbyp, lsedrv;
1622                 struct udevice *dev = priv->osc_dev[_LSE];
1623
1624                 bypass = dev_read_bool(dev, "st,bypass");
1625                 digbyp = dev_read_bool(dev, "st,digbypass");
1626                 lse_css = dev_read_bool(dev, "st,css");
1627                 lsedrv = dev_read_u32_default(dev, "st,drive",
1628                                               LSEDRV_MEDIUM_HIGH);
1629
1630                 stm32mp1_lse_enable(rcc, bypass, digbyp, lsedrv);
1631         }
1632
1633         if (priv->osc[_HSE]) {
1634                 int bypass, digbyp, css;
1635                 struct udevice *dev = priv->osc_dev[_HSE];
1636
1637                 bypass = dev_read_bool(dev, "st,bypass");
1638                 digbyp = dev_read_bool(dev, "st,digbypass");
1639                 css = dev_read_bool(dev, "st,css");
1640
1641                 stm32mp1_hse_enable(rcc, bypass, digbyp, css);
1642         }
1643         /* CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR)
1644          * => switch on CSI even if node is not present in device tree
1645          */
1646         stm32mp1_csi_set(rcc, 1);
1647
1648         /* come back to HSI */
1649         debug("come back to HSI\n");
1650         set_clksrc(priv, CLK_MPU_HSI);
1651         set_clksrc(priv, CLK_AXI_HSI);
1652         set_clksrc(priv, CLK_MCU_HSI);
1653
1654         debug("pll stop\n");
1655         for (i = 0; i < _PLL_NB; i++)
1656                 pll_stop(priv, i);
1657
1658         /* configure HSIDIV */
1659         debug("configure HSIDIV\n");
1660         if (priv->osc[_HSI]) {
1661                 stm32mp1_hsidiv(rcc, priv->osc[_HSI]);
1662                 stgen_config(priv);
1663         }
1664
1665         /* select DIV */
1666         debug("select DIV\n");
1667         /* no ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */
1668         writel(clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK, rcc + RCC_MPCKDIVR);
1669         set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR);
1670         set_clkdiv(clkdiv[CLKDIV_APB4], rcc + RCC_APB4DIVR);
1671         set_clkdiv(clkdiv[CLKDIV_APB5], rcc + RCC_APB5DIVR);
1672         set_clkdiv(clkdiv[CLKDIV_MCU], rcc + RCC_MCUDIVR);
1673         set_clkdiv(clkdiv[CLKDIV_APB1], rcc + RCC_APB1DIVR);
1674         set_clkdiv(clkdiv[CLKDIV_APB2], rcc + RCC_APB2DIVR);
1675         set_clkdiv(clkdiv[CLKDIV_APB3], rcc + RCC_APB3DIVR);
1676
1677         /* no ready bit for RTC */
1678         writel(clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK, rcc + RCC_RTCDIVR);
1679
1680         /* configure PLLs source */
1681         debug("configure PLLs source\n");
1682         set_clksrc(priv, clksrc[CLKSRC_PLL12]);
1683         set_clksrc(priv, clksrc[CLKSRC_PLL3]);
1684         set_clksrc(priv, clksrc[CLKSRC_PLL4]);
1685
1686         /* configure and start PLLs */
1687         debug("configure PLLs\n");
1688         for (i = 0; i < _PLL_NB; i++) {
1689                 u32 fracv;
1690                 u32 csg[PLLCSG_NB];
1691
1692                 debug("configure PLL %d @ %d\n", i,
1693                       ofnode_to_offset(plloff[i]));
1694                 if (!ofnode_valid(plloff[i]))
1695                         continue;
1696
1697                 fracv = ofnode_read_u32_default(plloff[i], "frac", 0);
1698                 pll_config(priv, i, pllcfg[i], fracv);
1699                 ret = ofnode_read_u32_array(plloff[i], "csg", csg, PLLCSG_NB);
1700                 if (!ret) {
1701                         pll_csg(priv, i, csg);
1702                 } else if (ret != -FDT_ERR_NOTFOUND) {
1703                         debug("invalid csg node for pll@%d res=%d\n", i, ret);
1704                         return ret;
1705                 }
1706                 pll_start(priv, i);
1707         }
1708
1709         /* wait and start PLLs ouptut when ready */
1710         for (i = 0; i < _PLL_NB; i++) {
1711                 if (!ofnode_valid(plloff[i]))
1712                         continue;
1713                 debug("output PLL %d\n", i);
1714                 pll_output(priv, i, pllcfg[i][PLLCFG_O]);
1715         }
1716
1717         /* wait LSE ready before to use it */
1718         if (priv->osc[_LSE])
1719                 stm32mp1_lse_wait(rcc);
1720
1721         /* configure with expected clock source */
1722         debug("CLKSRC\n");
1723         set_clksrc(priv, clksrc[CLKSRC_MPU]);
1724         set_clksrc(priv, clksrc[CLKSRC_AXI]);
1725         set_clksrc(priv, clksrc[CLKSRC_MCU]);
1726         set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css);
1727
1728         /* configure PKCK */
1729         debug("PKCK\n");
1730         pkcs_cell = dev_read_prop(dev, "st,pkcs", &len);
1731         if (pkcs_cell) {
1732                 bool ckper_disabled = false;
1733
1734                 for (i = 0; i < len / sizeof(u32); i++) {
1735                         u32 pkcs = (u32)fdt32_to_cpu(pkcs_cell[i]);
1736
1737                         if (pkcs == CLK_CKPER_DISABLED) {
1738                                 ckper_disabled = true;
1739                                 continue;
1740                         }
1741                         pkcs_config(priv, pkcs);
1742                 }
1743                 /* CKPER is source for some peripheral clock
1744                  * (FMC-NAND / QPSI-NOR) and switching source is allowed
1745                  * only if previous clock is still ON
1746                  * => deactivated CKPER only after switching clock
1747                  */
1748                 if (ckper_disabled)
1749                         pkcs_config(priv, CLK_CKPER_DISABLED);
1750         }
1751
1752         /* STGEN clock source can change with CLK_STGEN_XXX */
1753         stgen_config(priv);
1754
1755         debug("oscillator off\n");
1756         /* switch OFF HSI if not found in device-tree */
1757         if (!priv->osc[_HSI])
1758                 stm32mp1_hsi_set(rcc, 0);
1759
1760         /* Software Self-Refresh mode (SSR) during DDR initilialization */
1761         clrsetbits_le32(priv->base + RCC_DDRITFCR,
1762                         RCC_DDRITFCR_DDRCKMOD_MASK,
1763                         RCC_DDRITFCR_DDRCKMOD_SSR <<
1764                         RCC_DDRITFCR_DDRCKMOD_SHIFT);
1765
1766         return 0;
1767 }
1768 #endif /* STM32MP1_CLOCK_TREE_INIT */
1769
1770 static int pll_set_output_rate(struct udevice *dev,
1771                                int pll_id,
1772                                int div_id,
1773                                unsigned long clk_rate)
1774 {
1775         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1776         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1777         u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1778         int div;
1779         ulong fvco;
1780
1781         if (div_id > _DIV_NB)
1782                 return -EINVAL;
1783
1784         fvco = pll_get_fvco(priv, pll_id);
1785
1786         if (fvco <= clk_rate)
1787                 div = 1;
1788         else
1789                 div = DIV_ROUND_UP(fvco, clk_rate);
1790
1791         if (div > 128)
1792                 div = 128;
1793
1794         debug("fvco = %ld, clk_rate = %ld, div=%d\n", fvco, clk_rate, div);
1795         /* stop the requested output */
1796         clrbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
1797         /* change divider */
1798         clrsetbits_le32(priv->base + pll[pll_id].pllxcfgr2,
1799                         RCC_PLLNCFGR2_DIVX_MASK << RCC_PLLNCFGR2_SHIFT(div_id),
1800                         (div - 1) << RCC_PLLNCFGR2_SHIFT(div_id));
1801         /* start the requested output */
1802         setbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
1803
1804         return 0;
1805 }
1806
1807 static ulong stm32mp1_clk_set_rate(struct clk *clk, unsigned long clk_rate)
1808 {
1809         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1810         int p;
1811
1812         switch (clk->id) {
1813         case LTDC_PX:
1814         case DSI_PX:
1815                 break;
1816         default:
1817                 pr_err("not supported");
1818                 return -EINVAL;
1819         }
1820
1821         p = stm32mp1_clk_get_parent(priv, clk->id);
1822         if (p < 0)
1823                 return -EINVAL;
1824
1825         switch (p) {
1826         case _PLL4_Q:
1827                 /* for LTDC_PX and DSI_PX case */
1828                 return pll_set_output_rate(clk->dev, _PLL4, _DIV_Q, clk_rate);
1829         }
1830
1831         return -EINVAL;
1832 }
1833
1834 static void stm32mp1_osc_clk_init(const char *name,
1835                                   struct stm32mp1_clk_priv *priv,
1836                                   int index)
1837 {
1838         struct clk clk;
1839         struct udevice *dev = NULL;
1840
1841         priv->osc[index] = 0;
1842         clk.id = 0;
1843         if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) {
1844                 if (clk_request(dev, &clk))
1845                         pr_err("%s request", name);
1846                 else
1847                         priv->osc[index] = clk_get_rate(&clk);
1848         }
1849         priv->osc_dev[index] = dev;
1850 }
1851
1852 static void stm32mp1_osc_init(struct udevice *dev)
1853 {
1854         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1855         int i;
1856         const char *name[NB_OSC] = {
1857                 [_LSI] = "clk-lsi",
1858                 [_LSE] = "clk-lse",
1859                 [_HSI] = "clk-hsi",
1860                 [_HSE] = "clk-hse",
1861                 [_CSI] = "clk-csi",
1862                 [_I2S_CKIN] = "i2s_ckin",
1863         };
1864
1865         for (i = 0; i < NB_OSC; i++) {
1866                 stm32mp1_osc_clk_init(name[i], priv, i);
1867                 debug("%d: %s => %x\n", i, name[i], (u32)priv->osc[i]);
1868         }
1869 }
1870
1871 static int stm32mp1_clk_probe(struct udevice *dev)
1872 {
1873         int result = 0;
1874         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1875
1876         priv->base = dev_read_addr(dev->parent);
1877         if (priv->base == FDT_ADDR_T_NONE)
1878                 return -EINVAL;
1879
1880         priv->data = (void *)&stm32mp1_data;
1881
1882         if (!priv->data->gate || !priv->data->sel ||
1883             !priv->data->pll)
1884                 return -EINVAL;
1885
1886         stm32mp1_osc_init(dev);
1887
1888 #ifdef STM32MP1_CLOCK_TREE_INIT
1889         /* clock tree init is done only one time, before relocation */
1890         if (!(gd->flags & GD_FLG_RELOC))
1891                 result = stm32mp1_clktree(dev);
1892 #endif
1893
1894         return result;
1895 }
1896
1897 static const struct clk_ops stm32mp1_clk_ops = {
1898         .enable = stm32mp1_clk_enable,
1899         .disable = stm32mp1_clk_disable,
1900         .get_rate = stm32mp1_clk_get_rate,
1901         .set_rate = stm32mp1_clk_set_rate,
1902 };
1903
1904 U_BOOT_DRIVER(stm32mp1_clock) = {
1905         .name = "stm32mp1_clk",
1906         .id = UCLASS_CLK,
1907         .ops = &stm32mp1_clk_ops,
1908         .priv_auto_alloc_size = sizeof(struct stm32mp1_clk_priv),
1909         .probe = stm32mp1_clk_probe,
1910 };