drivers/clk/clk_stm32mp1.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   4  */
   5
   6 #include <common.h>
   7 #include <clk-uclass.h>
   8 #include <div64.h>
   9 #include <dm.h>
  10 #include <regmap.h>
  11 #include <spl.h>
  12 #include <syscon.h>
  13 #include <time.h>
  14 #include <vsprintf.h>
  15 #include <linux/io.h>
  16 #include <linux/iopoll.h>
  17 #include <dt-bindings/clock/stm32mp1-clks.h>
  18 #include <dt-bindings/clock/stm32mp1-clksrc.h>
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 #ifndef CONFIG_STM32MP1_TRUSTED
  23 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
  24 /* activate clock tree initialization in the driver */
  25 #define STM32MP1_CLOCK_TREE_INIT
  26 #endif
  27 #endif
  28
  29 #define MAX_HSI_HZ              64000000
  30
  31 /* TIMEOUT */
  32 #define TIMEOUT_200MS           200000
  33 #define TIMEOUT_1S              1000000
  34
  35 /* STGEN registers */
  36 #define STGENC_CNTCR            0x00
  37 #define STGENC_CNTSR            0x04
  38 #define STGENC_CNTCVL           0x08
  39 #define STGENC_CNTCVU           0x0C
  40 #define STGENC_CNTFID0          0x20
  41
  42 #define STGENC_CNTCR_EN         BIT(0)
  43
  44 /* RCC registers */
  45 #define RCC_OCENSETR            0x0C
  46 #define RCC_OCENCLRR            0x10
  47 #define RCC_HSICFGR             0x18
  48 #define RCC_MPCKSELR            0x20
  49 #define RCC_ASSCKSELR           0x24
  50 #define RCC_RCK12SELR           0x28
  51 #define RCC_MPCKDIVR            0x2C
  52 #define RCC_AXIDIVR             0x30
  53 #define RCC_APB4DIVR            0x3C
  54 #define RCC_APB5DIVR            0x40
  55 #define RCC_RTCDIVR             0x44
  56 #define RCC_MSSCKSELR           0x48
  57 #define RCC_PLL1CR              0x80
  58 #define RCC_PLL1CFGR1           0x84
  59 #define RCC_PLL1CFGR2           0x88
  60 #define RCC_PLL1FRACR           0x8C
  61 #define RCC_PLL1CSGR            0x90
  62 #define RCC_PLL2CR              0x94
  63 #define RCC_PLL2CFGR1           0x98
  64 #define RCC_PLL2CFGR2           0x9C
  65 #define RCC_PLL2FRACR           0xA0
  66 #define RCC_PLL2CSGR            0xA4
  67 #define RCC_I2C46CKSELR         0xC0
  68 #define RCC_CPERCKSELR          0xD0
  69 #define RCC_STGENCKSELR         0xD4
  70 #define RCC_DDRITFCR            0xD8
  71 #define RCC_BDCR                0x140
  72 #define RCC_RDLSICR             0x144
  73 #define RCC_MP_APB4ENSETR       0x200
  74 #define RCC_MP_APB5ENSETR       0x208
  75 #define RCC_MP_AHB5ENSETR       0x210
  76 #define RCC_MP_AHB6ENSETR       0x218
  77 #define RCC_OCRDYR              0x808
  78 #define RCC_DBGCFGR             0x80C
  79 #define RCC_RCK3SELR            0x820
  80 #define RCC_RCK4SELR            0x824
  81 #define RCC_MCUDIVR             0x830
  82 #define RCC_APB1DIVR            0x834
  83 #define RCC_APB2DIVR            0x838
  84 #define RCC_APB3DIVR            0x83C
  85 #define RCC_PLL3CR              0x880
  86 #define RCC_PLL3CFGR1           0x884
  87 #define RCC_PLL3CFGR2           0x888
  88 #define RCC_PLL3FRACR           0x88C
  89 #define RCC_PLL3CSGR            0x890
  90 #define RCC_PLL4CR              0x894
  91 #define RCC_PLL4CFGR1           0x898
  92 #define RCC_PLL4CFGR2           0x89C
  93 #define RCC_PLL4FRACR           0x8A0
  94 #define RCC_PLL4CSGR            0x8A4
  95 #define RCC_I2C12CKSELR         0x8C0
  96 #define RCC_I2C35CKSELR         0x8C4
  97 #define RCC_SPI2S1CKSELR        0x8D8
  98 #define RCC_UART6CKSELR         0x8E4
  99 #define RCC_UART24CKSELR        0x8E8
 100 #define RCC_UART35CKSELR        0x8EC
 101 #define RCC_UART78CKSELR        0x8F0
 102 #define RCC_SDMMC12CKSELR       0x8F4
 103 #define RCC_SDMMC3CKSELR        0x8F8
 104 #define RCC_ETHCKSELR           0x8FC
 105 #define RCC_QSPICKSELR          0x900
 106 #define RCC_FMCCKSELR           0x904
 107 #define RCC_USBCKSELR           0x91C
 108 #define RCC_DSICKSELR           0x924
 109 #define RCC_ADCCKSELR           0x928
 110 #define RCC_MP_APB1ENSETR       0xA00
 111 #define RCC_MP_APB2ENSETR       0XA08
 112 #define RCC_MP_APB3ENSETR       0xA10
 113 #define RCC_MP_AHB2ENSETR       0xA18
 114 #define RCC_MP_AHB3ENSETR       0xA20
 115 #define RCC_MP_AHB4ENSETR       0xA28
 116
 117 /* used for most of SELR register */
 118 #define RCC_SELR_SRC_MASK       GENMASK(2, 0)
 119 #define RCC_SELR_SRCRDY         BIT(31)
 120
 121 /* Values of RCC_MPCKSELR register */
 122 #define RCC_MPCKSELR_HSI        0
 123 #define RCC_MPCKSELR_HSE        1
 124 #define RCC_MPCKSELR_PLL        2
 125 #define RCC_MPCKSELR_PLL_MPUDIV 3
 126
 127 /* Values of RCC_ASSCKSELR register */
 128 #define RCC_ASSCKSELR_HSI       0
 129 #define RCC_ASSCKSELR_HSE       1
 130 #define RCC_ASSCKSELR_PLL       2
 131
 132 /* Values of RCC_MSSCKSELR register */
 133 #define RCC_MSSCKSELR_HSI       0
 134 #define RCC_MSSCKSELR_HSE       1
 135 #define RCC_MSSCKSELR_CSI       2
 136 #define RCC_MSSCKSELR_PLL       3
 137
 138 /* Values of RCC_CPERCKSELR register */
 139 #define RCC_CPERCKSELR_HSI      0
 140 #define RCC_CPERCKSELR_CSI      1
 141 #define RCC_CPERCKSELR_HSE      2
 142
 143 /* used for most of DIVR register : max div for RTC */
 144 #define RCC_DIVR_DIV_MASK       GENMASK(5, 0)
 145 #define RCC_DIVR_DIVRDY         BIT(31)
 146
 147 /* Masks for specific DIVR registers */
 148 #define RCC_APBXDIV_MASK        GENMASK(2, 0)
 149 #define RCC_MPUDIV_MASK         GENMASK(2, 0)
 150 #define RCC_AXIDIV_MASK         GENMASK(2, 0)
 151 #define RCC_MCUDIV_MASK         GENMASK(3, 0)
 152
 153 /*  offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
 154 #define RCC_MP_ENCLRR_OFFSET    4
 155
 156 /* Fields of RCC_BDCR register */
 157 #define RCC_BDCR_LSEON          BIT(0)
 158 #define RCC_BDCR_LSEBYP         BIT(1)
 159 #define RCC_BDCR_LSERDY         BIT(2)
 160 #define RCC_BDCR_DIGBYP         BIT(3)
 161 #define RCC_BDCR_LSEDRV_MASK    GENMASK(5, 4)
 162 #define RCC_BDCR_LSEDRV_SHIFT   4
 163 #define RCC_BDCR_LSECSSON       BIT(8)
 164 #define RCC_BDCR_RTCCKEN        BIT(20)
 165 #define RCC_BDCR_RTCSRC_MASK    GENMASK(17, 16)
 166 #define RCC_BDCR_RTCSRC_SHIFT   16
 167
 168 /* Fields of RCC_RDLSICR register */
 169 #define RCC_RDLSICR_LSION       BIT(0)
 170 #define RCC_RDLSICR_LSIRDY      BIT(1)
 171
 172 /* used for ALL PLLNCR registers */
 173 #define RCC_PLLNCR_PLLON        BIT(0)
 174 #define RCC_PLLNCR_PLLRDY       BIT(1)
 175 #define RCC_PLLNCR_SSCG_CTRL    BIT(2)
 176 #define RCC_PLLNCR_DIVPEN       BIT(4)
 177 #define RCC_PLLNCR_DIVQEN       BIT(5)
 178 #define RCC_PLLNCR_DIVREN       BIT(6)
 179 #define RCC_PLLNCR_DIVEN_SHIFT  4
 180
 181 /* used for ALL PLLNCFGR1 registers */
 182 #define RCC_PLLNCFGR1_DIVM_SHIFT        16
 183 #define RCC_PLLNCFGR1_DIVM_MASK         GENMASK(21, 16)
 184 #define RCC_PLLNCFGR1_DIVN_SHIFT        0
 185 #define RCC_PLLNCFGR1_DIVN_MASK         GENMASK(8, 0)
 186 /* only for PLL3 and PLL4 */
 187 #define RCC_PLLNCFGR1_IFRGE_SHIFT       24
 188 #define RCC_PLLNCFGR1_IFRGE_MASK        GENMASK(25, 24)
 189
 190 /* used for ALL PLLNCFGR2 registers , using stm32mp1_div_id */
 191 #define RCC_PLLNCFGR2_SHIFT(div_id)     ((div_id) * 8)
 192 #define RCC_PLLNCFGR2_DIVX_MASK         GENMASK(6, 0)
 193 #define RCC_PLLNCFGR2_DIVP_SHIFT        RCC_PLLNCFGR2_SHIFT(_DIV_P)
 194 #define RCC_PLLNCFGR2_DIVP_MASK         GENMASK(6, 0)
 195 #define RCC_PLLNCFGR2_DIVQ_SHIFT        RCC_PLLNCFGR2_SHIFT(_DIV_Q)
 196 #define RCC_PLLNCFGR2_DIVQ_MASK         GENMASK(14, 8)
 197 #define RCC_PLLNCFGR2_DIVR_SHIFT        RCC_PLLNCFGR2_SHIFT(_DIV_R)
 198 #define RCC_PLLNCFGR2_DIVR_MASK         GENMASK(22, 16)
 199
 200 /* used for ALL PLLNFRACR registers */
 201 #define RCC_PLLNFRACR_FRACV_SHIFT       3
 202 #define RCC_PLLNFRACR_FRACV_MASK        GENMASK(15, 3)
 203 #define RCC_PLLNFRACR_FRACLE            BIT(16)
 204
 205 /* used for ALL PLLNCSGR registers */
 206 #define RCC_PLLNCSGR_INC_STEP_SHIFT     16
 207 #define RCC_PLLNCSGR_INC_STEP_MASK      GENMASK(30, 16)
 208 #define RCC_PLLNCSGR_MOD_PER_SHIFT      0
 209 #define RCC_PLLNCSGR_MOD_PER_MASK       GENMASK(12, 0)
 210 #define RCC_PLLNCSGR_SSCG_MODE_SHIFT    15
 211 #define RCC_PLLNCSGR_SSCG_MODE_MASK     BIT(15)
 212
 213 /* used for RCC_OCENSETR and RCC_OCENCLRR registers */
 214 #define RCC_OCENR_HSION                 BIT(0)
 215 #define RCC_OCENR_CSION                 BIT(4)
 216 #define RCC_OCENR_DIGBYP                BIT(7)
 217 #define RCC_OCENR_HSEON                 BIT(8)
 218 #define RCC_OCENR_HSEBYP                BIT(10)
 219 #define RCC_OCENR_HSECSSON              BIT(11)
 220
 221 /* Fields of RCC_OCRDYR register */
 222 #define RCC_OCRDYR_HSIRDY               BIT(0)
 223 #define RCC_OCRDYR_HSIDIVRDY            BIT(2)
 224 #define RCC_OCRDYR_CSIRDY               BIT(4)
 225 #define RCC_OCRDYR_HSERDY               BIT(8)
 226
 227 /* Fields of DDRITFCR register */
 228 #define RCC_DDRITFCR_DDRCKMOD_MASK      GENMASK(22, 20)
 229 #define RCC_DDRITFCR_DDRCKMOD_SHIFT     20
 230 #define RCC_DDRITFCR_DDRCKMOD_SSR       0
 231
 232 /* Fields of RCC_HSICFGR register */
 233 #define RCC_HSICFGR_HSIDIV_MASK         GENMASK(1, 0)
 234
 235 /* used for MCO related operations */
 236 #define RCC_MCOCFG_MCOON                BIT(12)
 237 #define RCC_MCOCFG_MCODIV_MASK          GENMASK(7, 4)
 238 #define RCC_MCOCFG_MCODIV_SHIFT         4
 239 #define RCC_MCOCFG_MCOSRC_MASK          GENMASK(2, 0)
 240
 241 enum stm32mp1_parent_id {
 242 /*
 243  * _HSI, _HSE, _CSI, _LSI, _LSE should not be moved
 244  * they are used as index in osc[] as entry point
 245  */
 246         _HSI,
 247         _HSE,
 248         _CSI,
 249         _LSI,
 250         _LSE,
 251         _I2S_CKIN,
 252         NB_OSC,
 253
 254 /* other parent source */
 255         _HSI_KER = NB_OSC,
 256         _HSE_KER,
 257         _HSE_KER_DIV2,
 258         _CSI_KER,
 259         _PLL1_P,
 260         _PLL1_Q,
 261         _PLL1_R,
 262         _PLL2_P,
 263         _PLL2_Q,
 264         _PLL2_R,
 265         _PLL3_P,
 266         _PLL3_Q,
 267         _PLL3_R,
 268         _PLL4_P,
 269         _PLL4_Q,
 270         _PLL4_R,
 271         _ACLK,
 272         _PCLK1,
 273         _PCLK2,
 274         _PCLK3,
 275         _PCLK4,
 276         _PCLK5,
 277         _HCLK6,
 278         _HCLK2,
 279         _CK_PER,
 280         _CK_MPU,
 281         _CK_MCU,
 282         _DSI_PHY,
 283         _USB_PHY_48,
 284         _PARENT_NB,
 285         _UNKNOWN_ID = 0xff,
 286 };
 287
 288 enum stm32mp1_parent_sel {
 289         _I2C12_SEL,
 290         _I2C35_SEL,
 291         _I2C46_SEL,
 292         _UART6_SEL,
 293         _UART24_SEL,
 294         _UART35_SEL,
 295         _UART78_SEL,
 296         _SDMMC12_SEL,
 297         _SDMMC3_SEL,
 298         _ETH_SEL,
 299         _QSPI_SEL,
 300         _FMC_SEL,
 301         _USBPHY_SEL,
 302         _USBO_SEL,
 303         _STGEN_SEL,
 304         _DSI_SEL,
 305         _ADC12_SEL,
 306         _SPI1_SEL,
 307         _RTC_SEL,
 308         _PARENT_SEL_NB,
 309         _UNKNOWN_SEL = 0xff,
 310 };
 311
 312 enum stm32mp1_pll_id {
 313         _PLL1,
 314         _PLL2,
 315         _PLL3,
 316         _PLL4,
 317         _PLL_NB
 318 };
 319
 320 enum stm32mp1_div_id {
 321         _DIV_P,
 322         _DIV_Q,
 323         _DIV_R,
 324         _DIV_NB,
 325 };
 326
 327 enum stm32mp1_clksrc_id {
 328         CLKSRC_MPU,
 329         CLKSRC_AXI,
 330         CLKSRC_MCU,
 331         CLKSRC_PLL12,
 332         CLKSRC_PLL3,
 333         CLKSRC_PLL4,
 334         CLKSRC_RTC,
 335         CLKSRC_MCO1,
 336         CLKSRC_MCO2,
 337         CLKSRC_NB
 338 };
 339
 340 enum stm32mp1_clkdiv_id {
 341         CLKDIV_MPU,
 342         CLKDIV_AXI,
 343         CLKDIV_MCU,
 344         CLKDIV_APB1,
 345         CLKDIV_APB2,
 346         CLKDIV_APB3,
 347         CLKDIV_APB4,
 348         CLKDIV_APB5,
 349         CLKDIV_RTC,
 350         CLKDIV_MCO1,
 351         CLKDIV_MCO2,
 352         CLKDIV_NB
 353 };
 354
 355 enum stm32mp1_pllcfg {
 356         PLLCFG_M,
 357         PLLCFG_N,
 358         PLLCFG_P,
 359         PLLCFG_Q,
 360         PLLCFG_R,
 361         PLLCFG_O,
 362         PLLCFG_NB
 363 };
 364
 365 enum stm32mp1_pllcsg {
 366         PLLCSG_MOD_PER,
 367         PLLCSG_INC_STEP,
 368         PLLCSG_SSCG_MODE,
 369         PLLCSG_NB
 370 };
 371
 372 enum stm32mp1_plltype {
 373         PLL_800,
 374         PLL_1600,
 375         PLL_TYPE_NB
 376 };
 377
 378 struct stm32mp1_pll {
 379         u8 refclk_min;
 380         u8 refclk_max;
 381         u8 divn_max;
 382 };
 383
 384 struct stm32mp1_clk_gate {
 385         u16 offset;
 386         u8 bit;
 387         u8 index;
 388         u8 set_clr;
 389         u8 sel;
 390         u8 fixed;
 391 };
 392
 393 struct stm32mp1_clk_sel {
 394         u16 offset;
 395         u8 src;
 396         u8 msk;
 397         u8 nb_parent;
 398         const u8 *parent;
 399 };
 400
 401 #define REFCLK_SIZE 4
 402 struct stm32mp1_clk_pll {
 403         enum stm32mp1_plltype plltype;
 404         u16 rckxselr;
 405         u16 pllxcfgr1;
 406         u16 pllxcfgr2;
 407         u16 pllxfracr;
 408         u16 pllxcr;
 409         u16 pllxcsgr;
 410         u8 refclk[REFCLK_SIZE];
 411 };
 412
 413 struct stm32mp1_clk_data {
 414         const struct stm32mp1_clk_gate *gate;
 415         const struct stm32mp1_clk_sel *sel;
 416         const struct stm32mp1_clk_pll *pll;
 417         const int nb_gate;
 418 };
 419
 420 struct stm32mp1_clk_priv {
 421         fdt_addr_t base;
 422         const struct stm32mp1_clk_data *data;
 423         ulong osc[NB_OSC];
 424         struct udevice *osc_dev[NB_OSC];
 425 };
 426
 427 #define STM32MP1_CLK(off, b, idx, s)            \
 428         {                                       \
 429                 .offset = (off),                \
 430                 .bit = (b),                     \
 431                 .index = (idx),                 \
 432                 .set_clr = 0,                   \
 433                 .sel = (s),                     \
 434                 .fixed = _UNKNOWN_ID,           \
 435         }
 436
 437 #define STM32MP1_CLK_F(off, b, idx, f)          \
 438         {                                       \
 439                 .offset = (off),                \
 440                 .bit = (b),                     \
 441                 .index = (idx),                 \
 442                 .set_clr = 0,                   \
 443                 .sel = _UNKNOWN_SEL,            \
 444                 .fixed = (f),                   \
 445         }
 446
 447 #define STM32MP1_CLK_SET_CLR(off, b, idx, s)    \
 448         {                                       \
 449                 .offset = (off),                \
 450                 .bit = (b),                     \
 451                 .index = (idx),                 \
 452                 .set_clr = 1,                   \
 453                 .sel = (s),                     \
 454                 .fixed = _UNKNOWN_ID,           \
 455         }
 456
 457 #define STM32MP1_CLK_SET_CLR_F(off, b, idx, f)  \
 458         {                                       \
 459                 .offset = (off),                \
 460                 .bit = (b),                     \
 461                 .index = (idx),                 \
 462                 .set_clr = 1,                   \
 463                 .sel = _UNKNOWN_SEL,            \
 464                 .fixed = (f),                   \
 465         }
 466
 467 #define STM32MP1_CLK_PARENT(idx, off, s, m, p)   \
 468         [(idx)] = {                             \
 469                 .offset = (off),                \
 470                 .src = (s),                     \
 471                 .msk = (m),                     \
 472                 .parent = (p),                  \
 473                 .nb_parent = ARRAY_SIZE((p))    \
 474         }
 475
 476 #define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, off4, off5, off6,\
 477                         p1, p2, p3, p4) \
 478         [(idx)] = {                             \
 479                 .plltype = (type),                      \
 480                 .rckxselr = (off1),             \
 481                 .pllxcfgr1 = (off2),            \
 482                 .pllxcfgr2 = (off3),            \
 483                 .pllxfracr = (off4),            \
 484                 .pllxcr = (off5),               \
 485                 .pllxcsgr = (off6),             \
 486                 .refclk[0] = (p1),              \
 487                 .refclk[1] = (p2),              \
 488                 .refclk[2] = (p3),              \
 489                 .refclk[3] = (p4),              \
 490         }
 491
 492 static const u8 stm32mp1_clks[][2] = {
 493         {CK_PER, _CK_PER},
 494         {CK_MPU, _CK_MPU},
 495         {CK_AXI, _ACLK},
 496         {CK_MCU, _CK_MCU},
 497         {CK_HSE, _HSE},
 498         {CK_CSI, _CSI},
 499         {CK_LSI, _LSI},
 500         {CK_LSE, _LSE},
 501         {CK_HSI, _HSI},
 502         {CK_HSE_DIV2, _HSE_KER_DIV2},
 503 };
 504
 505 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
 506         STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL),
 507         STM32MP1_CLK(RCC_DDRITFCR, 1, DDRC1LP, _UNKNOWN_SEL),
 508         STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL),
 509         STM32MP1_CLK(RCC_DDRITFCR, 3, DDRC2LP, _UNKNOWN_SEL),
 510         STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
 511         STM32MP1_CLK(RCC_DDRITFCR, 5, DDRPHYCLP, _UNKNOWN_SEL),
 512         STM32MP1_CLK(RCC_DDRITFCR, 6, DDRCAPB, _UNKNOWN_SEL),
 513         STM32MP1_CLK(RCC_DDRITFCR, 7, DDRCAPBLP, _UNKNOWN_SEL),
 514         STM32MP1_CLK(RCC_DDRITFCR, 8, AXIDCG, _UNKNOWN_SEL),
 515         STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL),
 516         STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL),
 517
 518         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
 519         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
 520         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
 521         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL),
 522         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL),
 523         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL),
 524         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL),
 525         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL),
 526         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL),
 527         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
 528
 529         STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 8, SPI1_K, _SPI1_SEL),
 530         STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
 531
 532         STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3),
 533
 534         STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 0, LTDC_PX, _PLL4_Q),
 535         STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 4, DSI_PX, _PLL4_Q),
 536         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 4, DSI_K, _DSI_SEL),
 537         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
 538         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
 539         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
 540
 541         STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
 542         STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5),
 543         STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
 544
 545         STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB2ENSETR, 5, ADC12, _HCLK2),
 546         STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 5, ADC12_K, _ADC12_SEL),
 547         STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
 548         STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
 549
 550         STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 11, HSEM, _UNKNOWN_SEL),
 551         STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 12, IPCC, _UNKNOWN_SEL),
 552
 553         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
 554         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
 555         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
 556         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL),
 557         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL),
 558         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL),
 559         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL),
 560         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL),
 561         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL),
 562         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL),
 563         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
 564
 565         STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
 566         STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 6, RNG1_K, _UNKNOWN_SEL),
 567
 568         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK_K, _ETH_SEL),
 569         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL),
 570         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL),
 571         STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK),
 572         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
 573         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
 574         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL),
 575         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL),
 576         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL),
 577
 578         STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
 579
 580         STM32MP1_CLK(RCC_BDCR, 20, RTC, _RTC_SEL),
 581 };
 582
 583 static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
 584 static const u8 i2c35_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
 585 static const u8 i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER};
 586 static const u8 uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
 587                                         _HSE_KER};
 588 static const u8 uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 589                                          _HSE_KER};
 590 static const u8 uart35_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 591                                          _HSE_KER};
 592 static const u8 uart78_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 593                                          _HSE_KER};
 594 static const u8 sdmmc12_parents[] = {_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER};
 595 static const u8 sdmmc3_parents[] = {_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER};
 596 static const u8 eth_parents[] = {_PLL4_P, _PLL3_Q};
 597 static const u8 qspi_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
 598 static const u8 fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
 599 static const u8 usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2};
 600 static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48};
 601 static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER};
 602 static const u8 dsi_parents[] = {_DSI_PHY, _PLL4_P};
 603 static const u8 adc_parents[] = {_PLL4_R, _CK_PER, _PLL3_Q};
 604 static const u8 spi_parents[] = {_PLL4_P, _PLL3_Q, _I2S_CKIN, _CK_PER,
 605                                  _PLL3_R};
 606 static const u8 rtc_parents[] = {_UNKNOWN_ID, _LSE, _LSI, _HSE};
 607
 608 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
 609         STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents),
 610         STM32MP1_CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents),
 611         STM32MP1_CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents),
 612         STM32MP1_CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents),
 613         STM32MP1_CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7,
 614                             uart24_parents),
 615         STM32MP1_CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7,
 616                             uart35_parents),
 617         STM32MP1_CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7,
 618                             uart78_parents),
 619         STM32MP1_CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7,
 620                             sdmmc12_parents),
 621         STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7,
 622                             sdmmc3_parents),
 623         STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents),
 624         STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents),
 625         STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents),
 626         STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents),
 627         STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
 628         STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
 629         STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents),
 630         STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x1, adc_parents),
 631         STM32MP1_CLK_PARENT(_SPI1_SEL, RCC_SPI2S1CKSELR, 0, 0x7, spi_parents),
 632         STM32MP1_CLK_PARENT(_RTC_SEL, RCC_BDCR, RCC_BDCR_RTCSRC_SHIFT,
 633                             (RCC_BDCR_RTCSRC_MASK >> RCC_BDCR_RTCSRC_SHIFT),
 634                             rtc_parents),
 635 };
 636
 637 #ifdef STM32MP1_CLOCK_TREE_INIT
 638 /* define characteristic of PLL according type */
 639 #define DIVN_MIN        24
 640 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
 641         [PLL_800] = {
 642                 .refclk_min = 4,
 643                 .refclk_max = 16,
 644                 .divn_max = 99,
 645                 },
 646         [PLL_1600] = {
 647                 .refclk_min = 8,
 648                 .refclk_max = 16,
 649                 .divn_max = 199,
 650                 },
 651 };
 652 #endif /* STM32MP1_CLOCK_TREE_INIT */
 653
 654 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = {
 655         STM32MP1_CLK_PLL(_PLL1, PLL_1600,
 656                          RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2,
 657                          RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR,
 658                          _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
 659         STM32MP1_CLK_PLL(_PLL2, PLL_1600,
 660                          RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2,
 661                          RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR,
 662                          _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
 663         STM32MP1_CLK_PLL(_PLL3, PLL_800,
 664                          RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2,
 665                          RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR,
 666                          _HSI, _HSE, _CSI, _UNKNOWN_ID),
 667         STM32MP1_CLK_PLL(_PLL4, PLL_800,
 668                          RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2,
 669                          RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR,
 670                          _HSI, _HSE, _CSI, _I2S_CKIN),
 671 };
 672
 673 /* Prescaler table lookups for clock computation */
 674 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */
 675 static const u8 stm32mp1_mcu_div[16] = {
 676         0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9
 677 };
 678
 679 /* div = /1 /2 /4 /8 /16 : same divider for pmu and apbx*/
 680 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div
 681 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div
 682 static const u8 stm32mp1_mpu_apbx_div[8] = {
 683         0, 1, 2, 3, 4, 4, 4, 4
 684 };
 685
 686 /* div = /1 /2 /3 /4 */
 687 static const u8 stm32mp1_axi_div[8] = {
 688         1, 2, 3, 4, 4, 4, 4, 4
 689 };
 690
 691 static const __maybe_unused
 692 char * const stm32mp1_clk_parent_name[_PARENT_NB] = {
 693         [_HSI] = "HSI",
 694         [_HSE] = "HSE",
 695         [_CSI] = "CSI",
 696         [_LSI] = "LSI",
 697         [_LSE] = "LSE",
 698         [_I2S_CKIN] = "I2S_CKIN",
 699         [_HSI_KER] = "HSI_KER",
 700         [_HSE_KER] = "HSE_KER",
 701         [_HSE_KER_DIV2] = "HSE_KER_DIV2",
 702         [_CSI_KER] = "CSI_KER",
 703         [_PLL1_P] = "PLL1_P",
 704         [_PLL1_Q] = "PLL1_Q",
 705         [_PLL1_R] = "PLL1_R",
 706         [_PLL2_P] = "PLL2_P",
 707         [_PLL2_Q] = "PLL2_Q",
 708         [_PLL2_R] = "PLL2_R",
 709         [_PLL3_P] = "PLL3_P",
 710         [_PLL3_Q] = "PLL3_Q",
 711         [_PLL3_R] = "PLL3_R",
 712         [_PLL4_P] = "PLL4_P",
 713         [_PLL4_Q] = "PLL4_Q",
 714         [_PLL4_R] = "PLL4_R",
 715         [_ACLK] = "ACLK",
 716         [_PCLK1] = "PCLK1",
 717         [_PCLK2] = "PCLK2",
 718         [_PCLK3] = "PCLK3",
 719         [_PCLK4] = "PCLK4",
 720         [_PCLK5] = "PCLK5",
 721         [_HCLK6] = "KCLK6",
 722         [_HCLK2] = "HCLK2",
 723         [_CK_PER] = "CK_PER",
 724         [_CK_MPU] = "CK_MPU",
 725         [_CK_MCU] = "CK_MCU",
 726         [_USB_PHY_48] = "USB_PHY_48",
 727         [_DSI_PHY] = "DSI_PHY_PLL",
 728 };
 729
 730 static const __maybe_unused
 731 char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
 732         [_I2C12_SEL] = "I2C12",
 733         [_I2C35_SEL] = "I2C35",
 734         [_I2C46_SEL] = "I2C46",
 735         [_UART6_SEL] = "UART6",
 736         [_UART24_SEL] = "UART24",
 737         [_UART35_SEL] = "UART35",
 738         [_UART78_SEL] = "UART78",
 739         [_SDMMC12_SEL] = "SDMMC12",
 740         [_SDMMC3_SEL] = "SDMMC3",
 741         [_ETH_SEL] = "ETH",
 742         [_QSPI_SEL] = "QSPI",
 743         [_FMC_SEL] = "FMC",
 744         [_USBPHY_SEL] = "USBPHY",
 745         [_USBO_SEL] = "USBO",
 746         [_STGEN_SEL] = "STGEN",
 747         [_DSI_SEL] = "DSI",
 748         [_ADC12_SEL] = "ADC12",
 749         [_SPI1_SEL] = "SPI1",
 750         [_RTC_SEL] = "RTC",
 751 };
 752
 753 static const struct stm32mp1_clk_data stm32mp1_data = {
 754         .gate = stm32mp1_clk_gate,
 755         .sel = stm32mp1_clk_sel,
 756         .pll = stm32mp1_clk_pll,
 757         .nb_gate = ARRAY_SIZE(stm32mp1_clk_gate),
 758 };
 759
 760 static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx)
 761 {
 762         if (idx >= NB_OSC) {
 763                 debug("%s: clk id %d not found\n", __func__, idx);
 764                 return 0;
 765         }
 766
 767         return priv->osc[idx];
 768 }
 769
 770 static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id)
 771 {
 772         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 773         int i, nb_clks = priv->data->nb_gate;
 774
 775         for (i = 0; i < nb_clks; i++) {
 776                 if (gate[i].index == id)
 777                         break;
 778         }
 779
 780         if (i == nb_clks) {
 781                 printf("%s: clk id %d not found\n", __func__, (u32)id);
 782                 return -EINVAL;
 783         }
 784
 785         return i;
 786 }
 787
 788 static int stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv,
 789                                 int i)
 790 {
 791         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 792
 793         if (gate[i].sel > _PARENT_SEL_NB) {
 794                 printf("%s: parents for clk id %d not found\n",
 795                        __func__, i);
 796                 return -EINVAL;
 797         }
 798
 799         return gate[i].sel;
 800 }
 801
 802 static int stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv *priv,
 803                                          int i)
 804 {
 805         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 806
 807         if (gate[i].fixed == _UNKNOWN_ID)
 808                 return -ENOENT;
 809
 810         return gate[i].fixed;
 811 }
 812
 813 static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv,
 814                                    unsigned long id)
 815 {
 816         const struct stm32mp1_clk_sel *sel = priv->data->sel;
 817         int i;
 818         int s, p;
 819         unsigned int idx;
 820
 821         for (idx = 0; idx < ARRAY_SIZE(stm32mp1_clks); idx++)
 822                 if (stm32mp1_clks[idx][0] == id)
 823                         return stm32mp1_clks[idx][1];
 824
 825         i = stm32mp1_clk_get_id(priv, id);
 826         if (i < 0)
 827                 return i;
 828
 829         p = stm32mp1_clk_get_fixed_parent(priv, i);
 830         if (p >= 0 && p < _PARENT_NB)
 831                 return p;
 832
 833         s = stm32mp1_clk_get_sel(priv, i);
 834         if (s < 0)
 835                 return s;
 836
 837         p = (readl(priv->base + sel[s].offset) >> sel[s].src) & sel[s].msk;
 838
 839         if (p < sel[s].nb_parent) {
 840 #ifdef DEBUG
 841                 debug("%s: %s clock is the parent %s of clk id %d\n", __func__,
 842                       stm32mp1_clk_parent_name[sel[s].parent[p]],
 843                       stm32mp1_clk_parent_sel_name[s],
 844                       (u32)id);
 845 #endif
 846                 return sel[s].parent[p];
 847         }
 848
 849         pr_err("%s: no parents defined for clk id %d\n",
 850                __func__, (u32)id);
 851
 852         return -EINVAL;
 853 }
 854
 855 static ulong  pll_get_fref_ck(struct stm32mp1_clk_priv *priv,
 856                               int pll_id)
 857 {
 858         const struct stm32mp1_clk_pll *pll = priv->data->pll;
 859         u32 selr;
 860         int src;
 861         ulong refclk;
 862
 863         /* Get current refclk */
 864         selr = readl(priv->base + pll[pll_id].rckxselr);
 865         src = selr & RCC_SELR_SRC_MASK;
 866
 867         refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]);
 868
 869         return refclk;
 870 }
 871
 872 /*
 873  * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL
 874  * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1)
 875  * - PLL3 & PLL4 => return VCO     with Fpll_y_ck = FVCO / (DIVy + 1)
 876  * => in all the case Fpll_y_ck = pll_get_fvco() / (DIVy + 1)
 877  */
 878 static ulong pll_get_fvco(struct stm32mp1_clk_priv *priv,
 879                           int pll_id)
 880 {
 881         const struct stm32mp1_clk_pll *pll = priv->data->pll;
 882         int divm, divn;
 883         ulong refclk, fvco;
 884         u32 cfgr1, fracr;
 885
 886         cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1);
 887         fracr = readl(priv->base + pll[pll_id].pllxfracr);
 888
 889         divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
 890         divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
 891
 892         refclk = pll_get_fref_ck(priv, pll_id);
 893
 894         /* with FRACV :
 895          *   Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1)
 896          * without FRACV
 897          *   Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1)
 898          */
 899         if (fracr & RCC_PLLNFRACR_FRACLE) {
 900                 u32 fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK)
 901                             >> RCC_PLLNFRACR_FRACV_SHIFT;
 902                 fvco = (ulong)lldiv((unsigned long long)refclk *
 903                                      (((divn + 1) << 13) + fracv),
 904                                      ((unsigned long long)(divm + 1)) << 13);
 905         } else {
 906                 fvco = (ulong)(refclk * (divn + 1) / (divm + 1));
 907         }
 908
 909         return fvco;
 910 }
 911
 912 static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
 913                                     int pll_id, int div_id)
 914 {
 915         const struct stm32mp1_clk_pll *pll = priv->data->pll;
 916         int divy;
 917         ulong dfout;
 918         u32 cfgr2;
 919
 920         if (div_id >= _DIV_NB)
 921                 return 0;
 922
 923         cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2);
 924         divy = (cfgr2 >> RCC_PLLNCFGR2_SHIFT(div_id)) & RCC_PLLNCFGR2_DIVX_MASK;
 925
 926         dfout = pll_get_fvco(priv, pll_id) / (divy + 1);
 927
 928         return dfout;
 929 }
 930
 931 static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
 932 {
 933         u32 reg;
 934         ulong clock = 0;
 935
 936         switch (p) {
 937         case _CK_MPU:
 938         /* MPU sub system */
 939                 reg = readl(priv->base + RCC_MPCKSELR);
 940                 switch (reg & RCC_SELR_SRC_MASK) {
 941                 case RCC_MPCKSELR_HSI:
 942                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
 943                         break;
 944                 case RCC_MPCKSELR_HSE:
 945                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
 946                         break;
 947                 case RCC_MPCKSELR_PLL:
 948                 case RCC_MPCKSELR_PLL_MPUDIV:
 949                         clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P);
 950                         if (p == RCC_MPCKSELR_PLL_MPUDIV) {
 951                                 reg = readl(priv->base + RCC_MPCKDIVR);
 952                                 clock /= stm32mp1_mpu_div[reg &
 953                                                           RCC_MPUDIV_MASK];
 954                         }
 955                         break;
 956                 }
 957                 break;
 958         /* AXI sub system */
 959         case _ACLK:
 960         case _HCLK2:
 961         case _HCLK6:
 962         case _PCLK4:
 963         case _PCLK5:
 964                 reg = readl(priv->base + RCC_ASSCKSELR);
 965                 switch (reg & RCC_SELR_SRC_MASK) {
 966                 case RCC_ASSCKSELR_HSI:
 967                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
 968                         break;
 969                 case RCC_ASSCKSELR_HSE:
 970                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
 971                         break;
 972                 case RCC_ASSCKSELR_PLL:
 973                         clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P);
 974                         break;
 975                 }
 976
 977                 /* System clock divider */
 978                 reg = readl(priv->base + RCC_AXIDIVR);
 979                 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK];
 980
 981                 switch (p) {
 982                 case _PCLK4:
 983                         reg = readl(priv->base + RCC_APB4DIVR);
 984                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
 985                         break;
 986                 case _PCLK5:
 987                         reg = readl(priv->base + RCC_APB5DIVR);
 988                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
 989                         break;
 990                 default:
 991                         break;
 992                 }
 993                 break;
 994         /* MCU sub system */
 995         case _CK_MCU:
 996         case _PCLK1:
 997         case _PCLK2:
 998         case _PCLK3:
 999                 reg = readl(priv->base + RCC_MSSCKSELR);
1000                 switch (reg & RCC_SELR_SRC_MASK) {
1001                 case RCC_MSSCKSELR_HSI:
1002                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
1003                         break;
1004                 case RCC_MSSCKSELR_HSE:
1005                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
1006                         break;
1007                 case RCC_MSSCKSELR_CSI:
1008                         clock = stm32mp1_clk_get_fixed(priv, _CSI);
1009                         break;
1010                 case RCC_MSSCKSELR_PLL:
1011                         clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_P);
1012                         break;
1013                 }
1014
1015                 /* MCU clock divider */
1016                 reg = readl(priv->base + RCC_MCUDIVR);
1017                 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK];
1018
1019                 switch (p) {
1020                 case _PCLK1:
1021                         reg = readl(priv->base + RCC_APB1DIVR);
1022                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1023                         break;
1024                 case _PCLK2:
1025                         reg = readl(priv->base + RCC_APB2DIVR);
1026                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1027                         break;
1028                 case _PCLK3:
1029                         reg = readl(priv->base + RCC_APB3DIVR);
1030                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1031                         break;
1032                 case _CK_MCU:
1033                 default:
1034                         break;
1035                 }
1036                 break;
1037         case _CK_PER:
1038                 reg = readl(priv->base + RCC_CPERCKSELR);
1039                 switch (reg & RCC_SELR_SRC_MASK) {
1040                 case RCC_CPERCKSELR_HSI:
1041                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
1042                         break;
1043                 case RCC_CPERCKSELR_HSE:
1044                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
1045                         break;
1046                 case RCC_CPERCKSELR_CSI:
1047                         clock = stm32mp1_clk_get_fixed(priv, _CSI);
1048                         break;
1049                 }
1050                 break;
1051         case _HSI:
1052         case _HSI_KER:
1053                 clock = stm32mp1_clk_get_fixed(priv, _HSI);
1054                 break;
1055         case _CSI:
1056         case _CSI_KER:
1057                 clock = stm32mp1_clk_get_fixed(priv, _CSI);
1058                 break;
1059         case _HSE:
1060         case _HSE_KER:
1061         case _HSE_KER_DIV2:
1062                 clock = stm32mp1_clk_get_fixed(priv, _HSE);
1063                 if (p == _HSE_KER_DIV2)
1064                         clock >>= 1;
1065                 break;
1066         case _LSI:
1067                 clock = stm32mp1_clk_get_fixed(priv, _LSI);
1068                 break;
1069         case _LSE:
1070                 clock = stm32mp1_clk_get_fixed(priv, _LSE);
1071                 break;
1072         /* PLL */
1073         case _PLL1_P:
1074         case _PLL1_Q:
1075         case _PLL1_R:
1076                 clock = stm32mp1_read_pll_freq(priv, _PLL1, p - _PLL1_P);
1077                 break;
1078         case _PLL2_P:
1079         case _PLL2_Q:
1080         case _PLL2_R:
1081                 clock = stm32mp1_read_pll_freq(priv, _PLL2, p - _PLL2_P);
1082                 break;
1083         case _PLL3_P:
1084         case _PLL3_Q:
1085         case _PLL3_R:
1086                 clock = stm32mp1_read_pll_freq(priv, _PLL3, p - _PLL3_P);
1087                 break;
1088         case _PLL4_P:
1089         case _PLL4_Q:
1090         case _PLL4_R:
1091                 clock = stm32mp1_read_pll_freq(priv, _PLL4, p - _PLL4_P);
1092                 break;
1093         /* other */
1094         case _USB_PHY_48:
1095                 clock = 48000000;
1096                 break;
1097         case _DSI_PHY:
1098         {
1099                 struct clk clk;
1100                 struct udevice *dev = NULL;
1101
1102                 if (!uclass_get_device_by_name(UCLASS_CLK, "ck_dsi_phy",
1103                                                &dev)) {
1104                         if (clk_request(dev, &clk)) {
1105                                 pr_err("ck_dsi_phy request");
1106                         } else {
1107                                 clk.id = 0;
1108                                 clock = clk_get_rate(&clk);
1109                         }
1110                 }
1111                 break;
1112         }
1113         default:
1114                 break;
1115         }
1116
1117         debug("%s(%d) clock = %lx : %ld kHz\n",
1118               __func__, p, clock, clock / 1000);
1119
1120         return clock;
1121 }
1122
1123 static int stm32mp1_clk_enable(struct clk *clk)
1124 {
1125         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1126         const struct stm32mp1_clk_gate *gate = priv->data->gate;
1127         int i = stm32mp1_clk_get_id(priv, clk->id);
1128
1129         if (i < 0)
1130                 return i;
1131
1132         if (gate[i].set_clr)
1133                 writel(BIT(gate[i].bit), priv->base + gate[i].offset);
1134         else
1135                 setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1136
1137         debug("%s: id clock %d has been enabled\n", __func__, (u32)clk->id);
1138
1139         return 0;
1140 }
1141
1142 static int stm32mp1_clk_disable(struct clk *clk)
1143 {
1144         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1145         const struct stm32mp1_clk_gate *gate = priv->data->gate;
1146         int i = stm32mp1_clk_get_id(priv, clk->id);
1147
1148         if (i < 0)
1149                 return i;
1150
1151         if (gate[i].set_clr)
1152                 writel(BIT(gate[i].bit),
1153                        priv->base + gate[i].offset
1154                        + RCC_MP_ENCLRR_OFFSET);
1155         else
1156                 clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1157
1158         debug("%s: id clock %d has been disabled\n", __func__, (u32)clk->id);
1159
1160         return 0;
1161 }
1162
1163 static ulong stm32mp1_clk_get_rate(struct clk *clk)
1164 {
1165         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1166         int p = stm32mp1_clk_get_parent(priv, clk->id);
1167         ulong rate;
1168
1169         if (p < 0)
1170                 return 0;
1171
1172         rate = stm32mp1_clk_get(priv, p);
1173
1174 #ifdef DEBUG
1175         debug("%s: computed rate for id clock %d is %d (parent is %s)\n",
1176               __func__, (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]);
1177 #endif
1178         return rate;
1179 }
1180
1181 #ifdef STM32MP1_CLOCK_TREE_INIT
1182 static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset,
1183                                 u32 mask_on)
1184 {
1185         u32 address = rcc + offset;
1186
1187         if (enable)
1188                 setbits_le32(address, mask_on);
1189         else
1190                 clrbits_le32(address, mask_on);
1191 }
1192
1193 static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on)
1194 {
1195         writel(mask_on, rcc + (enable ? RCC_OCENSETR : RCC_OCENCLRR));
1196 }
1197
1198 static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset,
1199                              u32 mask_rdy)
1200 {
1201         u32 mask_test = 0;
1202         u32 address = rcc + offset;
1203         u32 val;
1204         int ret;
1205
1206         if (enable)
1207                 mask_test = mask_rdy;
1208
1209         ret = readl_poll_timeout(address, val,
1210                                  (val & mask_rdy) == mask_test,
1211                                  TIMEOUT_1S);
1212
1213         if (ret)
1214                 pr_err("OSC %x @ %x timeout for enable=%d : 0x%x\n",
1215                        mask_rdy, address, enable, readl(address));
1216
1217         return ret;
1218 }
1219
1220 static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int digbyp,
1221                                 int lsedrv)
1222 {
1223         u32 value;
1224
1225         if (digbyp)
1226                 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_DIGBYP);
1227
1228         if (bypass || digbyp)
1229                 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP);
1230
1231         /*
1232          * warning: not recommended to switch directly from "high drive"
1233          * to "medium low drive", and vice-versa.
1234          */
1235         value = (readl(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK)
1236                 >> RCC_BDCR_LSEDRV_SHIFT;
1237
1238         while (value != lsedrv) {
1239                 if (value > lsedrv)
1240                         value--;
1241                 else
1242                         value++;
1243
1244                 clrsetbits_le32(rcc + RCC_BDCR,
1245                                 RCC_BDCR_LSEDRV_MASK,
1246                                 value << RCC_BDCR_LSEDRV_SHIFT);
1247         }
1248
1249         stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON);
1250 }
1251
1252 static void stm32mp1_lse_wait(fdt_addr_t rcc)
1253 {
1254         stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY);
1255 }
1256
1257 static void stm32mp1_lsi_set(fdt_addr_t rcc, int enable)
1258 {
1259         stm32mp1_ls_osc_set(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSION);
1260         stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY);
1261 }
1262
1263 static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int digbyp, int css)
1264 {
1265         if (digbyp)
1266                 writel(RCC_OCENR_DIGBYP, rcc + RCC_OCENSETR);
1267         if (bypass || digbyp)
1268                 writel(RCC_OCENR_HSEBYP, rcc + RCC_OCENSETR);
1269
1270         stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON);
1271         stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY);
1272
1273         if (css)
1274                 writel(RCC_OCENR_HSECSSON, rcc + RCC_OCENSETR);
1275 }
1276
1277 static void stm32mp1_csi_set(fdt_addr_t rcc, int enable)
1278 {
1279         stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_CSION);
1280         stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY);
1281 }
1282
1283 static void stm32mp1_hsi_set(fdt_addr_t rcc, int enable)
1284 {
1285         stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_HSION);
1286         stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_HSIRDY);
1287 }
1288
1289 static int stm32mp1_set_hsidiv(fdt_addr_t rcc, u8 hsidiv)
1290 {
1291         u32 address = rcc + RCC_OCRDYR;
1292         u32 val;
1293         int ret;
1294
1295         clrsetbits_le32(rcc + RCC_HSICFGR,
1296                         RCC_HSICFGR_HSIDIV_MASK,
1297                         RCC_HSICFGR_HSIDIV_MASK & hsidiv);
1298
1299         ret = readl_poll_timeout(address, val,
1300                                  val & RCC_OCRDYR_HSIDIVRDY,
1301                                  TIMEOUT_200MS);
1302         if (ret)
1303                 pr_err("HSIDIV failed @ 0x%x: 0x%x\n",
1304                        address, readl(address));
1305
1306         return ret;
1307 }
1308
1309 static int stm32mp1_hsidiv(fdt_addr_t rcc, ulong hsifreq)
1310 {
1311         u8 hsidiv;
1312         u32 hsidivfreq = MAX_HSI_HZ;
1313
1314         for (hsidiv = 0; hsidiv < 4; hsidiv++,
1315              hsidivfreq = hsidivfreq / 2)
1316                 if (hsidivfreq == hsifreq)
1317                         break;
1318
1319         if (hsidiv == 4) {
1320                 pr_err("clk-hsi frequency invalid");
1321                 return -1;
1322         }
1323
1324         if (hsidiv > 0)
1325                 return stm32mp1_set_hsidiv(rcc, hsidiv);
1326
1327         return 0;
1328 }
1329
1330 static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id)
1331 {
1332         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1333
1334         clrsetbits_le32(priv->base + pll[pll_id].pllxcr,
1335                         RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN |
1336                         RCC_PLLNCR_DIVREN,
1337                         RCC_PLLNCR_PLLON);
1338 }
1339
1340 static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output)
1341 {
1342         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1343         u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1344         u32 val;
1345         int ret;
1346
1347         ret = readl_poll_timeout(pllxcr, val, val & RCC_PLLNCR_PLLRDY,
1348                                  TIMEOUT_200MS);
1349
1350         if (ret) {
1351                 pr_err("PLL%d start failed @ 0x%x: 0x%x\n",
1352                        pll_id, pllxcr, readl(pllxcr));
1353                 return ret;
1354         }
1355
1356         /* start the requested output */
1357         setbits_le32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT);
1358
1359         return 0;
1360 }
1361
1362 static int pll_stop(struct stm32mp1_clk_priv *priv, int pll_id)
1363 {
1364         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1365         u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1366         u32 val;
1367
1368         /* stop all output */
1369         clrbits_le32(pllxcr,
1370                      RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN);
1371
1372         /* stop PLL */
1373         clrbits_le32(pllxcr, RCC_PLLNCR_PLLON);
1374
1375         /* wait PLL stopped */
1376         return readl_poll_timeout(pllxcr, val, (val & RCC_PLLNCR_PLLRDY) == 0,
1377                                   TIMEOUT_200MS);
1378 }
1379
1380 static void pll_config_output(struct stm32mp1_clk_priv *priv,
1381                               int pll_id, u32 *pllcfg)
1382 {
1383         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1384         fdt_addr_t rcc = priv->base;
1385         u32 value;
1386
1387         value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT)
1388                 & RCC_PLLNCFGR2_DIVP_MASK;
1389         value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT)
1390                  & RCC_PLLNCFGR2_DIVQ_MASK;
1391         value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT)
1392                  & RCC_PLLNCFGR2_DIVR_MASK;
1393         writel(value, rcc + pll[pll_id].pllxcfgr2);
1394 }
1395
1396 static int pll_config(struct stm32mp1_clk_priv *priv, int pll_id,
1397                       u32 *pllcfg, u32 fracv)
1398 {
1399         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1400         fdt_addr_t rcc = priv->base;
1401         enum stm32mp1_plltype type = pll[pll_id].plltype;
1402         int src;
1403         ulong refclk;
1404         u8 ifrge = 0;
1405         u32 value;
1406
1407         src = readl(priv->base + pll[pll_id].rckxselr) & RCC_SELR_SRC_MASK;
1408
1409         refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]) /
1410                  (pllcfg[PLLCFG_M] + 1);
1411
1412         if (refclk < (stm32mp1_pll[type].refclk_min * 1000000) ||
1413             refclk > (stm32mp1_pll[type].refclk_max * 1000000)) {
1414                 debug("invalid refclk = %x\n", (u32)refclk);
1415                 return -EINVAL;
1416         }
1417         if (type == PLL_800 && refclk >= 8000000)
1418                 ifrge = 1;
1419
1420         value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT)
1421                  & RCC_PLLNCFGR1_DIVN_MASK;
1422         value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT)
1423                  & RCC_PLLNCFGR1_DIVM_MASK;
1424         value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT)
1425                  & RCC_PLLNCFGR1_IFRGE_MASK;
1426         writel(value, rcc + pll[pll_id].pllxcfgr1);
1427
1428         /* fractional configuration: load sigma-delta modulator (SDM) */
1429
1430         /* Write into FRACV the new fractional value , and FRACLE to 0 */
1431         writel(fracv << RCC_PLLNFRACR_FRACV_SHIFT,
1432                rcc + pll[pll_id].pllxfracr);
1433
1434         /* Write FRACLE to 1 : FRACV value is loaded into the SDM */
1435         setbits_le32(rcc + pll[pll_id].pllxfracr,
1436                      RCC_PLLNFRACR_FRACLE);
1437
1438         pll_config_output(priv, pll_id, pllcfg);
1439
1440         return 0;
1441 }
1442
1443 static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg)
1444 {
1445         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1446         u32 pllxcsg;
1447
1448         pllxcsg = ((csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) &
1449                     RCC_PLLNCSGR_MOD_PER_MASK) |
1450                   ((csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) &
1451                     RCC_PLLNCSGR_INC_STEP_MASK) |
1452                   ((csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) &
1453                     RCC_PLLNCSGR_SSCG_MODE_MASK);
1454
1455         writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr);
1456
1457         setbits_le32(priv->base + pll[pll_id].pllxcr, RCC_PLLNCR_SSCG_CTRL);
1458 }
1459
1460 static  __maybe_unused int pll_set_rate(struct udevice *dev,
1461                                         int pll_id,
1462                                         int div_id,
1463                                         unsigned long clk_rate)
1464 {
1465         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1466         unsigned int pllcfg[PLLCFG_NB];
1467         ofnode plloff;
1468         char name[12];
1469         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1470         enum stm32mp1_plltype type = pll[pll_id].plltype;
1471         int divm, divn, divy;
1472         int ret;
1473         ulong fck_ref;
1474         u32 fracv;
1475         u64 value;
1476
1477         if (div_id > _DIV_NB)
1478                 return -EINVAL;
1479
1480         sprintf(name, "st,pll@%d", pll_id);
1481         plloff = dev_read_subnode(dev, name);
1482         if (!ofnode_valid(plloff))
1483                 return -FDT_ERR_NOTFOUND;
1484
1485         ret = ofnode_read_u32_array(plloff, "cfg",
1486                                     pllcfg, PLLCFG_NB);
1487         if (ret < 0)
1488                 return -FDT_ERR_NOTFOUND;
1489
1490         fck_ref = pll_get_fref_ck(priv, pll_id);
1491
1492         divm = pllcfg[PLLCFG_M];
1493         /* select output divider = 0: for _DIV_P, 1:_DIV_Q 2:_DIV_R */
1494         divy = pllcfg[PLLCFG_P + div_id];
1495
1496         /* For: PLL1 & PLL2 => VCO is * 2 but ck_pll_y is also / 2
1497          * So same final result than PLL2 et 4
1498          * with FRACV
1499          * Fck_pll_y = Fck_ref * ((DIVN + 1) + FRACV / 2^13)
1500          *             / (DIVy + 1) * (DIVM + 1)
1501          * value = (DIVN + 1) * 2^13 + FRACV / 2^13
1502          *       = Fck_pll_y (DIVy + 1) * (DIVM + 1) * 2^13 / Fck_ref
1503          */
1504         value = ((u64)clk_rate * (divy + 1) * (divm + 1)) << 13;
1505         value = lldiv(value, fck_ref);
1506
1507         divn = (value >> 13) - 1;
1508         if (divn < DIVN_MIN ||
1509             divn > stm32mp1_pll[type].divn_max) {
1510                 pr_err("divn invalid = %d", divn);
1511                 return -EINVAL;
1512         }
1513         fracv = value - ((divn + 1) << 13);
1514         pllcfg[PLLCFG_N] = divn;
1515
1516         /* reconfigure PLL */
1517         pll_stop(priv, pll_id);
1518         pll_config(priv, pll_id, pllcfg, fracv);
1519         pll_start(priv, pll_id);
1520         pll_output(priv, pll_id, pllcfg[PLLCFG_O]);
1521
1522         return 0;
1523 }
1524
1525 static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc)
1526 {
1527         u32 address = priv->base + (clksrc >> 4);
1528         u32 val;
1529         int ret;
1530
1531         clrsetbits_le32(address, RCC_SELR_SRC_MASK, clksrc & RCC_SELR_SRC_MASK);
1532         ret = readl_poll_timeout(address, val, val & RCC_SELR_SRCRDY,
1533                                  TIMEOUT_200MS);
1534         if (ret)
1535                 pr_err("CLKSRC %x start failed @ 0x%x: 0x%x\n",
1536                        clksrc, address, readl(address));
1537
1538         return ret;
1539 }
1540
1541 static void stgen_config(struct stm32mp1_clk_priv *priv)
1542 {
1543         int p;
1544         u32 stgenc, cntfid0;
1545         ulong rate;
1546
1547         stgenc = STM32_STGEN_BASE;
1548         cntfid0 = readl(stgenc + STGENC_CNTFID0);
1549         p = stm32mp1_clk_get_parent(priv, STGEN_K);
1550         rate = stm32mp1_clk_get(priv, p);
1551
1552         if (cntfid0 != rate) {
1553                 u64 counter;
1554
1555                 pr_debug("System Generic Counter (STGEN) update\n");
1556                 clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1557                 counter = (u64)readl(stgenc + STGENC_CNTCVL);
1558                 counter |= ((u64)(readl(stgenc + STGENC_CNTCVU))) << 32;
1559                 counter = lldiv(counter * (u64)rate, cntfid0);
1560                 writel((u32)counter, stgenc + STGENC_CNTCVL);
1561                 writel((u32)(counter >> 32), stgenc + STGENC_CNTCVU);
1562                 writel(rate, stgenc + STGENC_CNTFID0);
1563                 setbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1564
1565                 __asm__ volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (rate));
1566
1567                 /* need to update gd->arch.timer_rate_hz with new frequency */
1568                 timer_init();
1569         }
1570 }
1571
1572 static int set_clkdiv(unsigned int clkdiv, u32 address)
1573 {
1574         u32 val;
1575         int ret;
1576
1577         clrsetbits_le32(address, RCC_DIVR_DIV_MASK, clkdiv & RCC_DIVR_DIV_MASK);
1578         ret = readl_poll_timeout(address, val, val & RCC_DIVR_DIVRDY,
1579                                  TIMEOUT_200MS);
1580         if (ret)
1581                 pr_err("CLKDIV %x start failed @ 0x%x: 0x%x\n",
1582                        clkdiv, address, readl(address));
1583
1584         return ret;
1585 }
1586
1587 static void stm32mp1_mco_csg(struct stm32mp1_clk_priv *priv,
1588                              u32 clksrc, u32 clkdiv)
1589 {
1590         u32 address = priv->base + (clksrc >> 4);
1591
1592         /*
1593          * binding clksrc : bit15-4 offset
1594          *                  bit3:   disable
1595          *                  bit2-0: MCOSEL[2:0]
1596          */
1597         if (clksrc & 0x8) {
1598                 clrbits_le32(address, RCC_MCOCFG_MCOON);
1599         } else {
1600                 clrsetbits_le32(address,
1601                                 RCC_MCOCFG_MCOSRC_MASK,
1602                                 clksrc & RCC_MCOCFG_MCOSRC_MASK);
1603                 clrsetbits_le32(address,
1604                                 RCC_MCOCFG_MCODIV_MASK,
1605                                 clkdiv << RCC_MCOCFG_MCODIV_SHIFT);
1606                 setbits_le32(address, RCC_MCOCFG_MCOON);
1607         }
1608 }
1609
1610 static void set_rtcsrc(struct stm32mp1_clk_priv *priv,
1611                        unsigned int clksrc,
1612                        int lse_css)
1613 {
1614         u32 address = priv->base + RCC_BDCR;
1615
1616         if (readl(address) & RCC_BDCR_RTCCKEN)
1617                 goto skip_rtc;
1618
1619         if (clksrc == CLK_RTC_DISABLED)
1620                 goto skip_rtc;
1621
1622         clrsetbits_le32(address,
1623                         RCC_BDCR_RTCSRC_MASK,
1624                         clksrc << RCC_BDCR_RTCSRC_SHIFT);
1625
1626         setbits_le32(address, RCC_BDCR_RTCCKEN);
1627
1628 skip_rtc:
1629         if (lse_css)
1630                 setbits_le32(address, RCC_BDCR_LSECSSON);
1631 }
1632
1633 static void pkcs_config(struct stm32mp1_clk_priv *priv, u32 pkcs)
1634 {
1635         u32 address = priv->base + ((pkcs >> 4) & 0xFFF);
1636         u32 value = pkcs & 0xF;
1637         u32 mask = 0xF;
1638
1639         if (pkcs & BIT(31)) {
1640                 mask <<= 4;
1641                 value <<= 4;
1642         }
1643         clrsetbits_le32(address, mask, value);
1644 }
1645
1646 static int stm32mp1_clktree(struct udevice *dev)
1647 {
1648         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1649         fdt_addr_t rcc = priv->base;
1650         unsigned int clksrc[CLKSRC_NB];
1651         unsigned int clkdiv[CLKDIV_NB];
1652         unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
1653         ofnode plloff[_PLL_NB];
1654         int ret;
1655         int i, len;
1656         int lse_css = 0;
1657         const u32 *pkcs_cell;
1658
1659         /* check mandatory field */
1660         ret = dev_read_u32_array(dev, "st,clksrc", clksrc, CLKSRC_NB);
1661         if (ret < 0) {
1662                 debug("field st,clksrc invalid: error %d\n", ret);
1663                 return -FDT_ERR_NOTFOUND;
1664         }
1665
1666         ret = dev_read_u32_array(dev, "st,clkdiv", clkdiv, CLKDIV_NB);
1667         if (ret < 0) {
1668                 debug("field st,clkdiv invalid: error %d\n", ret);
1669                 return -FDT_ERR_NOTFOUND;
1670         }
1671
1672         /* check mandatory field in each pll */
1673         for (i = 0; i < _PLL_NB; i++) {
1674                 char name[12];
1675
1676                 sprintf(name, "st,pll@%d", i);
1677                 plloff[i] = dev_read_subnode(dev, name);
1678                 if (!ofnode_valid(plloff[i]))
1679                         continue;
1680                 ret = ofnode_read_u32_array(plloff[i], "cfg",
1681                                             pllcfg[i], PLLCFG_NB);
1682                 if (ret < 0) {
1683                         debug("field cfg invalid: error %d\n", ret);
1684                         return -FDT_ERR_NOTFOUND;
1685                 }
1686         }
1687
1688         debug("configuration MCO\n");
1689         stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]);
1690         stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]);
1691
1692         debug("switch ON osillator\n");
1693         /*
1694          * switch ON oscillator found in device-tree,
1695          * HSI already ON after bootrom
1696          */
1697         if (priv->osc[_LSI])
1698                 stm32mp1_lsi_set(rcc, 1);
1699
1700         if (priv->osc[_LSE]) {
1701                 int bypass, digbyp, lsedrv;
1702                 struct udevice *dev = priv->osc_dev[_LSE];
1703
1704                 bypass = dev_read_bool(dev, "st,bypass");
1705                 digbyp = dev_read_bool(dev, "st,digbypass");
1706                 lse_css = dev_read_bool(dev, "st,css");
1707                 lsedrv = dev_read_u32_default(dev, "st,drive",
1708                                               LSEDRV_MEDIUM_HIGH);
1709
1710                 stm32mp1_lse_enable(rcc, bypass, digbyp, lsedrv);
1711         }
1712
1713         if (priv->osc[_HSE]) {
1714                 int bypass, digbyp, css;
1715                 struct udevice *dev = priv->osc_dev[_HSE];
1716
1717                 bypass = dev_read_bool(dev, "st,bypass");
1718                 digbyp = dev_read_bool(dev, "st,digbypass");
1719                 css = dev_read_bool(dev, "st,css");
1720
1721                 stm32mp1_hse_enable(rcc, bypass, digbyp, css);
1722         }
1723         /* CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR)
1724          * => switch on CSI even if node is not present in device tree
1725          */
1726         stm32mp1_csi_set(rcc, 1);
1727
1728         /* come back to HSI */
1729         debug("come back to HSI\n");
1730         set_clksrc(priv, CLK_MPU_HSI);
1731         set_clksrc(priv, CLK_AXI_HSI);
1732         set_clksrc(priv, CLK_MCU_HSI);
1733
1734         debug("pll stop\n");
1735         for (i = 0; i < _PLL_NB; i++)
1736                 pll_stop(priv, i);
1737
1738         /* configure HSIDIV */
1739         debug("configure HSIDIV\n");
1740         if (priv->osc[_HSI]) {
1741                 stm32mp1_hsidiv(rcc, priv->osc[_HSI]);
1742                 stgen_config(priv);
1743         }
1744
1745         /* select DIV */
1746         debug("select DIV\n");
1747         /* no ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */
1748         writel(clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK, rcc + RCC_MPCKDIVR);
1749         set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR);
1750         set_clkdiv(clkdiv[CLKDIV_APB4], rcc + RCC_APB4DIVR);
1751         set_clkdiv(clkdiv[CLKDIV_APB5], rcc + RCC_APB5DIVR);
1752         set_clkdiv(clkdiv[CLKDIV_MCU], rcc + RCC_MCUDIVR);
1753         set_clkdiv(clkdiv[CLKDIV_APB1], rcc + RCC_APB1DIVR);
1754         set_clkdiv(clkdiv[CLKDIV_APB2], rcc + RCC_APB2DIVR);
1755         set_clkdiv(clkdiv[CLKDIV_APB3], rcc + RCC_APB3DIVR);
1756
1757         /* no ready bit for RTC */
1758         writel(clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK, rcc + RCC_RTCDIVR);
1759
1760         /* configure PLLs source */
1761         debug("configure PLLs source\n");
1762         set_clksrc(priv, clksrc[CLKSRC_PLL12]);
1763         set_clksrc(priv, clksrc[CLKSRC_PLL3]);
1764         set_clksrc(priv, clksrc[CLKSRC_PLL4]);
1765
1766         /* configure and start PLLs */
1767         debug("configure PLLs\n");
1768         for (i = 0; i < _PLL_NB; i++) {
1769                 u32 fracv;
1770                 u32 csg[PLLCSG_NB];
1771
1772                 debug("configure PLL %d @ %d\n", i,
1773                       ofnode_to_offset(plloff[i]));
1774                 if (!ofnode_valid(plloff[i]))
1775                         continue;
1776
1777                 fracv = ofnode_read_u32_default(plloff[i], "frac", 0);
1778                 pll_config(priv, i, pllcfg[i], fracv);
1779                 ret = ofnode_read_u32_array(plloff[i], "csg", csg, PLLCSG_NB);
1780                 if (!ret) {
1781                         pll_csg(priv, i, csg);
1782                 } else if (ret != -FDT_ERR_NOTFOUND) {
1783                         debug("invalid csg node for pll@%d res=%d\n", i, ret);
1784                         return ret;
1785                 }
1786                 pll_start(priv, i);
1787         }
1788
1789         /* wait and start PLLs ouptut when ready */
1790         for (i = 0; i < _PLL_NB; i++) {
1791                 if (!ofnode_valid(plloff[i]))
1792                         continue;
1793                 debug("output PLL %d\n", i);
1794                 pll_output(priv, i, pllcfg[i][PLLCFG_O]);
1795         }
1796
1797         /* wait LSE ready before to use it */
1798         if (priv->osc[_LSE])
1799                 stm32mp1_lse_wait(rcc);
1800
1801         /* configure with expected clock source */
1802         debug("CLKSRC\n");
1803         set_clksrc(priv, clksrc[CLKSRC_MPU]);
1804         set_clksrc(priv, clksrc[CLKSRC_AXI]);
1805         set_clksrc(priv, clksrc[CLKSRC_MCU]);
1806         set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css);
1807
1808         /* configure PKCK */
1809         debug("PKCK\n");
1810         pkcs_cell = dev_read_prop(dev, "st,pkcs", &len);
1811         if (pkcs_cell) {
1812                 bool ckper_disabled = false;
1813
1814                 for (i = 0; i < len / sizeof(u32); i++) {
1815                         u32 pkcs = (u32)fdt32_to_cpu(pkcs_cell[i]);
1816
1817                         if (pkcs == CLK_CKPER_DISABLED) {
1818                                 ckper_disabled = true;
1819                                 continue;
1820                         }
1821                         pkcs_config(priv, pkcs);
1822                 }
1823                 /* CKPER is source for some peripheral clock
1824                  * (FMC-NAND / QPSI-NOR) and switching source is allowed
1825                  * only if previous clock is still ON
1826                  * => deactivated CKPER only after switching clock
1827                  */
1828                 if (ckper_disabled)
1829                         pkcs_config(priv, CLK_CKPER_DISABLED);
1830         }
1831
1832         /* STGEN clock source can change with CLK_STGEN_XXX */
1833         stgen_config(priv);
1834
1835         debug("oscillator off\n");
1836         /* switch OFF HSI if not found in device-tree */
1837         if (!priv->osc[_HSI])
1838                 stm32mp1_hsi_set(rcc, 0);
1839
1840         /* Software Self-Refresh mode (SSR) during DDR initilialization */
1841         clrsetbits_le32(priv->base + RCC_DDRITFCR,
1842                         RCC_DDRITFCR_DDRCKMOD_MASK,
1843                         RCC_DDRITFCR_DDRCKMOD_SSR <<
1844                         RCC_DDRITFCR_DDRCKMOD_SHIFT);
1845
1846         return 0;
1847 }
1848 #endif /* STM32MP1_CLOCK_TREE_INIT */
1849
1850 static int pll_set_output_rate(struct udevice *dev,
1851                                int pll_id,
1852                                int div_id,
1853                                unsigned long clk_rate)
1854 {
1855         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1856         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1857         u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1858         int div;
1859         ulong fvco;
1860
1861         if (div_id > _DIV_NB)
1862                 return -EINVAL;
1863
1864         fvco = pll_get_fvco(priv, pll_id);
1865
1866         if (fvco <= clk_rate)
1867                 div = 1;
1868         else
1869                 div = DIV_ROUND_UP(fvco, clk_rate);
1870
1871         if (div > 128)
1872                 div = 128;
1873
1874         /* stop the requested output */
1875         clrbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
1876         /* change divider */
1877         clrsetbits_le32(priv->base + pll[pll_id].pllxcfgr2,
1878                         RCC_PLLNCFGR2_DIVX_MASK << RCC_PLLNCFGR2_SHIFT(div_id),
1879                         (div - 1) << RCC_PLLNCFGR2_SHIFT(div_id));
1880         /* start the requested output */
1881         setbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
1882
1883         return 0;
1884 }
1885
1886 static ulong stm32mp1_clk_set_rate(struct clk *clk, unsigned long clk_rate)
1887 {
1888         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1889         int p;
1890
1891         switch (clk->id) {
1892 #if defined(STM32MP1_CLOCK_TREE_INIT) && \
1893         defined(CONFIG_STM32MP1_DDR_INTERACTIVE)
1894         case DDRPHYC:
1895                 break;
1896 #endif
1897         case LTDC_PX:
1898         case DSI_PX:
1899                 break;
1900         default:
1901                 pr_err("not supported");
1902                 return -EINVAL;
1903         }
1904
1905         p = stm32mp1_clk_get_parent(priv, clk->id);
1906 #ifdef DEBUG
1907         debug("%s: parent = %d:%s\n", __func__, p, stm32mp1_clk_parent_name[p]);
1908 #endif
1909         if (p < 0)
1910                 return -EINVAL;
1911
1912         switch (p) {
1913 #if defined(STM32MP1_CLOCK_TREE_INIT) && \
1914         defined(CONFIG_STM32MP1_DDR_INTERACTIVE)
1915         case _PLL2_R: /* DDRPHYC */
1916         {
1917                 /* only for change DDR clock in interactive mode */
1918                 ulong result;
1919
1920                 set_clksrc(priv, CLK_AXI_HSI);
1921                 result = pll_set_rate(clk->dev,  _PLL2, _DIV_R, clk_rate);
1922                 set_clksrc(priv, CLK_AXI_PLL2P);
1923                 return result;
1924         }
1925 #endif
1926
1927         case _PLL4_Q:
1928                 /* for LTDC_PX and DSI_PX case */
1929                 return pll_set_output_rate(clk->dev, _PLL4, _DIV_Q, clk_rate);
1930         }
1931
1932         return -EINVAL;
1933 }
1934
1935 static void stm32mp1_osc_clk_init(const char *name,
1936                                   struct stm32mp1_clk_priv *priv,
1937                                   int index)
1938 {
1939         struct clk clk;
1940         struct udevice *dev = NULL;
1941
1942         priv->osc[index] = 0;
1943         clk.id = 0;
1944         if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) {
1945                 if (clk_request(dev, &clk))
1946                         pr_err("%s request", name);
1947                 else
1948                         priv->osc[index] = clk_get_rate(&clk);
1949         }
1950         priv->osc_dev[index] = dev;
1951 }
1952
1953 static void stm32mp1_osc_init(struct udevice *dev)
1954 {
1955         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1956         int i;
1957         const char *name[NB_OSC] = {
1958                 [_LSI] = "clk-lsi",
1959                 [_LSE] = "clk-lse",
1960                 [_HSI] = "clk-hsi",
1961                 [_HSE] = "clk-hse",
1962                 [_CSI] = "clk-csi",
1963                 [_I2S_CKIN] = "i2s_ckin",
1964         };
1965
1966         for (i = 0; i < NB_OSC; i++) {
1967                 stm32mp1_osc_clk_init(name[i], priv, i);
1968                 debug("%d: %s => %x\n", i, name[i], (u32)priv->osc[i]);
1969         }
1970 }
1971
1972 static void  __maybe_unused stm32mp1_clk_dump(struct stm32mp1_clk_priv *priv)
1973 {
1974         char buf[32];
1975         int i, s, p;
1976
1977         printf("Clocks:\n");
1978         for (i = 0; i < _PARENT_NB; i++) {
1979                 printf("- %s : %s MHz\n",
1980                        stm32mp1_clk_parent_name[i],
1981                        strmhz(buf, stm32mp1_clk_get(priv, i)));
1982         }
1983         printf("Source Clocks:\n");
1984         for (i = 0; i < _PARENT_SEL_NB; i++) {
1985                 p = (readl(priv->base + priv->data->sel[i].offset) >>
1986                      priv->data->sel[i].src) & priv->data->sel[i].msk;
1987                 if (p < priv->data->sel[i].nb_parent) {
1988                         s = priv->data->sel[i].parent[p];
1989                         printf("- %s(%d) => parent %s(%d)\n",
1990                                stm32mp1_clk_parent_sel_name[i], i,
1991                                stm32mp1_clk_parent_name[s], s);
1992                 } else {
1993                         printf("- %s(%d) => parent index %d is invalid\n",
1994                                stm32mp1_clk_parent_sel_name[i], i, p);
1995                 }
1996         }
1997 }
1998
1999 #ifdef CONFIG_CMD_CLK
2000 int soc_clk_dump(void)
2001 {
2002         struct udevice *dev;
2003         struct stm32mp1_clk_priv *priv;
2004         int ret;
2005
2006         ret = uclass_get_device_by_driver(UCLASS_CLK,
2007                                           DM_GET_DRIVER(stm32mp1_clock),
2008                                           &dev);
2009         if (ret)
2010                 return ret;
2011
2012         priv = dev_get_priv(dev);
2013
2014         stm32mp1_clk_dump(priv);
2015
2016         return 0;
2017 }
2018 #endif
2019
2020 static int stm32mp1_clk_probe(struct udevice *dev)
2021 {
2022         int result = 0;
2023         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
2024
2025         priv->base = dev_read_addr(dev->parent);
2026         if (priv->base == FDT_ADDR_T_NONE)
2027                 return -EINVAL;
2028
2029         priv->data = (void *)&stm32mp1_data;
2030
2031         if (!priv->data->gate || !priv->data->sel ||
2032             !priv->data->pll)
2033                 return -EINVAL;
2034
2035         stm32mp1_osc_init(dev);
2036
2037 #ifdef STM32MP1_CLOCK_TREE_INIT
2038         /* clock tree init is done only one time, before relocation */
2039         if (!(gd->flags & GD_FLG_RELOC))
2040                 result = stm32mp1_clktree(dev);
2041 #endif
2042
2043 #ifndef CONFIG_SPL_BUILD
2044 #if defined(DEBUG)
2045         /* display debug information for probe after relocation */
2046         if (gd->flags & GD_FLG_RELOC)
2047                 stm32mp1_clk_dump(priv);
2048 #endif
2049
2050         gd->cpu_clk = stm32mp1_clk_get(priv, _CK_MPU);
2051         gd->bus_clk = stm32mp1_clk_get(priv, _ACLK);
2052         /* DDRPHYC father */
2053         gd->mem_clk = stm32mp1_clk_get(priv, _PLL2_R);
2054 #if defined(CONFIG_DISPLAY_CPUINFO)
2055         if (gd->flags & GD_FLG_RELOC) {
2056                 char buf[32];
2057
2058                 printf("Clocks:\n");
2059                 printf("- MPU : %s MHz\n", strmhz(buf, gd->cpu_clk));
2060                 printf("- MCU : %s MHz\n",
2061                        strmhz(buf, stm32mp1_clk_get(priv, _CK_MCU)));
2062                 printf("- AXI : %s MHz\n", strmhz(buf, gd->bus_clk));
2063                 printf("- PER : %s MHz\n",
2064                        strmhz(buf, stm32mp1_clk_get(priv, _CK_PER)));
2065                 printf("- DDR : %s MHz\n", strmhz(buf, gd->mem_clk));
2066         }
2067 #endif /* CONFIG_DISPLAY_CPUINFO */
2068 #endif
2069
2070         return result;
2071 }
2072
2073 static const struct clk_ops stm32mp1_clk_ops = {
2074         .enable = stm32mp1_clk_enable,
2075         .disable = stm32mp1_clk_disable,
2076         .get_rate = stm32mp1_clk_get_rate,
2077         .set_rate = stm32mp1_clk_set_rate,
2078 };
2079
2080 U_BOOT_DRIVER(stm32mp1_clock) = {
2081         .name = "stm32mp1_clk",
2082         .id = UCLASS_CLK,
2083         .ops = &stm32mp1_clk_ops,
2084         .priv_auto_alloc_size = sizeof(struct stm32mp1_clk_priv),
2085         .probe = stm32mp1_clk_probe,
2086 };