drivers/clk/clk_stm32mp1.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   4  */
   5
   6 #include <common.h>
   7 #include <clk-uclass.h>
   8 #include <div64.h>
   9 #include <dm.h>
  10 #include <regmap.h>
  11 #include <spl.h>
  12 #include <syscon.h>
  13 #include <time.h>
  14 #include <vsprintf.h>
  15 #include <linux/io.h>
  16 #include <linux/iopoll.h>
  17 #include <dt-bindings/clock/stm32mp1-clks.h>
  18 #include <dt-bindings/clock/stm32mp1-clksrc.h>
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 #ifndef CONFIG_STM32MP1_TRUSTED
  23 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
  24 /* activate clock tree initialization in the driver */
  25 #define STM32MP1_CLOCK_TREE_INIT
  26 #endif
  27 #endif
  28
  29 #define MAX_HSI_HZ              64000000
  30
  31 /* TIMEOUT */
  32 #define TIMEOUT_200MS           200000
  33 #define TIMEOUT_1S              1000000
  34
  35 /* STGEN registers */
  36 #define STGENC_CNTCR            0x00
  37 #define STGENC_CNTSR            0x04
  38 #define STGENC_CNTCVL           0x08
  39 #define STGENC_CNTCVU           0x0C
  40 #define STGENC_CNTFID0          0x20
  41
  42 #define STGENC_CNTCR_EN         BIT(0)
  43
  44 /* RCC registers */
  45 #define RCC_OCENSETR            0x0C
  46 #define RCC_OCENCLRR            0x10
  47 #define RCC_HSICFGR             0x18
  48 #define RCC_MPCKSELR            0x20
  49 #define RCC_ASSCKSELR           0x24
  50 #define RCC_RCK12SELR           0x28
  51 #define RCC_MPCKDIVR            0x2C
  52 #define RCC_AXIDIVR             0x30
  53 #define RCC_APB4DIVR            0x3C
  54 #define RCC_APB5DIVR            0x40
  55 #define RCC_RTCDIVR             0x44
  56 #define RCC_MSSCKSELR           0x48
  57 #define RCC_PLL1CR              0x80
  58 #define RCC_PLL1CFGR1           0x84
  59 #define RCC_PLL1CFGR2           0x88
  60 #define RCC_PLL1FRACR           0x8C
  61 #define RCC_PLL1CSGR            0x90
  62 #define RCC_PLL2CR              0x94
  63 #define RCC_PLL2CFGR1           0x98
  64 #define RCC_PLL2CFGR2           0x9C
  65 #define RCC_PLL2FRACR           0xA0
  66 #define RCC_PLL2CSGR            0xA4
  67 #define RCC_I2C46CKSELR         0xC0
  68 #define RCC_CPERCKSELR          0xD0
  69 #define RCC_STGENCKSELR         0xD4
  70 #define RCC_DDRITFCR            0xD8
  71 #define RCC_BDCR                0x140
  72 #define RCC_RDLSICR             0x144
  73 #define RCC_MP_APB4ENSETR       0x200
  74 #define RCC_MP_APB5ENSETR       0x208
  75 #define RCC_MP_AHB5ENSETR       0x210
  76 #define RCC_MP_AHB6ENSETR       0x218
  77 #define RCC_OCRDYR              0x808
  78 #define RCC_DBGCFGR             0x80C
  79 #define RCC_RCK3SELR            0x820
  80 #define RCC_RCK4SELR            0x824
  81 #define RCC_MCUDIVR             0x830
  82 #define RCC_APB1DIVR            0x834
  83 #define RCC_APB2DIVR            0x838
  84 #define RCC_APB3DIVR            0x83C
  85 #define RCC_PLL3CR              0x880
  86 #define RCC_PLL3CFGR1           0x884
  87 #define RCC_PLL3CFGR2           0x888
  88 #define RCC_PLL3FRACR           0x88C
  89 #define RCC_PLL3CSGR            0x890
  90 #define RCC_PLL4CR              0x894
  91 #define RCC_PLL4CFGR1           0x898
  92 #define RCC_PLL4CFGR2           0x89C
  93 #define RCC_PLL4FRACR           0x8A0
  94 #define RCC_PLL4CSGR            0x8A4
  95 #define RCC_I2C12CKSELR         0x8C0
  96 #define RCC_I2C35CKSELR         0x8C4
  97 #define RCC_SPI2S1CKSELR        0x8D8
  98 #define RCC_UART6CKSELR         0x8E4
  99 #define RCC_UART24CKSELR        0x8E8
 100 #define RCC_UART35CKSELR        0x8EC
 101 #define RCC_UART78CKSELR        0x8F0
 102 #define RCC_SDMMC12CKSELR       0x8F4
 103 #define RCC_SDMMC3CKSELR        0x8F8
 104 #define RCC_ETHCKSELR           0x8FC
 105 #define RCC_QSPICKSELR          0x900
 106 #define RCC_FMCCKSELR           0x904
 107 #define RCC_USBCKSELR           0x91C
 108 #define RCC_DSICKSELR           0x924
 109 #define RCC_ADCCKSELR           0x928
 110 #define RCC_MP_APB1ENSETR       0xA00
 111 #define RCC_MP_APB2ENSETR       0XA08
 112 #define RCC_MP_APB3ENSETR       0xA10
 113 #define RCC_MP_AHB2ENSETR       0xA18
 114 #define RCC_MP_AHB3ENSETR       0xA20
 115 #define RCC_MP_AHB4ENSETR       0xA28
 116
 117 /* used for most of SELR register */
 118 #define RCC_SELR_SRC_MASK       GENMASK(2, 0)
 119 #define RCC_SELR_SRCRDY         BIT(31)
 120
 121 /* Values of RCC_MPCKSELR register */
 122 #define RCC_MPCKSELR_HSI        0
 123 #define RCC_MPCKSELR_HSE        1
 124 #define RCC_MPCKSELR_PLL        2
 125 #define RCC_MPCKSELR_PLL_MPUDIV 3
 126
 127 /* Values of RCC_ASSCKSELR register */
 128 #define RCC_ASSCKSELR_HSI       0
 129 #define RCC_ASSCKSELR_HSE       1
 130 #define RCC_ASSCKSELR_PLL       2
 131
 132 /* Values of RCC_MSSCKSELR register */
 133 #define RCC_MSSCKSELR_HSI       0
 134 #define RCC_MSSCKSELR_HSE       1
 135 #define RCC_MSSCKSELR_CSI       2
 136 #define RCC_MSSCKSELR_PLL       3
 137
 138 /* Values of RCC_CPERCKSELR register */
 139 #define RCC_CPERCKSELR_HSI      0
 140 #define RCC_CPERCKSELR_CSI      1
 141 #define RCC_CPERCKSELR_HSE      2
 142
 143 /* used for most of DIVR register : max div for RTC */
 144 #define RCC_DIVR_DIV_MASK       GENMASK(5, 0)
 145 #define RCC_DIVR_DIVRDY         BIT(31)
 146
 147 /* Masks for specific DIVR registers */
 148 #define RCC_APBXDIV_MASK        GENMASK(2, 0)
 149 #define RCC_MPUDIV_MASK         GENMASK(2, 0)
 150 #define RCC_AXIDIV_MASK         GENMASK(2, 0)
 151 #define RCC_MCUDIV_MASK         GENMASK(3, 0)
 152
 153 /*  offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
 154 #define RCC_MP_ENCLRR_OFFSET    4
 155
 156 /* Fields of RCC_BDCR register */
 157 #define RCC_BDCR_LSEON          BIT(0)
 158 #define RCC_BDCR_LSEBYP         BIT(1)
 159 #define RCC_BDCR_LSERDY         BIT(2)
 160 #define RCC_BDCR_DIGBYP         BIT(3)
 161 #define RCC_BDCR_LSEDRV_MASK    GENMASK(5, 4)
 162 #define RCC_BDCR_LSEDRV_SHIFT   4
 163 #define RCC_BDCR_LSECSSON       BIT(8)
 164 #define RCC_BDCR_RTCCKEN        BIT(20)
 165 #define RCC_BDCR_RTCSRC_MASK    GENMASK(17, 16)
 166 #define RCC_BDCR_RTCSRC_SHIFT   16
 167
 168 /* Fields of RCC_RDLSICR register */
 169 #define RCC_RDLSICR_LSION       BIT(0)
 170 #define RCC_RDLSICR_LSIRDY      BIT(1)
 171
 172 /* used for ALL PLLNCR registers */
 173 #define RCC_PLLNCR_PLLON        BIT(0)
 174 #define RCC_PLLNCR_PLLRDY       BIT(1)
 175 #define RCC_PLLNCR_SSCG_CTRL    BIT(2)
 176 #define RCC_PLLNCR_DIVPEN       BIT(4)
 177 #define RCC_PLLNCR_DIVQEN       BIT(5)
 178 #define RCC_PLLNCR_DIVREN       BIT(6)
 179 #define RCC_PLLNCR_DIVEN_SHIFT  4
 180
 181 /* used for ALL PLLNCFGR1 registers */
 182 #define RCC_PLLNCFGR1_DIVM_SHIFT        16
 183 #define RCC_PLLNCFGR1_DIVM_MASK         GENMASK(21, 16)
 184 #define RCC_PLLNCFGR1_DIVN_SHIFT        0
 185 #define RCC_PLLNCFGR1_DIVN_MASK         GENMASK(8, 0)
 186 /* only for PLL3 and PLL4 */
 187 #define RCC_PLLNCFGR1_IFRGE_SHIFT       24
 188 #define RCC_PLLNCFGR1_IFRGE_MASK        GENMASK(25, 24)
 189
 190 /* used for ALL PLLNCFGR2 registers , using stm32mp1_div_id */
 191 #define RCC_PLLNCFGR2_SHIFT(div_id)     ((div_id) * 8)
 192 #define RCC_PLLNCFGR2_DIVX_MASK         GENMASK(6, 0)
 193 #define RCC_PLLNCFGR2_DIVP_SHIFT        RCC_PLLNCFGR2_SHIFT(_DIV_P)
 194 #define RCC_PLLNCFGR2_DIVP_MASK         GENMASK(6, 0)
 195 #define RCC_PLLNCFGR2_DIVQ_SHIFT        RCC_PLLNCFGR2_SHIFT(_DIV_Q)
 196 #define RCC_PLLNCFGR2_DIVQ_MASK         GENMASK(14, 8)
 197 #define RCC_PLLNCFGR2_DIVR_SHIFT        RCC_PLLNCFGR2_SHIFT(_DIV_R)
 198 #define RCC_PLLNCFGR2_DIVR_MASK         GENMASK(22, 16)
 199
 200 /* used for ALL PLLNFRACR registers */
 201 #define RCC_PLLNFRACR_FRACV_SHIFT       3
 202 #define RCC_PLLNFRACR_FRACV_MASK        GENMASK(15, 3)
 203 #define RCC_PLLNFRACR_FRACLE            BIT(16)
 204
 205 /* used for ALL PLLNCSGR registers */
 206 #define RCC_PLLNCSGR_INC_STEP_SHIFT     16
 207 #define RCC_PLLNCSGR_INC_STEP_MASK      GENMASK(30, 16)
 208 #define RCC_PLLNCSGR_MOD_PER_SHIFT      0
 209 #define RCC_PLLNCSGR_MOD_PER_MASK       GENMASK(12, 0)
 210 #define RCC_PLLNCSGR_SSCG_MODE_SHIFT    15
 211 #define RCC_PLLNCSGR_SSCG_MODE_MASK     BIT(15)
 212
 213 /* used for RCC_OCENSETR and RCC_OCENCLRR registers */
 214 #define RCC_OCENR_HSION                 BIT(0)
 215 #define RCC_OCENR_CSION                 BIT(4)
 216 #define RCC_OCENR_DIGBYP                BIT(7)
 217 #define RCC_OCENR_HSEON                 BIT(8)
 218 #define RCC_OCENR_HSEBYP                BIT(10)
 219 #define RCC_OCENR_HSECSSON              BIT(11)
 220
 221 /* Fields of RCC_OCRDYR register */
 222 #define RCC_OCRDYR_HSIRDY               BIT(0)
 223 #define RCC_OCRDYR_HSIDIVRDY            BIT(2)
 224 #define RCC_OCRDYR_CSIRDY               BIT(4)
 225 #define RCC_OCRDYR_HSERDY               BIT(8)
 226
 227 /* Fields of DDRITFCR register */
 228 #define RCC_DDRITFCR_DDRCKMOD_MASK      GENMASK(22, 20)
 229 #define RCC_DDRITFCR_DDRCKMOD_SHIFT     20
 230 #define RCC_DDRITFCR_DDRCKMOD_SSR       0
 231
 232 /* Fields of RCC_HSICFGR register */
 233 #define RCC_HSICFGR_HSIDIV_MASK         GENMASK(1, 0)
 234
 235 /* used for MCO related operations */
 236 #define RCC_MCOCFG_MCOON                BIT(12)
 237 #define RCC_MCOCFG_MCODIV_MASK          GENMASK(7, 4)
 238 #define RCC_MCOCFG_MCODIV_SHIFT         4
 239 #define RCC_MCOCFG_MCOSRC_MASK          GENMASK(2, 0)
 240
 241 enum stm32mp1_parent_id {
 242 /*
 243  * _HSI, _HSE, _CSI, _LSI, _LSE should not be moved
 244  * they are used as index in osc[] as entry point
 245  */
 246         _HSI,
 247         _HSE,
 248         _CSI,
 249         _LSI,
 250         _LSE,
 251         _I2S_CKIN,
 252         NB_OSC,
 253
 254 /* other parent source */
 255         _HSI_KER = NB_OSC,
 256         _HSE_KER,
 257         _HSE_KER_DIV2,
 258         _CSI_KER,
 259         _PLL1_P,
 260         _PLL1_Q,
 261         _PLL1_R,
 262         _PLL2_P,
 263         _PLL2_Q,
 264         _PLL2_R,
 265         _PLL3_P,
 266         _PLL3_Q,
 267         _PLL3_R,
 268         _PLL4_P,
 269         _PLL4_Q,
 270         _PLL4_R,
 271         _ACLK,
 272         _PCLK1,
 273         _PCLK2,
 274         _PCLK3,
 275         _PCLK4,
 276         _PCLK5,
 277         _HCLK6,
 278         _HCLK2,
 279         _CK_PER,
 280         _CK_MPU,
 281         _CK_MCU,
 282         _DSI_PHY,
 283         _USB_PHY_48,
 284         _PARENT_NB,
 285         _UNKNOWN_ID = 0xff,
 286 };
 287
 288 enum stm32mp1_parent_sel {
 289         _I2C12_SEL,
 290         _I2C35_SEL,
 291         _I2C46_SEL,
 292         _UART6_SEL,
 293         _UART24_SEL,
 294         _UART35_SEL,
 295         _UART78_SEL,
 296         _SDMMC12_SEL,
 297         _SDMMC3_SEL,
 298         _ETH_SEL,
 299         _QSPI_SEL,
 300         _FMC_SEL,
 301         _USBPHY_SEL,
 302         _USBO_SEL,
 303         _STGEN_SEL,
 304         _DSI_SEL,
 305         _ADC12_SEL,
 306         _SPI1_SEL,
 307         _RTC_SEL,
 308         _PARENT_SEL_NB,
 309         _UNKNOWN_SEL = 0xff,
 310 };
 311
 312 enum stm32mp1_pll_id {
 313         _PLL1,
 314         _PLL2,
 315         _PLL3,
 316         _PLL4,
 317         _PLL_NB
 318 };
 319
 320 enum stm32mp1_div_id {
 321         _DIV_P,
 322         _DIV_Q,
 323         _DIV_R,
 324         _DIV_NB,
 325 };
 326
 327 enum stm32mp1_clksrc_id {
 328         CLKSRC_MPU,
 329         CLKSRC_AXI,
 330         CLKSRC_MCU,
 331         CLKSRC_PLL12,
 332         CLKSRC_PLL3,
 333         CLKSRC_PLL4,
 334         CLKSRC_RTC,
 335         CLKSRC_MCO1,
 336         CLKSRC_MCO2,
 337         CLKSRC_NB
 338 };
 339
 340 enum stm32mp1_clkdiv_id {
 341         CLKDIV_MPU,
 342         CLKDIV_AXI,
 343         CLKDIV_MCU,
 344         CLKDIV_APB1,
 345         CLKDIV_APB2,
 346         CLKDIV_APB3,
 347         CLKDIV_APB4,
 348         CLKDIV_APB5,
 349         CLKDIV_RTC,
 350         CLKDIV_MCO1,
 351         CLKDIV_MCO2,
 352         CLKDIV_NB
 353 };
 354
 355 enum stm32mp1_pllcfg {
 356         PLLCFG_M,
 357         PLLCFG_N,
 358         PLLCFG_P,
 359         PLLCFG_Q,
 360         PLLCFG_R,
 361         PLLCFG_O,
 362         PLLCFG_NB
 363 };
 364
 365 enum stm32mp1_pllcsg {
 366         PLLCSG_MOD_PER,
 367         PLLCSG_INC_STEP,
 368         PLLCSG_SSCG_MODE,
 369         PLLCSG_NB
 370 };
 371
 372 enum stm32mp1_plltype {
 373         PLL_800,
 374         PLL_1600,
 375         PLL_TYPE_NB
 376 };
 377
 378 struct stm32mp1_pll {
 379         u8 refclk_min;
 380         u8 refclk_max;
 381         u8 divn_max;
 382 };
 383
 384 struct stm32mp1_clk_gate {
 385         u16 offset;
 386         u8 bit;
 387         u8 index;
 388         u8 set_clr;
 389         u8 sel;
 390         u8 fixed;
 391 };
 392
 393 struct stm32mp1_clk_sel {
 394         u16 offset;
 395         u8 src;
 396         u8 msk;
 397         u8 nb_parent;
 398         const u8 *parent;
 399 };
 400
 401 #define REFCLK_SIZE 4
 402 struct stm32mp1_clk_pll {
 403         enum stm32mp1_plltype plltype;
 404         u16 rckxselr;
 405         u16 pllxcfgr1;
 406         u16 pllxcfgr2;
 407         u16 pllxfracr;
 408         u16 pllxcr;
 409         u16 pllxcsgr;
 410         u8 refclk[REFCLK_SIZE];
 411 };
 412
 413 struct stm32mp1_clk_data {
 414         const struct stm32mp1_clk_gate *gate;
 415         const struct stm32mp1_clk_sel *sel;
 416         const struct stm32mp1_clk_pll *pll;
 417         const int nb_gate;
 418 };
 419
 420 struct stm32mp1_clk_priv {
 421         fdt_addr_t base;
 422         const struct stm32mp1_clk_data *data;
 423         ulong osc[NB_OSC];
 424         struct udevice *osc_dev[NB_OSC];
 425 };
 426
 427 #define STM32MP1_CLK(off, b, idx, s)            \
 428         {                                       \
 429                 .offset = (off),                \
 430                 .bit = (b),                     \
 431                 .index = (idx),                 \
 432                 .set_clr = 0,                   \
 433                 .sel = (s),                     \
 434                 .fixed = _UNKNOWN_ID,           \
 435         }
 436
 437 #define STM32MP1_CLK_F(off, b, idx, f)          \
 438         {                                       \
 439                 .offset = (off),                \
 440                 .bit = (b),                     \
 441                 .index = (idx),                 \
 442                 .set_clr = 0,                   \
 443                 .sel = _UNKNOWN_SEL,            \
 444                 .fixed = (f),                   \
 445         }
 446
 447 #define STM32MP1_CLK_SET_CLR(off, b, idx, s)    \
 448         {                                       \
 449                 .offset = (off),                \
 450                 .bit = (b),                     \
 451                 .index = (idx),                 \
 452                 .set_clr = 1,                   \
 453                 .sel = (s),                     \
 454                 .fixed = _UNKNOWN_ID,           \
 455         }
 456
 457 #define STM32MP1_CLK_SET_CLR_F(off, b, idx, f)  \
 458         {                                       \
 459                 .offset = (off),                \
 460                 .bit = (b),                     \
 461                 .index = (idx),                 \
 462                 .set_clr = 1,                   \
 463                 .sel = _UNKNOWN_SEL,            \
 464                 .fixed = (f),                   \
 465         }
 466
 467 #define STM32MP1_CLK_PARENT(idx, off, s, m, p)   \
 468         [(idx)] = {                             \
 469                 .offset = (off),                \
 470                 .src = (s),                     \
 471                 .msk = (m),                     \
 472                 .parent = (p),                  \
 473                 .nb_parent = ARRAY_SIZE((p))    \
 474         }
 475
 476 #define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, off4, off5, off6,\
 477                         p1, p2, p3, p4) \
 478         [(idx)] = {                             \
 479                 .plltype = (type),                      \
 480                 .rckxselr = (off1),             \
 481                 .pllxcfgr1 = (off2),            \
 482                 .pllxcfgr2 = (off3),            \
 483                 .pllxfracr = (off4),            \
 484                 .pllxcr = (off5),               \
 485                 .pllxcsgr = (off6),             \
 486                 .refclk[0] = (p1),              \
 487                 .refclk[1] = (p2),              \
 488                 .refclk[2] = (p3),              \
 489                 .refclk[3] = (p4),              \
 490         }
 491
 492 static const u8 stm32mp1_clks[][2] = {
 493         {CK_PER, _CK_PER},
 494         {CK_MPU, _CK_MPU},
 495         {CK_AXI, _ACLK},
 496         {CK_MCU, _CK_MCU},
 497         {CK_HSE, _HSE},
 498         {CK_CSI, _CSI},
 499         {CK_LSI, _LSI},
 500         {CK_LSE, _LSE},
 501         {CK_HSI, _HSI},
 502         {CK_HSE_DIV2, _HSE_KER_DIV2},
 503 };
 504
 505 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
 506         STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL),
 507         STM32MP1_CLK(RCC_DDRITFCR, 1, DDRC1LP, _UNKNOWN_SEL),
 508         STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL),
 509         STM32MP1_CLK(RCC_DDRITFCR, 3, DDRC2LP, _UNKNOWN_SEL),
 510         STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
 511         STM32MP1_CLK(RCC_DDRITFCR, 5, DDRPHYCLP, _UNKNOWN_SEL),
 512         STM32MP1_CLK(RCC_DDRITFCR, 6, DDRCAPB, _UNKNOWN_SEL),
 513         STM32MP1_CLK(RCC_DDRITFCR, 7, DDRCAPBLP, _UNKNOWN_SEL),
 514         STM32MP1_CLK(RCC_DDRITFCR, 8, AXIDCG, _UNKNOWN_SEL),
 515         STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL),
 516         STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL),
 517
 518         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
 519         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
 520         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
 521         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL),
 522         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL),
 523         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL),
 524         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL),
 525         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL),
 526         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL),
 527         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
 528
 529         STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 8, SPI1_K, _SPI1_SEL),
 530         STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
 531
 532         STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3),
 533
 534         STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 0, LTDC_PX, _PLL4_Q),
 535         STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 4, DSI_PX, _PLL4_Q),
 536         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 4, DSI_K, _DSI_SEL),
 537         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
 538         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
 539         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
 540
 541         STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
 542         STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5),
 543         STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
 544
 545         STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB2ENSETR, 5, ADC12, _HCLK2),
 546         STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 5, ADC12_K, _ADC12_SEL),
 547         STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
 548         STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
 549
 550         STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 11, HSEM, _UNKNOWN_SEL),
 551         STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 12, IPCC, _UNKNOWN_SEL),
 552
 553         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
 554         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
 555         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
 556         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL),
 557         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL),
 558         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL),
 559         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL),
 560         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL),
 561         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL),
 562         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL),
 563         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
 564
 565         STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
 566
 567         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK_K, _ETH_SEL),
 568         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL),
 569         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL),
 570         STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK),
 571         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
 572         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
 573         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL),
 574         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL),
 575         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL),
 576
 577         STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
 578
 579         STM32MP1_CLK(RCC_BDCR, 20, RTC, _RTC_SEL),
 580 };
 581
 582 static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
 583 static const u8 i2c35_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
 584 static const u8 i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER};
 585 static const u8 uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
 586                                         _HSE_KER};
 587 static const u8 uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 588                                          _HSE_KER};
 589 static const u8 uart35_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 590                                          _HSE_KER};
 591 static const u8 uart78_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 592                                          _HSE_KER};
 593 static const u8 sdmmc12_parents[] = {_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER};
 594 static const u8 sdmmc3_parents[] = {_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER};
 595 static const u8 eth_parents[] = {_PLL4_P, _PLL3_Q};
 596 static const u8 qspi_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
 597 static const u8 fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
 598 static const u8 usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2};
 599 static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48};
 600 static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER};
 601 static const u8 dsi_parents[] = {_DSI_PHY, _PLL4_P};
 602 static const u8 adc_parents[] = {_PLL4_R, _CK_PER, _PLL3_Q};
 603 static const u8 spi_parents[] = {_PLL4_P, _PLL3_Q, _I2S_CKIN, _CK_PER,
 604                                  _PLL3_R};
 605 static const u8 rtc_parents[] = {_UNKNOWN_ID, _LSE, _LSI, _HSE};
 606
 607 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
 608         STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents),
 609         STM32MP1_CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents),
 610         STM32MP1_CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents),
 611         STM32MP1_CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents),
 612         STM32MP1_CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7,
 613                             uart24_parents),
 614         STM32MP1_CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7,
 615                             uart35_parents),
 616         STM32MP1_CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7,
 617                             uart78_parents),
 618         STM32MP1_CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7,
 619                             sdmmc12_parents),
 620         STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7,
 621                             sdmmc3_parents),
 622         STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents),
 623         STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents),
 624         STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents),
 625         STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents),
 626         STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
 627         STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
 628         STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents),
 629         STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x1, adc_parents),
 630         STM32MP1_CLK_PARENT(_SPI1_SEL, RCC_SPI2S1CKSELR, 0, 0x7, spi_parents),
 631         STM32MP1_CLK_PARENT(_RTC_SEL, RCC_BDCR, RCC_BDCR_RTCSRC_SHIFT,
 632                             (RCC_BDCR_RTCSRC_MASK >> RCC_BDCR_RTCSRC_SHIFT),
 633                             rtc_parents),
 634 };
 635
 636 #ifdef STM32MP1_CLOCK_TREE_INIT
 637 /* define characteristic of PLL according type */
 638 #define DIVN_MIN        24
 639 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
 640         [PLL_800] = {
 641                 .refclk_min = 4,
 642                 .refclk_max = 16,
 643                 .divn_max = 99,
 644                 },
 645         [PLL_1600] = {
 646                 .refclk_min = 8,
 647                 .refclk_max = 16,
 648                 .divn_max = 199,
 649                 },
 650 };
 651 #endif /* STM32MP1_CLOCK_TREE_INIT */
 652
 653 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = {
 654         STM32MP1_CLK_PLL(_PLL1, PLL_1600,
 655                          RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2,
 656                          RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR,
 657                          _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
 658         STM32MP1_CLK_PLL(_PLL2, PLL_1600,
 659                          RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2,
 660                          RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR,
 661                          _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
 662         STM32MP1_CLK_PLL(_PLL3, PLL_800,
 663                          RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2,
 664                          RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR,
 665                          _HSI, _HSE, _CSI, _UNKNOWN_ID),
 666         STM32MP1_CLK_PLL(_PLL4, PLL_800,
 667                          RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2,
 668                          RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR,
 669                          _HSI, _HSE, _CSI, _I2S_CKIN),
 670 };
 671
 672 /* Prescaler table lookups for clock computation */
 673 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */
 674 static const u8 stm32mp1_mcu_div[16] = {
 675         0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9
 676 };
 677
 678 /* div = /1 /2 /4 /8 /16 : same divider for pmu and apbx*/
 679 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div
 680 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div
 681 static const u8 stm32mp1_mpu_apbx_div[8] = {
 682         0, 1, 2, 3, 4, 4, 4, 4
 683 };
 684
 685 /* div = /1 /2 /3 /4 */
 686 static const u8 stm32mp1_axi_div[8] = {
 687         1, 2, 3, 4, 4, 4, 4, 4
 688 };
 689
 690 static const __maybe_unused
 691 char * const stm32mp1_clk_parent_name[_PARENT_NB] = {
 692         [_HSI] = "HSI",
 693         [_HSE] = "HSE",
 694         [_CSI] = "CSI",
 695         [_LSI] = "LSI",
 696         [_LSE] = "LSE",
 697         [_I2S_CKIN] = "I2S_CKIN",
 698         [_HSI_KER] = "HSI_KER",
 699         [_HSE_KER] = "HSE_KER",
 700         [_HSE_KER_DIV2] = "HSE_KER_DIV2",
 701         [_CSI_KER] = "CSI_KER",
 702         [_PLL1_P] = "PLL1_P",
 703         [_PLL1_Q] = "PLL1_Q",
 704         [_PLL1_R] = "PLL1_R",
 705         [_PLL2_P] = "PLL2_P",
 706         [_PLL2_Q] = "PLL2_Q",
 707         [_PLL2_R] = "PLL2_R",
 708         [_PLL3_P] = "PLL3_P",
 709         [_PLL3_Q] = "PLL3_Q",
 710         [_PLL3_R] = "PLL3_R",
 711         [_PLL4_P] = "PLL4_P",
 712         [_PLL4_Q] = "PLL4_Q",
 713         [_PLL4_R] = "PLL4_R",
 714         [_ACLK] = "ACLK",
 715         [_PCLK1] = "PCLK1",
 716         [_PCLK2] = "PCLK2",
 717         [_PCLK3] = "PCLK3",
 718         [_PCLK4] = "PCLK4",
 719         [_PCLK5] = "PCLK5",
 720         [_HCLK6] = "KCLK6",
 721         [_HCLK2] = "HCLK2",
 722         [_CK_PER] = "CK_PER",
 723         [_CK_MPU] = "CK_MPU",
 724         [_CK_MCU] = "CK_MCU",
 725         [_USB_PHY_48] = "USB_PHY_48",
 726         [_DSI_PHY] = "DSI_PHY_PLL",
 727 };
 728
 729 static const __maybe_unused
 730 char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
 731         [_I2C12_SEL] = "I2C12",
 732         [_I2C35_SEL] = "I2C35",
 733         [_I2C46_SEL] = "I2C46",
 734         [_UART6_SEL] = "UART6",
 735         [_UART24_SEL] = "UART24",
 736         [_UART35_SEL] = "UART35",
 737         [_UART78_SEL] = "UART78",
 738         [_SDMMC12_SEL] = "SDMMC12",
 739         [_SDMMC3_SEL] = "SDMMC3",
 740         [_ETH_SEL] = "ETH",
 741         [_QSPI_SEL] = "QSPI",
 742         [_FMC_SEL] = "FMC",
 743         [_USBPHY_SEL] = "USBPHY",
 744         [_USBO_SEL] = "USBO",
 745         [_STGEN_SEL] = "STGEN",
 746         [_DSI_SEL] = "DSI",
 747         [_ADC12_SEL] = "ADC12",
 748         [_SPI1_SEL] = "SPI1",
 749         [_RTC_SEL] = "RTC",
 750 };
 751
 752 static const struct stm32mp1_clk_data stm32mp1_data = {
 753         .gate = stm32mp1_clk_gate,
 754         .sel = stm32mp1_clk_sel,
 755         .pll = stm32mp1_clk_pll,
 756         .nb_gate = ARRAY_SIZE(stm32mp1_clk_gate),
 757 };
 758
 759 static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx)
 760 {
 761         if (idx >= NB_OSC) {
 762                 debug("%s: clk id %d not found\n", __func__, idx);
 763                 return 0;
 764         }
 765
 766         return priv->osc[idx];
 767 }
 768
 769 static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id)
 770 {
 771         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 772         int i, nb_clks = priv->data->nb_gate;
 773
 774         for (i = 0; i < nb_clks; i++) {
 775                 if (gate[i].index == id)
 776                         break;
 777         }
 778
 779         if (i == nb_clks) {
 780                 printf("%s: clk id %d not found\n", __func__, (u32)id);
 781                 return -EINVAL;
 782         }
 783
 784         return i;
 785 }
 786
 787 static int stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv,
 788                                 int i)
 789 {
 790         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 791
 792         if (gate[i].sel > _PARENT_SEL_NB) {
 793                 printf("%s: parents for clk id %d not found\n",
 794                        __func__, i);
 795                 return -EINVAL;
 796         }
 797
 798         return gate[i].sel;
 799 }
 800
 801 static int stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv *priv,
 802                                          int i)
 803 {
 804         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 805
 806         if (gate[i].fixed == _UNKNOWN_ID)
 807                 return -ENOENT;
 808
 809         return gate[i].fixed;
 810 }
 811
 812 static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv,
 813                                    unsigned long id)
 814 {
 815         const struct stm32mp1_clk_sel *sel = priv->data->sel;
 816         int i;
 817         int s, p;
 818         unsigned int idx;
 819
 820         for (idx = 0; idx < ARRAY_SIZE(stm32mp1_clks); idx++)
 821                 if (stm32mp1_clks[idx][0] == id)
 822                         return stm32mp1_clks[idx][1];
 823
 824         i = stm32mp1_clk_get_id(priv, id);
 825         if (i < 0)
 826                 return i;
 827
 828         p = stm32mp1_clk_get_fixed_parent(priv, i);
 829         if (p >= 0 && p < _PARENT_NB)
 830                 return p;
 831
 832         s = stm32mp1_clk_get_sel(priv, i);
 833         if (s < 0)
 834                 return s;
 835
 836         p = (readl(priv->base + sel[s].offset) >> sel[s].src) & sel[s].msk;
 837
 838         if (p < sel[s].nb_parent) {
 839 #ifdef DEBUG
 840                 debug("%s: %s clock is the parent %s of clk id %d\n", __func__,
 841                       stm32mp1_clk_parent_name[sel[s].parent[p]],
 842                       stm32mp1_clk_parent_sel_name[s],
 843                       (u32)id);
 844 #endif
 845                 return sel[s].parent[p];
 846         }
 847
 848         pr_err("%s: no parents defined for clk id %d\n",
 849                __func__, (u32)id);
 850
 851         return -EINVAL;
 852 }
 853
 854 static ulong  pll_get_fref_ck(struct stm32mp1_clk_priv *priv,
 855                               int pll_id)
 856 {
 857         const struct stm32mp1_clk_pll *pll = priv->data->pll;
 858         u32 selr;
 859         int src;
 860         ulong refclk;
 861
 862         /* Get current refclk */
 863         selr = readl(priv->base + pll[pll_id].rckxselr);
 864         src = selr & RCC_SELR_SRC_MASK;
 865
 866         refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]);
 867
 868         return refclk;
 869 }
 870
 871 /*
 872  * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL
 873  * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1)
 874  * - PLL3 & PLL4 => return VCO     with Fpll_y_ck = FVCO / (DIVy + 1)
 875  * => in all the case Fpll_y_ck = pll_get_fvco() / (DIVy + 1)
 876  */
 877 static ulong pll_get_fvco(struct stm32mp1_clk_priv *priv,
 878                           int pll_id)
 879 {
 880         const struct stm32mp1_clk_pll *pll = priv->data->pll;
 881         int divm, divn;
 882         ulong refclk, fvco;
 883         u32 cfgr1, fracr;
 884
 885         cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1);
 886         fracr = readl(priv->base + pll[pll_id].pllxfracr);
 887
 888         divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
 889         divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
 890
 891         refclk = pll_get_fref_ck(priv, pll_id);
 892
 893         /* with FRACV :
 894          *   Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1)
 895          * without FRACV
 896          *   Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1)
 897          */
 898         if (fracr & RCC_PLLNFRACR_FRACLE) {
 899                 u32 fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK)
 900                             >> RCC_PLLNFRACR_FRACV_SHIFT;
 901                 fvco = (ulong)lldiv((unsigned long long)refclk *
 902                                      (((divn + 1) << 13) + fracv),
 903                                      ((unsigned long long)(divm + 1)) << 13);
 904         } else {
 905                 fvco = (ulong)(refclk * (divn + 1) / (divm + 1));
 906         }
 907
 908         return fvco;
 909 }
 910
 911 static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
 912                                     int pll_id, int div_id)
 913 {
 914         const struct stm32mp1_clk_pll *pll = priv->data->pll;
 915         int divy;
 916         ulong dfout;
 917         u32 cfgr2;
 918
 919         if (div_id >= _DIV_NB)
 920                 return 0;
 921
 922         cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2);
 923         divy = (cfgr2 >> RCC_PLLNCFGR2_SHIFT(div_id)) & RCC_PLLNCFGR2_DIVX_MASK;
 924
 925         dfout = pll_get_fvco(priv, pll_id) / (divy + 1);
 926
 927         return dfout;
 928 }
 929
 930 static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
 931 {
 932         u32 reg;
 933         ulong clock = 0;
 934
 935         switch (p) {
 936         case _CK_MPU:
 937         /* MPU sub system */
 938                 reg = readl(priv->base + RCC_MPCKSELR);
 939                 switch (reg & RCC_SELR_SRC_MASK) {
 940                 case RCC_MPCKSELR_HSI:
 941                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
 942                         break;
 943                 case RCC_MPCKSELR_HSE:
 944                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
 945                         break;
 946                 case RCC_MPCKSELR_PLL:
 947                 case RCC_MPCKSELR_PLL_MPUDIV:
 948                         clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P);
 949                         if (p == RCC_MPCKSELR_PLL_MPUDIV) {
 950                                 reg = readl(priv->base + RCC_MPCKDIVR);
 951                                 clock /= stm32mp1_mpu_div[reg &
 952                                                           RCC_MPUDIV_MASK];
 953                         }
 954                         break;
 955                 }
 956                 break;
 957         /* AXI sub system */
 958         case _ACLK:
 959         case _HCLK2:
 960         case _HCLK6:
 961         case _PCLK4:
 962         case _PCLK5:
 963                 reg = readl(priv->base + RCC_ASSCKSELR);
 964                 switch (reg & RCC_SELR_SRC_MASK) {
 965                 case RCC_ASSCKSELR_HSI:
 966                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
 967                         break;
 968                 case RCC_ASSCKSELR_HSE:
 969                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
 970                         break;
 971                 case RCC_ASSCKSELR_PLL:
 972                         clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P);
 973                         break;
 974                 }
 975
 976                 /* System clock divider */
 977                 reg = readl(priv->base + RCC_AXIDIVR);
 978                 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK];
 979
 980                 switch (p) {
 981                 case _PCLK4:
 982                         reg = readl(priv->base + RCC_APB4DIVR);
 983                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
 984                         break;
 985                 case _PCLK5:
 986                         reg = readl(priv->base + RCC_APB5DIVR);
 987                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
 988                         break;
 989                 default:
 990                         break;
 991                 }
 992                 break;
 993         /* MCU sub system */
 994         case _CK_MCU:
 995         case _PCLK1:
 996         case _PCLK2:
 997         case _PCLK3:
 998                 reg = readl(priv->base + RCC_MSSCKSELR);
 999                 switch (reg & RCC_SELR_SRC_MASK) {
1000                 case RCC_MSSCKSELR_HSI:
1001                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
1002                         break;
1003                 case RCC_MSSCKSELR_HSE:
1004                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
1005                         break;
1006                 case RCC_MSSCKSELR_CSI:
1007                         clock = stm32mp1_clk_get_fixed(priv, _CSI);
1008                         break;
1009                 case RCC_MSSCKSELR_PLL:
1010                         clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_P);
1011                         break;
1012                 }
1013
1014                 /* MCU clock divider */
1015                 reg = readl(priv->base + RCC_MCUDIVR);
1016                 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK];
1017
1018                 switch (p) {
1019                 case _PCLK1:
1020                         reg = readl(priv->base + RCC_APB1DIVR);
1021                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1022                         break;
1023                 case _PCLK2:
1024                         reg = readl(priv->base + RCC_APB2DIVR);
1025                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1026                         break;
1027                 case _PCLK3:
1028                         reg = readl(priv->base + RCC_APB3DIVR);
1029                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1030                         break;
1031                 case _CK_MCU:
1032                 default:
1033                         break;
1034                 }
1035                 break;
1036         case _CK_PER:
1037                 reg = readl(priv->base + RCC_CPERCKSELR);
1038                 switch (reg & RCC_SELR_SRC_MASK) {
1039                 case RCC_CPERCKSELR_HSI:
1040                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
1041                         break;
1042                 case RCC_CPERCKSELR_HSE:
1043                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
1044                         break;
1045                 case RCC_CPERCKSELR_CSI:
1046                         clock = stm32mp1_clk_get_fixed(priv, _CSI);
1047                         break;
1048                 }
1049                 break;
1050         case _HSI:
1051         case _HSI_KER:
1052                 clock = stm32mp1_clk_get_fixed(priv, _HSI);
1053                 break;
1054         case _CSI:
1055         case _CSI_KER:
1056                 clock = stm32mp1_clk_get_fixed(priv, _CSI);
1057                 break;
1058         case _HSE:
1059         case _HSE_KER:
1060         case _HSE_KER_DIV2:
1061                 clock = stm32mp1_clk_get_fixed(priv, _HSE);
1062                 if (p == _HSE_KER_DIV2)
1063                         clock >>= 1;
1064                 break;
1065         case _LSI:
1066                 clock = stm32mp1_clk_get_fixed(priv, _LSI);
1067                 break;
1068         case _LSE:
1069                 clock = stm32mp1_clk_get_fixed(priv, _LSE);
1070                 break;
1071         /* PLL */
1072         case _PLL1_P:
1073         case _PLL1_Q:
1074         case _PLL1_R:
1075                 clock = stm32mp1_read_pll_freq(priv, _PLL1, p - _PLL1_P);
1076                 break;
1077         case _PLL2_P:
1078         case _PLL2_Q:
1079         case _PLL2_R:
1080                 clock = stm32mp1_read_pll_freq(priv, _PLL2, p - _PLL2_P);
1081                 break;
1082         case _PLL3_P:
1083         case _PLL3_Q:
1084         case _PLL3_R:
1085                 clock = stm32mp1_read_pll_freq(priv, _PLL3, p - _PLL3_P);
1086                 break;
1087         case _PLL4_P:
1088         case _PLL4_Q:
1089         case _PLL4_R:
1090                 clock = stm32mp1_read_pll_freq(priv, _PLL4, p - _PLL4_P);
1091                 break;
1092         /* other */
1093         case _USB_PHY_48:
1094                 clock = 48000000;
1095                 break;
1096         case _DSI_PHY:
1097         {
1098                 struct clk clk;
1099                 struct udevice *dev = NULL;
1100
1101                 if (!uclass_get_device_by_name(UCLASS_CLK, "ck_dsi_phy",
1102                                                &dev)) {
1103                         if (clk_request(dev, &clk)) {
1104                                 pr_err("ck_dsi_phy request");
1105                         } else {
1106                                 clk.id = 0;
1107                                 clock = clk_get_rate(&clk);
1108                         }
1109                 }
1110                 break;
1111         }
1112         default:
1113                 break;
1114         }
1115
1116         debug("%s(%d) clock = %lx : %ld kHz\n",
1117               __func__, p, clock, clock / 1000);
1118
1119         return clock;
1120 }
1121
1122 static int stm32mp1_clk_enable(struct clk *clk)
1123 {
1124         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1125         const struct stm32mp1_clk_gate *gate = priv->data->gate;
1126         int i = stm32mp1_clk_get_id(priv, clk->id);
1127
1128         if (i < 0)
1129                 return i;
1130
1131         if (gate[i].set_clr)
1132                 writel(BIT(gate[i].bit), priv->base + gate[i].offset);
1133         else
1134                 setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1135
1136         debug("%s: id clock %d has been enabled\n", __func__, (u32)clk->id);
1137
1138         return 0;
1139 }
1140
1141 static int stm32mp1_clk_disable(struct clk *clk)
1142 {
1143         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1144         const struct stm32mp1_clk_gate *gate = priv->data->gate;
1145         int i = stm32mp1_clk_get_id(priv, clk->id);
1146
1147         if (i < 0)
1148                 return i;
1149
1150         if (gate[i].set_clr)
1151                 writel(BIT(gate[i].bit),
1152                        priv->base + gate[i].offset
1153                        + RCC_MP_ENCLRR_OFFSET);
1154         else
1155                 clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1156
1157         debug("%s: id clock %d has been disabled\n", __func__, (u32)clk->id);
1158
1159         return 0;
1160 }
1161
1162 static ulong stm32mp1_clk_get_rate(struct clk *clk)
1163 {
1164         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1165         int p = stm32mp1_clk_get_parent(priv, clk->id);
1166         ulong rate;
1167
1168         if (p < 0)
1169                 return 0;
1170
1171         rate = stm32mp1_clk_get(priv, p);
1172
1173 #ifdef DEBUG
1174         debug("%s: computed rate for id clock %d is %d (parent is %s)\n",
1175               __func__, (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]);
1176 #endif
1177         return rate;
1178 }
1179
1180 #ifdef STM32MP1_CLOCK_TREE_INIT
1181 static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset,
1182                                 u32 mask_on)
1183 {
1184         u32 address = rcc + offset;
1185
1186         if (enable)
1187                 setbits_le32(address, mask_on);
1188         else
1189                 clrbits_le32(address, mask_on);
1190 }
1191
1192 static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on)
1193 {
1194         writel(mask_on, rcc + (enable ? RCC_OCENSETR : RCC_OCENCLRR));
1195 }
1196
1197 static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset,
1198                              u32 mask_rdy)
1199 {
1200         u32 mask_test = 0;
1201         u32 address = rcc + offset;
1202         u32 val;
1203         int ret;
1204
1205         if (enable)
1206                 mask_test = mask_rdy;
1207
1208         ret = readl_poll_timeout(address, val,
1209                                  (val & mask_rdy) == mask_test,
1210                                  TIMEOUT_1S);
1211
1212         if (ret)
1213                 pr_err("OSC %x @ %x timeout for enable=%d : 0x%x\n",
1214                        mask_rdy, address, enable, readl(address));
1215
1216         return ret;
1217 }
1218
1219 static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int digbyp,
1220                                 int lsedrv)
1221 {
1222         u32 value;
1223
1224         if (digbyp)
1225                 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_DIGBYP);
1226
1227         if (bypass || digbyp)
1228                 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP);
1229
1230         /*
1231          * warning: not recommended to switch directly from "high drive"
1232          * to "medium low drive", and vice-versa.
1233          */
1234         value = (readl(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK)
1235                 >> RCC_BDCR_LSEDRV_SHIFT;
1236
1237         while (value != lsedrv) {
1238                 if (value > lsedrv)
1239                         value--;
1240                 else
1241                         value++;
1242
1243                 clrsetbits_le32(rcc + RCC_BDCR,
1244                                 RCC_BDCR_LSEDRV_MASK,
1245                                 value << RCC_BDCR_LSEDRV_SHIFT);
1246         }
1247
1248         stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON);
1249 }
1250
1251 static void stm32mp1_lse_wait(fdt_addr_t rcc)
1252 {
1253         stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY);
1254 }
1255
1256 static void stm32mp1_lsi_set(fdt_addr_t rcc, int enable)
1257 {
1258         stm32mp1_ls_osc_set(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSION);
1259         stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY);
1260 }
1261
1262 static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int digbyp, int css)
1263 {
1264         if (digbyp)
1265                 writel(RCC_OCENR_DIGBYP, rcc + RCC_OCENSETR);
1266         if (bypass || digbyp)
1267                 writel(RCC_OCENR_HSEBYP, rcc + RCC_OCENSETR);
1268
1269         stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON);
1270         stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY);
1271
1272         if (css)
1273                 writel(RCC_OCENR_HSECSSON, rcc + RCC_OCENSETR);
1274 }
1275
1276 static void stm32mp1_csi_set(fdt_addr_t rcc, int enable)
1277 {
1278         stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_CSION);
1279         stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY);
1280 }
1281
1282 static void stm32mp1_hsi_set(fdt_addr_t rcc, int enable)
1283 {
1284         stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_HSION);
1285         stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_HSIRDY);
1286 }
1287
1288 static int stm32mp1_set_hsidiv(fdt_addr_t rcc, u8 hsidiv)
1289 {
1290         u32 address = rcc + RCC_OCRDYR;
1291         u32 val;
1292         int ret;
1293
1294         clrsetbits_le32(rcc + RCC_HSICFGR,
1295                         RCC_HSICFGR_HSIDIV_MASK,
1296                         RCC_HSICFGR_HSIDIV_MASK & hsidiv);
1297
1298         ret = readl_poll_timeout(address, val,
1299                                  val & RCC_OCRDYR_HSIDIVRDY,
1300                                  TIMEOUT_200MS);
1301         if (ret)
1302                 pr_err("HSIDIV failed @ 0x%x: 0x%x\n",
1303                        address, readl(address));
1304
1305         return ret;
1306 }
1307
1308 static int stm32mp1_hsidiv(fdt_addr_t rcc, ulong hsifreq)
1309 {
1310         u8 hsidiv;
1311         u32 hsidivfreq = MAX_HSI_HZ;
1312
1313         for (hsidiv = 0; hsidiv < 4; hsidiv++,
1314              hsidivfreq = hsidivfreq / 2)
1315                 if (hsidivfreq == hsifreq)
1316                         break;
1317
1318         if (hsidiv == 4) {
1319                 pr_err("clk-hsi frequency invalid");
1320                 return -1;
1321         }
1322
1323         if (hsidiv > 0)
1324                 return stm32mp1_set_hsidiv(rcc, hsidiv);
1325
1326         return 0;
1327 }
1328
1329 static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id)
1330 {
1331         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1332
1333         clrsetbits_le32(priv->base + pll[pll_id].pllxcr,
1334                         RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN |
1335                         RCC_PLLNCR_DIVREN,
1336                         RCC_PLLNCR_PLLON);
1337 }
1338
1339 static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output)
1340 {
1341         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1342         u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1343         u32 val;
1344         int ret;
1345
1346         ret = readl_poll_timeout(pllxcr, val, val & RCC_PLLNCR_PLLRDY,
1347                                  TIMEOUT_200MS);
1348
1349         if (ret) {
1350                 pr_err("PLL%d start failed @ 0x%x: 0x%x\n",
1351                        pll_id, pllxcr, readl(pllxcr));
1352                 return ret;
1353         }
1354
1355         /* start the requested output */
1356         setbits_le32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT);
1357
1358         return 0;
1359 }
1360
1361 static int pll_stop(struct stm32mp1_clk_priv *priv, int pll_id)
1362 {
1363         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1364         u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1365         u32 val;
1366
1367         /* stop all output */
1368         clrbits_le32(pllxcr,
1369                      RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN);
1370
1371         /* stop PLL */
1372         clrbits_le32(pllxcr, RCC_PLLNCR_PLLON);
1373
1374         /* wait PLL stopped */
1375         return readl_poll_timeout(pllxcr, val, (val & RCC_PLLNCR_PLLRDY) == 0,
1376                                   TIMEOUT_200MS);
1377 }
1378
1379 static void pll_config_output(struct stm32mp1_clk_priv *priv,
1380                               int pll_id, u32 *pllcfg)
1381 {
1382         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1383         fdt_addr_t rcc = priv->base;
1384         u32 value;
1385
1386         value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT)
1387                 & RCC_PLLNCFGR2_DIVP_MASK;
1388         value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT)
1389                  & RCC_PLLNCFGR2_DIVQ_MASK;
1390         value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT)
1391                  & RCC_PLLNCFGR2_DIVR_MASK;
1392         writel(value, rcc + pll[pll_id].pllxcfgr2);
1393 }
1394
1395 static int pll_config(struct stm32mp1_clk_priv *priv, int pll_id,
1396                       u32 *pllcfg, u32 fracv)
1397 {
1398         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1399         fdt_addr_t rcc = priv->base;
1400         enum stm32mp1_plltype type = pll[pll_id].plltype;
1401         int src;
1402         ulong refclk;
1403         u8 ifrge = 0;
1404         u32 value;
1405
1406         src = readl(priv->base + pll[pll_id].rckxselr) & RCC_SELR_SRC_MASK;
1407
1408         refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]) /
1409                  (pllcfg[PLLCFG_M] + 1);
1410
1411         if (refclk < (stm32mp1_pll[type].refclk_min * 1000000) ||
1412             refclk > (stm32mp1_pll[type].refclk_max * 1000000)) {
1413                 debug("invalid refclk = %x\n", (u32)refclk);
1414                 return -EINVAL;
1415         }
1416         if (type == PLL_800 && refclk >= 8000000)
1417                 ifrge = 1;
1418
1419         value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT)
1420                  & RCC_PLLNCFGR1_DIVN_MASK;
1421         value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT)
1422                  & RCC_PLLNCFGR1_DIVM_MASK;
1423         value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT)
1424                  & RCC_PLLNCFGR1_IFRGE_MASK;
1425         writel(value, rcc + pll[pll_id].pllxcfgr1);
1426
1427         /* fractional configuration: load sigma-delta modulator (SDM) */
1428
1429         /* Write into FRACV the new fractional value , and FRACLE to 0 */
1430         writel(fracv << RCC_PLLNFRACR_FRACV_SHIFT,
1431                rcc + pll[pll_id].pllxfracr);
1432
1433         /* Write FRACLE to 1 : FRACV value is loaded into the SDM */
1434         setbits_le32(rcc + pll[pll_id].pllxfracr,
1435                      RCC_PLLNFRACR_FRACLE);
1436
1437         pll_config_output(priv, pll_id, pllcfg);
1438
1439         return 0;
1440 }
1441
1442 static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg)
1443 {
1444         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1445         u32 pllxcsg;
1446
1447         pllxcsg = ((csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) &
1448                     RCC_PLLNCSGR_MOD_PER_MASK) |
1449                   ((csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) &
1450                     RCC_PLLNCSGR_INC_STEP_MASK) |
1451                   ((csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) &
1452                     RCC_PLLNCSGR_SSCG_MODE_MASK);
1453
1454         writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr);
1455
1456         setbits_le32(priv->base + pll[pll_id].pllxcr, RCC_PLLNCR_SSCG_CTRL);
1457 }
1458
1459 static  __maybe_unused int pll_set_rate(struct udevice *dev,
1460                                         int pll_id,
1461                                         int div_id,
1462                                         unsigned long clk_rate)
1463 {
1464         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1465         unsigned int pllcfg[PLLCFG_NB];
1466         ofnode plloff;
1467         char name[12];
1468         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1469         enum stm32mp1_plltype type = pll[pll_id].plltype;
1470         int divm, divn, divy;
1471         int ret;
1472         ulong fck_ref;
1473         u32 fracv;
1474         u64 value;
1475
1476         if (div_id > _DIV_NB)
1477                 return -EINVAL;
1478
1479         sprintf(name, "st,pll@%d", pll_id);
1480         plloff = dev_read_subnode(dev, name);
1481         if (!ofnode_valid(plloff))
1482                 return -FDT_ERR_NOTFOUND;
1483
1484         ret = ofnode_read_u32_array(plloff, "cfg",
1485                                     pllcfg, PLLCFG_NB);
1486         if (ret < 0)
1487                 return -FDT_ERR_NOTFOUND;
1488
1489         fck_ref = pll_get_fref_ck(priv, pll_id);
1490
1491         divm = pllcfg[PLLCFG_M];
1492         /* select output divider = 0: for _DIV_P, 1:_DIV_Q 2:_DIV_R */
1493         divy = pllcfg[PLLCFG_P + div_id];
1494
1495         /* For: PLL1 & PLL2 => VCO is * 2 but ck_pll_y is also / 2
1496          * So same final result than PLL2 et 4
1497          * with FRACV
1498          * Fck_pll_y = Fck_ref * ((DIVN + 1) + FRACV / 2^13)
1499          *             / (DIVy + 1) * (DIVM + 1)
1500          * value = (DIVN + 1) * 2^13 + FRACV / 2^13
1501          *       = Fck_pll_y (DIVy + 1) * (DIVM + 1) * 2^13 / Fck_ref
1502          */
1503         value = ((u64)clk_rate * (divy + 1) * (divm + 1)) << 13;
1504         value = lldiv(value, fck_ref);
1505
1506         divn = (value >> 13) - 1;
1507         if (divn < DIVN_MIN ||
1508             divn > stm32mp1_pll[type].divn_max) {
1509                 pr_err("divn invalid = %d", divn);
1510                 return -EINVAL;
1511         }
1512         fracv = value - ((divn + 1) << 13);
1513         pllcfg[PLLCFG_N] = divn;
1514
1515         /* reconfigure PLL */
1516         pll_stop(priv, pll_id);
1517         pll_config(priv, pll_id, pllcfg, fracv);
1518         pll_start(priv, pll_id);
1519         pll_output(priv, pll_id, pllcfg[PLLCFG_O]);
1520
1521         return 0;
1522 }
1523
1524 static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc)
1525 {
1526         u32 address = priv->base + (clksrc >> 4);
1527         u32 val;
1528         int ret;
1529
1530         clrsetbits_le32(address, RCC_SELR_SRC_MASK, clksrc & RCC_SELR_SRC_MASK);
1531         ret = readl_poll_timeout(address, val, val & RCC_SELR_SRCRDY,
1532                                  TIMEOUT_200MS);
1533         if (ret)
1534                 pr_err("CLKSRC %x start failed @ 0x%x: 0x%x\n",
1535                        clksrc, address, readl(address));
1536
1537         return ret;
1538 }
1539
1540 static void stgen_config(struct stm32mp1_clk_priv *priv)
1541 {
1542         int p;
1543         u32 stgenc, cntfid0;
1544         ulong rate;
1545
1546         stgenc = STM32_STGEN_BASE;
1547         cntfid0 = readl(stgenc + STGENC_CNTFID0);
1548         p = stm32mp1_clk_get_parent(priv, STGEN_K);
1549         rate = stm32mp1_clk_get(priv, p);
1550
1551         if (cntfid0 != rate) {
1552                 u64 counter;
1553
1554                 pr_debug("System Generic Counter (STGEN) update\n");
1555                 clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1556                 counter = (u64)readl(stgenc + STGENC_CNTCVL);
1557                 counter |= ((u64)(readl(stgenc + STGENC_CNTCVU))) << 32;
1558                 counter = lldiv(counter * (u64)rate, cntfid0);
1559                 writel((u32)counter, stgenc + STGENC_CNTCVL);
1560                 writel((u32)(counter >> 32), stgenc + STGENC_CNTCVU);
1561                 writel(rate, stgenc + STGENC_CNTFID0);
1562                 setbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1563
1564                 __asm__ volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (rate));
1565
1566                 /* need to update gd->arch.timer_rate_hz with new frequency */
1567                 timer_init();
1568         }
1569 }
1570
1571 static int set_clkdiv(unsigned int clkdiv, u32 address)
1572 {
1573         u32 val;
1574         int ret;
1575
1576         clrsetbits_le32(address, RCC_DIVR_DIV_MASK, clkdiv & RCC_DIVR_DIV_MASK);
1577         ret = readl_poll_timeout(address, val, val & RCC_DIVR_DIVRDY,
1578                                  TIMEOUT_200MS);
1579         if (ret)
1580                 pr_err("CLKDIV %x start failed @ 0x%x: 0x%x\n",
1581                        clkdiv, address, readl(address));
1582
1583         return ret;
1584 }
1585
1586 static void stm32mp1_mco_csg(struct stm32mp1_clk_priv *priv,
1587                              u32 clksrc, u32 clkdiv)
1588 {
1589         u32 address = priv->base + (clksrc >> 4);
1590
1591         /*
1592          * binding clksrc : bit15-4 offset
1593          *                  bit3:   disable
1594          *                  bit2-0: MCOSEL[2:0]
1595          */
1596         if (clksrc & 0x8) {
1597                 clrbits_le32(address, RCC_MCOCFG_MCOON);
1598         } else {
1599                 clrsetbits_le32(address,
1600                                 RCC_MCOCFG_MCOSRC_MASK,
1601                                 clksrc & RCC_MCOCFG_MCOSRC_MASK);
1602                 clrsetbits_le32(address,
1603                                 RCC_MCOCFG_MCODIV_MASK,
1604                                 clkdiv << RCC_MCOCFG_MCODIV_SHIFT);
1605                 setbits_le32(address, RCC_MCOCFG_MCOON);
1606         }
1607 }
1608
1609 static void set_rtcsrc(struct stm32mp1_clk_priv *priv,
1610                        unsigned int clksrc,
1611                        int lse_css)
1612 {
1613         u32 address = priv->base + RCC_BDCR;
1614
1615         if (readl(address) & RCC_BDCR_RTCCKEN)
1616                 goto skip_rtc;
1617
1618         if (clksrc == CLK_RTC_DISABLED)
1619                 goto skip_rtc;
1620
1621         clrsetbits_le32(address,
1622                         RCC_BDCR_RTCSRC_MASK,
1623                         clksrc << RCC_BDCR_RTCSRC_SHIFT);
1624
1625         setbits_le32(address, RCC_BDCR_RTCCKEN);
1626
1627 skip_rtc:
1628         if (lse_css)
1629                 setbits_le32(address, RCC_BDCR_LSECSSON);
1630 }
1631
1632 static void pkcs_config(struct stm32mp1_clk_priv *priv, u32 pkcs)
1633 {
1634         u32 address = priv->base + ((pkcs >> 4) & 0xFFF);
1635         u32 value = pkcs & 0xF;
1636         u32 mask = 0xF;
1637
1638         if (pkcs & BIT(31)) {
1639                 mask <<= 4;
1640                 value <<= 4;
1641         }
1642         clrsetbits_le32(address, mask, value);
1643 }
1644
1645 static int stm32mp1_clktree(struct udevice *dev)
1646 {
1647         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1648         fdt_addr_t rcc = priv->base;
1649         unsigned int clksrc[CLKSRC_NB];
1650         unsigned int clkdiv[CLKDIV_NB];
1651         unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
1652         ofnode plloff[_PLL_NB];
1653         int ret;
1654         int i, len;
1655         int lse_css = 0;
1656         const u32 *pkcs_cell;
1657
1658         /* check mandatory field */
1659         ret = dev_read_u32_array(dev, "st,clksrc", clksrc, CLKSRC_NB);
1660         if (ret < 0) {
1661                 debug("field st,clksrc invalid: error %d\n", ret);
1662                 return -FDT_ERR_NOTFOUND;
1663         }
1664
1665         ret = dev_read_u32_array(dev, "st,clkdiv", clkdiv, CLKDIV_NB);
1666         if (ret < 0) {
1667                 debug("field st,clkdiv invalid: error %d\n", ret);
1668                 return -FDT_ERR_NOTFOUND;
1669         }
1670
1671         /* check mandatory field in each pll */
1672         for (i = 0; i < _PLL_NB; i++) {
1673                 char name[12];
1674
1675                 sprintf(name, "st,pll@%d", i);
1676                 plloff[i] = dev_read_subnode(dev, name);
1677                 if (!ofnode_valid(plloff[i]))
1678                         continue;
1679                 ret = ofnode_read_u32_array(plloff[i], "cfg",
1680                                             pllcfg[i], PLLCFG_NB);
1681                 if (ret < 0) {
1682                         debug("field cfg invalid: error %d\n", ret);
1683                         return -FDT_ERR_NOTFOUND;
1684                 }
1685         }
1686
1687         debug("configuration MCO\n");
1688         stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]);
1689         stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]);
1690
1691         debug("switch ON osillator\n");
1692         /*
1693          * switch ON oscillator found in device-tree,
1694          * HSI already ON after bootrom
1695          */
1696         if (priv->osc[_LSI])
1697                 stm32mp1_lsi_set(rcc, 1);
1698
1699         if (priv->osc[_LSE]) {
1700                 int bypass, digbyp, lsedrv;
1701                 struct udevice *dev = priv->osc_dev[_LSE];
1702
1703                 bypass = dev_read_bool(dev, "st,bypass");
1704                 digbyp = dev_read_bool(dev, "st,digbypass");
1705                 lse_css = dev_read_bool(dev, "st,css");
1706                 lsedrv = dev_read_u32_default(dev, "st,drive",
1707                                               LSEDRV_MEDIUM_HIGH);
1708
1709                 stm32mp1_lse_enable(rcc, bypass, digbyp, lsedrv);
1710         }
1711
1712         if (priv->osc[_HSE]) {
1713                 int bypass, digbyp, css;
1714                 struct udevice *dev = priv->osc_dev[_HSE];
1715
1716                 bypass = dev_read_bool(dev, "st,bypass");
1717                 digbyp = dev_read_bool(dev, "st,digbypass");
1718                 css = dev_read_bool(dev, "st,css");
1719
1720                 stm32mp1_hse_enable(rcc, bypass, digbyp, css);
1721         }
1722         /* CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR)
1723          * => switch on CSI even if node is not present in device tree
1724          */
1725         stm32mp1_csi_set(rcc, 1);
1726
1727         /* come back to HSI */
1728         debug("come back to HSI\n");
1729         set_clksrc(priv, CLK_MPU_HSI);
1730         set_clksrc(priv, CLK_AXI_HSI);
1731         set_clksrc(priv, CLK_MCU_HSI);
1732
1733         debug("pll stop\n");
1734         for (i = 0; i < _PLL_NB; i++)
1735                 pll_stop(priv, i);
1736
1737         /* configure HSIDIV */
1738         debug("configure HSIDIV\n");
1739         if (priv->osc[_HSI]) {
1740                 stm32mp1_hsidiv(rcc, priv->osc[_HSI]);
1741                 stgen_config(priv);
1742         }
1743
1744         /* select DIV */
1745         debug("select DIV\n");
1746         /* no ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */
1747         writel(clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK, rcc + RCC_MPCKDIVR);
1748         set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR);
1749         set_clkdiv(clkdiv[CLKDIV_APB4], rcc + RCC_APB4DIVR);
1750         set_clkdiv(clkdiv[CLKDIV_APB5], rcc + RCC_APB5DIVR);
1751         set_clkdiv(clkdiv[CLKDIV_MCU], rcc + RCC_MCUDIVR);
1752         set_clkdiv(clkdiv[CLKDIV_APB1], rcc + RCC_APB1DIVR);
1753         set_clkdiv(clkdiv[CLKDIV_APB2], rcc + RCC_APB2DIVR);
1754         set_clkdiv(clkdiv[CLKDIV_APB3], rcc + RCC_APB3DIVR);
1755
1756         /* no ready bit for RTC */
1757         writel(clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK, rcc + RCC_RTCDIVR);
1758
1759         /* configure PLLs source */
1760         debug("configure PLLs source\n");
1761         set_clksrc(priv, clksrc[CLKSRC_PLL12]);
1762         set_clksrc(priv, clksrc[CLKSRC_PLL3]);
1763         set_clksrc(priv, clksrc[CLKSRC_PLL4]);
1764
1765         /* configure and start PLLs */
1766         debug("configure PLLs\n");
1767         for (i = 0; i < _PLL_NB; i++) {
1768                 u32 fracv;
1769                 u32 csg[PLLCSG_NB];
1770
1771                 debug("configure PLL %d @ %d\n", i,
1772                       ofnode_to_offset(plloff[i]));
1773                 if (!ofnode_valid(plloff[i]))
1774                         continue;
1775
1776                 fracv = ofnode_read_u32_default(plloff[i], "frac", 0);
1777                 pll_config(priv, i, pllcfg[i], fracv);
1778                 ret = ofnode_read_u32_array(plloff[i], "csg", csg, PLLCSG_NB);
1779                 if (!ret) {
1780                         pll_csg(priv, i, csg);
1781                 } else if (ret != -FDT_ERR_NOTFOUND) {
1782                         debug("invalid csg node for pll@%d res=%d\n", i, ret);
1783                         return ret;
1784                 }
1785                 pll_start(priv, i);
1786         }
1787
1788         /* wait and start PLLs ouptut when ready */
1789         for (i = 0; i < _PLL_NB; i++) {
1790                 if (!ofnode_valid(plloff[i]))
1791                         continue;
1792                 debug("output PLL %d\n", i);
1793                 pll_output(priv, i, pllcfg[i][PLLCFG_O]);
1794         }
1795
1796         /* wait LSE ready before to use it */
1797         if (priv->osc[_LSE])
1798                 stm32mp1_lse_wait(rcc);
1799
1800         /* configure with expected clock source */
1801         debug("CLKSRC\n");
1802         set_clksrc(priv, clksrc[CLKSRC_MPU]);
1803         set_clksrc(priv, clksrc[CLKSRC_AXI]);
1804         set_clksrc(priv, clksrc[CLKSRC_MCU]);
1805         set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css);
1806
1807         /* configure PKCK */
1808         debug("PKCK\n");
1809         pkcs_cell = dev_read_prop(dev, "st,pkcs", &len);
1810         if (pkcs_cell) {
1811                 bool ckper_disabled = false;
1812
1813                 for (i = 0; i < len / sizeof(u32); i++) {
1814                         u32 pkcs = (u32)fdt32_to_cpu(pkcs_cell[i]);
1815
1816                         if (pkcs == CLK_CKPER_DISABLED) {
1817                                 ckper_disabled = true;
1818                                 continue;
1819                         }
1820                         pkcs_config(priv, pkcs);
1821                 }
1822                 /* CKPER is source for some peripheral clock
1823                  * (FMC-NAND / QPSI-NOR) and switching source is allowed
1824                  * only if previous clock is still ON
1825                  * => deactivated CKPER only after switching clock
1826                  */
1827                 if (ckper_disabled)
1828                         pkcs_config(priv, CLK_CKPER_DISABLED);
1829         }
1830
1831         /* STGEN clock source can change with CLK_STGEN_XXX */
1832         stgen_config(priv);
1833
1834         debug("oscillator off\n");
1835         /* switch OFF HSI if not found in device-tree */
1836         if (!priv->osc[_HSI])
1837                 stm32mp1_hsi_set(rcc, 0);
1838
1839         /* Software Self-Refresh mode (SSR) during DDR initilialization */
1840         clrsetbits_le32(priv->base + RCC_DDRITFCR,
1841                         RCC_DDRITFCR_DDRCKMOD_MASK,
1842                         RCC_DDRITFCR_DDRCKMOD_SSR <<
1843                         RCC_DDRITFCR_DDRCKMOD_SHIFT);
1844
1845         return 0;
1846 }
1847 #endif /* STM32MP1_CLOCK_TREE_INIT */
1848
1849 static int pll_set_output_rate(struct udevice *dev,
1850                                int pll_id,
1851                                int div_id,
1852                                unsigned long clk_rate)
1853 {
1854         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1855         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1856         u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1857         int div;
1858         ulong fvco;
1859
1860         if (div_id > _DIV_NB)
1861                 return -EINVAL;
1862
1863         fvco = pll_get_fvco(priv, pll_id);
1864
1865         if (fvco <= clk_rate)
1866                 div = 1;
1867         else
1868                 div = DIV_ROUND_UP(fvco, clk_rate);
1869
1870         if (div > 128)
1871                 div = 128;
1872
1873         /* stop the requested output */
1874         clrbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
1875         /* change divider */
1876         clrsetbits_le32(priv->base + pll[pll_id].pllxcfgr2,
1877                         RCC_PLLNCFGR2_DIVX_MASK << RCC_PLLNCFGR2_SHIFT(div_id),
1878                         (div - 1) << RCC_PLLNCFGR2_SHIFT(div_id));
1879         /* start the requested output */
1880         setbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
1881
1882         return 0;
1883 }
1884
1885 static ulong stm32mp1_clk_set_rate(struct clk *clk, unsigned long clk_rate)
1886 {
1887         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1888         int p;
1889
1890         switch (clk->id) {
1891 #if defined(STM32MP1_CLOCK_TREE_INIT) && \
1892         defined(CONFIG_STM32MP1_DDR_INTERACTIVE)
1893         case DDRPHYC:
1894                 break;
1895 #endif
1896         case LTDC_PX:
1897         case DSI_PX:
1898                 break;
1899         default:
1900                 pr_err("not supported");
1901                 return -EINVAL;
1902         }
1903
1904         p = stm32mp1_clk_get_parent(priv, clk->id);
1905 #ifdef DEBUG
1906         debug("%s: parent = %d:%s\n", __func__, p, stm32mp1_clk_parent_name[p]);
1907 #endif
1908         if (p < 0)
1909                 return -EINVAL;
1910
1911         switch (p) {
1912 #if defined(STM32MP1_CLOCK_TREE_INIT) && \
1913         defined(CONFIG_STM32MP1_DDR_INTERACTIVE)
1914         case _PLL2_R: /* DDRPHYC */
1915         {
1916                 /* only for change DDR clock in interactive mode */
1917                 ulong result;
1918
1919                 set_clksrc(priv, CLK_AXI_HSI);
1920                 result = pll_set_rate(clk->dev,  _PLL2, _DIV_R, clk_rate);
1921                 set_clksrc(priv, CLK_AXI_PLL2P);
1922                 return result;
1923         }
1924 #endif
1925
1926         case _PLL4_Q:
1927                 /* for LTDC_PX and DSI_PX case */
1928                 return pll_set_output_rate(clk->dev, _PLL4, _DIV_Q, clk_rate);
1929         }
1930
1931         return -EINVAL;
1932 }
1933
1934 static void stm32mp1_osc_clk_init(const char *name,
1935                                   struct stm32mp1_clk_priv *priv,
1936                                   int index)
1937 {
1938         struct clk clk;
1939         struct udevice *dev = NULL;
1940
1941         priv->osc[index] = 0;
1942         clk.id = 0;
1943         if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) {
1944                 if (clk_request(dev, &clk))
1945                         pr_err("%s request", name);
1946                 else
1947                         priv->osc[index] = clk_get_rate(&clk);
1948         }
1949         priv->osc_dev[index] = dev;
1950 }
1951
1952 static void stm32mp1_osc_init(struct udevice *dev)
1953 {
1954         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1955         int i;
1956         const char *name[NB_OSC] = {
1957                 [_LSI] = "clk-lsi",
1958                 [_LSE] = "clk-lse",
1959                 [_HSI] = "clk-hsi",
1960                 [_HSE] = "clk-hse",
1961                 [_CSI] = "clk-csi",
1962                 [_I2S_CKIN] = "i2s_ckin",
1963         };
1964
1965         for (i = 0; i < NB_OSC; i++) {
1966                 stm32mp1_osc_clk_init(name[i], priv, i);
1967                 debug("%d: %s => %x\n", i, name[i], (u32)priv->osc[i]);
1968         }
1969 }
1970
1971 static void  __maybe_unused stm32mp1_clk_dump(struct stm32mp1_clk_priv *priv)
1972 {
1973         char buf[32];
1974         int i, s, p;
1975
1976         printf("Clocks:\n");
1977         for (i = 0; i < _PARENT_NB; i++) {
1978                 printf("- %s : %s MHz\n",
1979                        stm32mp1_clk_parent_name[i],
1980                        strmhz(buf, stm32mp1_clk_get(priv, i)));
1981         }
1982         printf("Source Clocks:\n");
1983         for (i = 0; i < _PARENT_SEL_NB; i++) {
1984                 p = (readl(priv->base + priv->data->sel[i].offset) >>
1985                      priv->data->sel[i].src) & priv->data->sel[i].msk;
1986                 if (p < priv->data->sel[i].nb_parent) {
1987                         s = priv->data->sel[i].parent[p];
1988                         printf("- %s(%d) => parent %s(%d)\n",
1989                                stm32mp1_clk_parent_sel_name[i], i,
1990                                stm32mp1_clk_parent_name[s], s);
1991                 } else {
1992                         printf("- %s(%d) => parent index %d is invalid\n",
1993                                stm32mp1_clk_parent_sel_name[i], i, p);
1994                 }
1995         }
1996 }
1997
1998 #ifdef CONFIG_CMD_CLK
1999 int soc_clk_dump(void)
2000 {
2001         struct udevice *dev;
2002         struct stm32mp1_clk_priv *priv;
2003         int ret;
2004
2005         ret = uclass_get_device_by_driver(UCLASS_CLK,
2006                                           DM_GET_DRIVER(stm32mp1_clock),
2007                                           &dev);
2008         if (ret)
2009                 return ret;
2010
2011         priv = dev_get_priv(dev);
2012
2013         stm32mp1_clk_dump(priv);
2014
2015         return 0;
2016 }
2017 #endif
2018
2019 static int stm32mp1_clk_probe(struct udevice *dev)
2020 {
2021         int result = 0;
2022         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
2023
2024         priv->base = dev_read_addr(dev->parent);
2025         if (priv->base == FDT_ADDR_T_NONE)
2026                 return -EINVAL;
2027
2028         priv->data = (void *)&stm32mp1_data;
2029
2030         if (!priv->data->gate || !priv->data->sel ||
2031             !priv->data->pll)
2032                 return -EINVAL;
2033
2034         stm32mp1_osc_init(dev);
2035
2036 #ifdef STM32MP1_CLOCK_TREE_INIT
2037         /* clock tree init is done only one time, before relocation */
2038         if (!(gd->flags & GD_FLG_RELOC))
2039                 result = stm32mp1_clktree(dev);
2040 #endif
2041
2042 #ifndef CONFIG_SPL_BUILD
2043 #if defined(DEBUG)
2044         /* display debug information for probe after relocation */
2045         if (gd->flags & GD_FLG_RELOC)
2046                 stm32mp1_clk_dump(priv);
2047 #endif
2048
2049         gd->cpu_clk = stm32mp1_clk_get(priv, _CK_MPU);
2050         gd->bus_clk = stm32mp1_clk_get(priv, _ACLK);
2051         /* DDRPHYC father */
2052         gd->mem_clk = stm32mp1_clk_get(priv, _PLL2_R);
2053 #if defined(CONFIG_DISPLAY_CPUINFO)
2054         if (gd->flags & GD_FLG_RELOC) {
2055                 char buf[32];
2056
2057                 printf("Clocks:\n");
2058                 printf("- MPU : %s MHz\n", strmhz(buf, gd->cpu_clk));
2059                 printf("- MCU : %s MHz\n",
2060                        strmhz(buf, stm32mp1_clk_get(priv, _CK_MCU)));
2061                 printf("- AXI : %s MHz\n", strmhz(buf, gd->bus_clk));
2062                 printf("- PER : %s MHz\n",
2063                        strmhz(buf, stm32mp1_clk_get(priv, _CK_PER)));
2064                 printf("- DDR : %s MHz\n", strmhz(buf, gd->mem_clk));
2065         }
2066 #endif /* CONFIG_DISPLAY_CPUINFO */
2067 #endif
2068
2069         return result;
2070 }
2071
2072 static const struct clk_ops stm32mp1_clk_ops = {
2073         .enable = stm32mp1_clk_enable,
2074         .disable = stm32mp1_clk_disable,
2075         .get_rate = stm32mp1_clk_get_rate,
2076         .set_rate = stm32mp1_clk_set_rate,
2077 };
2078
2079 U_BOOT_DRIVER(stm32mp1_clock) = {
2080         .name = "stm32mp1_clk",
2081         .id = UCLASS_CLK,
2082         .ops = &stm32mp1_clk_ops,
2083         .priv_auto_alloc_size = sizeof(struct stm32mp1_clk_priv),
2084         .probe = stm32mp1_clk_probe,
2085 };