drivers/clk/clk_stm32mp1.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   4  */
   5
   6 #include <common.h>
   7 #include <clk-uclass.h>
   8 #include <div64.h>
   9 #include <dm.h>
  10 #include <regmap.h>
  11 #include <spl.h>
  12 #include <syscon.h>
  13 #include <linux/io.h>
  14 #include <linux/iopoll.h>
  15 #include <dt-bindings/clock/stm32mp1-clks.h>
  16 #include <dt-bindings/clock/stm32mp1-clksrc.h>
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 #ifndef CONFIG_STM32MP1_TRUSTED
  21 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
  22 /* activate clock tree initialization in the driver */
  23 #define STM32MP1_CLOCK_TREE_INIT
  24 #endif
  25 #endif
  26
  27 #define MAX_HSI_HZ              64000000
  28
  29 /* TIMEOUT */
  30 #define TIMEOUT_200MS           200000
  31 #define TIMEOUT_1S              1000000
  32
  33 /* STGEN registers */
  34 #define STGENC_CNTCR            0x00
  35 #define STGENC_CNTSR            0x04
  36 #define STGENC_CNTCVL           0x08
  37 #define STGENC_CNTCVU           0x0C
  38 #define STGENC_CNTFID0          0x20
  39
  40 #define STGENC_CNTCR_EN         BIT(0)
  41
  42 /* RCC registers */
  43 #define RCC_OCENSETR            0x0C
  44 #define RCC_OCENCLRR            0x10
  45 #define RCC_HSICFGR             0x18
  46 #define RCC_MPCKSELR            0x20
  47 #define RCC_ASSCKSELR           0x24
  48 #define RCC_RCK12SELR           0x28
  49 #define RCC_MPCKDIVR            0x2C
  50 #define RCC_AXIDIVR             0x30
  51 #define RCC_APB4DIVR            0x3C
  52 #define RCC_APB5DIVR            0x40
  53 #define RCC_RTCDIVR             0x44
  54 #define RCC_MSSCKSELR           0x48
  55 #define RCC_PLL1CR              0x80
  56 #define RCC_PLL1CFGR1           0x84
  57 #define RCC_PLL1CFGR2           0x88
  58 #define RCC_PLL1FRACR           0x8C
  59 #define RCC_PLL1CSGR            0x90
  60 #define RCC_PLL2CR              0x94
  61 #define RCC_PLL2CFGR1           0x98
  62 #define RCC_PLL2CFGR2           0x9C
  63 #define RCC_PLL2FRACR           0xA0
  64 #define RCC_PLL2CSGR            0xA4
  65 #define RCC_I2C46CKSELR         0xC0
  66 #define RCC_CPERCKSELR          0xD0
  67 #define RCC_STGENCKSELR         0xD4
  68 #define RCC_DDRITFCR            0xD8
  69 #define RCC_BDCR                0x140
  70 #define RCC_RDLSICR             0x144
  71 #define RCC_MP_APB4ENSETR       0x200
  72 #define RCC_MP_APB5ENSETR       0x208
  73 #define RCC_MP_AHB5ENSETR       0x210
  74 #define RCC_MP_AHB6ENSETR       0x218
  75 #define RCC_OCRDYR              0x808
  76 #define RCC_DBGCFGR             0x80C
  77 #define RCC_RCK3SELR            0x820
  78 #define RCC_RCK4SELR            0x824
  79 #define RCC_MCUDIVR             0x830
  80 #define RCC_APB1DIVR            0x834
  81 #define RCC_APB2DIVR            0x838
  82 #define RCC_APB3DIVR            0x83C
  83 #define RCC_PLL3CR              0x880
  84 #define RCC_PLL3CFGR1           0x884
  85 #define RCC_PLL3CFGR2           0x888
  86 #define RCC_PLL3FRACR           0x88C
  87 #define RCC_PLL3CSGR            0x890
  88 #define RCC_PLL4CR              0x894
  89 #define RCC_PLL4CFGR1           0x898
  90 #define RCC_PLL4CFGR2           0x89C
  91 #define RCC_PLL4FRACR           0x8A0
  92 #define RCC_PLL4CSGR            0x8A4
  93 #define RCC_I2C12CKSELR         0x8C0
  94 #define RCC_I2C35CKSELR         0x8C4
  95 #define RCC_SPI2S1CKSELR        0x8D8
  96 #define RCC_UART6CKSELR         0x8E4
  97 #define RCC_UART24CKSELR        0x8E8
  98 #define RCC_UART35CKSELR        0x8EC
  99 #define RCC_UART78CKSELR        0x8F0
 100 #define RCC_SDMMC12CKSELR       0x8F4
 101 #define RCC_SDMMC3CKSELR        0x8F8
 102 #define RCC_ETHCKSELR           0x8FC
 103 #define RCC_QSPICKSELR          0x900
 104 #define RCC_FMCCKSELR           0x904
 105 #define RCC_USBCKSELR           0x91C
 106 #define RCC_DSICKSELR           0x924
 107 #define RCC_ADCCKSELR           0x928
 108 #define RCC_MP_APB1ENSETR       0xA00
 109 #define RCC_MP_APB2ENSETR       0XA08
 110 #define RCC_MP_APB3ENSETR       0xA10
 111 #define RCC_MP_AHB2ENSETR       0xA18
 112 #define RCC_MP_AHB3ENSETR       0xA20
 113 #define RCC_MP_AHB4ENSETR       0xA28
 114
 115 /* used for most of SELR register */
 116 #define RCC_SELR_SRC_MASK       GENMASK(2, 0)
 117 #define RCC_SELR_SRCRDY         BIT(31)
 118
 119 /* Values of RCC_MPCKSELR register */
 120 #define RCC_MPCKSELR_HSI        0
 121 #define RCC_MPCKSELR_HSE        1
 122 #define RCC_MPCKSELR_PLL        2
 123 #define RCC_MPCKSELR_PLL_MPUDIV 3
 124
 125 /* Values of RCC_ASSCKSELR register */
 126 #define RCC_ASSCKSELR_HSI       0
 127 #define RCC_ASSCKSELR_HSE       1
 128 #define RCC_ASSCKSELR_PLL       2
 129
 130 /* Values of RCC_MSSCKSELR register */
 131 #define RCC_MSSCKSELR_HSI       0
 132 #define RCC_MSSCKSELR_HSE       1
 133 #define RCC_MSSCKSELR_CSI       2
 134 #define RCC_MSSCKSELR_PLL       3
 135
 136 /* Values of RCC_CPERCKSELR register */
 137 #define RCC_CPERCKSELR_HSI      0
 138 #define RCC_CPERCKSELR_CSI      1
 139 #define RCC_CPERCKSELR_HSE      2
 140
 141 /* used for most of DIVR register : max div for RTC */
 142 #define RCC_DIVR_DIV_MASK       GENMASK(5, 0)
 143 #define RCC_DIVR_DIVRDY         BIT(31)
 144
 145 /* Masks for specific DIVR registers */
 146 #define RCC_APBXDIV_MASK        GENMASK(2, 0)
 147 #define RCC_MPUDIV_MASK         GENMASK(2, 0)
 148 #define RCC_AXIDIV_MASK         GENMASK(2, 0)
 149 #define RCC_MCUDIV_MASK         GENMASK(3, 0)
 150
 151 /*  offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
 152 #define RCC_MP_ENCLRR_OFFSET    4
 153
 154 /* Fields of RCC_BDCR register */
 155 #define RCC_BDCR_LSEON          BIT(0)
 156 #define RCC_BDCR_LSEBYP         BIT(1)
 157 #define RCC_BDCR_LSERDY         BIT(2)
 158 #define RCC_BDCR_DIGBYP         BIT(3)
 159 #define RCC_BDCR_LSEDRV_MASK    GENMASK(5, 4)
 160 #define RCC_BDCR_LSEDRV_SHIFT   4
 161 #define RCC_BDCR_LSECSSON       BIT(8)
 162 #define RCC_BDCR_RTCCKEN        BIT(20)
 163 #define RCC_BDCR_RTCSRC_MASK    GENMASK(17, 16)
 164 #define RCC_BDCR_RTCSRC_SHIFT   16
 165
 166 /* Fields of RCC_RDLSICR register */
 167 #define RCC_RDLSICR_LSION       BIT(0)
 168 #define RCC_RDLSICR_LSIRDY      BIT(1)
 169
 170 /* used for ALL PLLNCR registers */
 171 #define RCC_PLLNCR_PLLON        BIT(0)
 172 #define RCC_PLLNCR_PLLRDY       BIT(1)
 173 #define RCC_PLLNCR_SSCG_CTRL    BIT(2)
 174 #define RCC_PLLNCR_DIVPEN       BIT(4)
 175 #define RCC_PLLNCR_DIVQEN       BIT(5)
 176 #define RCC_PLLNCR_DIVREN       BIT(6)
 177 #define RCC_PLLNCR_DIVEN_SHIFT  4
 178
 179 /* used for ALL PLLNCFGR1 registers */
 180 #define RCC_PLLNCFGR1_DIVM_SHIFT        16
 181 #define RCC_PLLNCFGR1_DIVM_MASK         GENMASK(21, 16)
 182 #define RCC_PLLNCFGR1_DIVN_SHIFT        0
 183 #define RCC_PLLNCFGR1_DIVN_MASK         GENMASK(8, 0)
 184 /* only for PLL3 and PLL4 */
 185 #define RCC_PLLNCFGR1_IFRGE_SHIFT       24
 186 #define RCC_PLLNCFGR1_IFRGE_MASK        GENMASK(25, 24)
 187
 188 /* used for ALL PLLNCFGR2 registers , using stm32mp1_div_id */
 189 #define RCC_PLLNCFGR2_SHIFT(div_id)     ((div_id) * 8)
 190 #define RCC_PLLNCFGR2_DIVX_MASK         GENMASK(6, 0)
 191 #define RCC_PLLNCFGR2_DIVP_SHIFT        RCC_PLLNCFGR2_SHIFT(_DIV_P)
 192 #define RCC_PLLNCFGR2_DIVP_MASK         GENMASK(6, 0)
 193 #define RCC_PLLNCFGR2_DIVQ_SHIFT        RCC_PLLNCFGR2_SHIFT(_DIV_Q)
 194 #define RCC_PLLNCFGR2_DIVQ_MASK         GENMASK(14, 8)
 195 #define RCC_PLLNCFGR2_DIVR_SHIFT        RCC_PLLNCFGR2_SHIFT(_DIV_R)
 196 #define RCC_PLLNCFGR2_DIVR_MASK         GENMASK(22, 16)
 197
 198 /* used for ALL PLLNFRACR registers */
 199 #define RCC_PLLNFRACR_FRACV_SHIFT       3
 200 #define RCC_PLLNFRACR_FRACV_MASK        GENMASK(15, 3)
 201 #define RCC_PLLNFRACR_FRACLE            BIT(16)
 202
 203 /* used for ALL PLLNCSGR registers */
 204 #define RCC_PLLNCSGR_INC_STEP_SHIFT     16
 205 #define RCC_PLLNCSGR_INC_STEP_MASK      GENMASK(30, 16)
 206 #define RCC_PLLNCSGR_MOD_PER_SHIFT      0
 207 #define RCC_PLLNCSGR_MOD_PER_MASK       GENMASK(12, 0)
 208 #define RCC_PLLNCSGR_SSCG_MODE_SHIFT    15
 209 #define RCC_PLLNCSGR_SSCG_MODE_MASK     BIT(15)
 210
 211 /* used for RCC_OCENSETR and RCC_OCENCLRR registers */
 212 #define RCC_OCENR_HSION                 BIT(0)
 213 #define RCC_OCENR_CSION                 BIT(4)
 214 #define RCC_OCENR_DIGBYP                BIT(7)
 215 #define RCC_OCENR_HSEON                 BIT(8)
 216 #define RCC_OCENR_HSEBYP                BIT(10)
 217 #define RCC_OCENR_HSECSSON              BIT(11)
 218
 219 /* Fields of RCC_OCRDYR register */
 220 #define RCC_OCRDYR_HSIRDY               BIT(0)
 221 #define RCC_OCRDYR_HSIDIVRDY            BIT(2)
 222 #define RCC_OCRDYR_CSIRDY               BIT(4)
 223 #define RCC_OCRDYR_HSERDY               BIT(8)
 224
 225 /* Fields of DDRITFCR register */
 226 #define RCC_DDRITFCR_DDRCKMOD_MASK      GENMASK(22, 20)
 227 #define RCC_DDRITFCR_DDRCKMOD_SHIFT     20
 228 #define RCC_DDRITFCR_DDRCKMOD_SSR       0
 229
 230 /* Fields of RCC_HSICFGR register */
 231 #define RCC_HSICFGR_HSIDIV_MASK         GENMASK(1, 0)
 232
 233 /* used for MCO related operations */
 234 #define RCC_MCOCFG_MCOON                BIT(12)
 235 #define RCC_MCOCFG_MCODIV_MASK          GENMASK(7, 4)
 236 #define RCC_MCOCFG_MCODIV_SHIFT         4
 237 #define RCC_MCOCFG_MCOSRC_MASK          GENMASK(2, 0)
 238
 239 enum stm32mp1_parent_id {
 240 /*
 241  * _HSI, _HSE, _CSI, _LSI, _LSE should not be moved
 242  * they are used as index in osc[] as entry point
 243  */
 244         _HSI,
 245         _HSE,
 246         _CSI,
 247         _LSI,
 248         _LSE,
 249         _I2S_CKIN,
 250         NB_OSC,
 251
 252 /* other parent source */
 253         _HSI_KER = NB_OSC,
 254         _HSE_KER,
 255         _HSE_KER_DIV2,
 256         _CSI_KER,
 257         _PLL1_P,
 258         _PLL1_Q,
 259         _PLL1_R,
 260         _PLL2_P,
 261         _PLL2_Q,
 262         _PLL2_R,
 263         _PLL3_P,
 264         _PLL3_Q,
 265         _PLL3_R,
 266         _PLL4_P,
 267         _PLL4_Q,
 268         _PLL4_R,
 269         _ACLK,
 270         _PCLK1,
 271         _PCLK2,
 272         _PCLK3,
 273         _PCLK4,
 274         _PCLK5,
 275         _HCLK6,
 276         _HCLK2,
 277         _CK_PER,
 278         _CK_MPU,
 279         _CK_MCU,
 280         _DSI_PHY,
 281         _USB_PHY_48,
 282         _PARENT_NB,
 283         _UNKNOWN_ID = 0xff,
 284 };
 285
 286 enum stm32mp1_parent_sel {
 287         _I2C12_SEL,
 288         _I2C35_SEL,
 289         _I2C46_SEL,
 290         _UART6_SEL,
 291         _UART24_SEL,
 292         _UART35_SEL,
 293         _UART78_SEL,
 294         _SDMMC12_SEL,
 295         _SDMMC3_SEL,
 296         _ETH_SEL,
 297         _QSPI_SEL,
 298         _FMC_SEL,
 299         _USBPHY_SEL,
 300         _USBO_SEL,
 301         _STGEN_SEL,
 302         _DSI_SEL,
 303         _ADC12_SEL,
 304         _SPI1_SEL,
 305         _RTC_SEL,
 306         _PARENT_SEL_NB,
 307         _UNKNOWN_SEL = 0xff,
 308 };
 309
 310 enum stm32mp1_pll_id {
 311         _PLL1,
 312         _PLL2,
 313         _PLL3,
 314         _PLL4,
 315         _PLL_NB
 316 };
 317
 318 enum stm32mp1_div_id {
 319         _DIV_P,
 320         _DIV_Q,
 321         _DIV_R,
 322         _DIV_NB,
 323 };
 324
 325 enum stm32mp1_clksrc_id {
 326         CLKSRC_MPU,
 327         CLKSRC_AXI,
 328         CLKSRC_MCU,
 329         CLKSRC_PLL12,
 330         CLKSRC_PLL3,
 331         CLKSRC_PLL4,
 332         CLKSRC_RTC,
 333         CLKSRC_MCO1,
 334         CLKSRC_MCO2,
 335         CLKSRC_NB
 336 };
 337
 338 enum stm32mp1_clkdiv_id {
 339         CLKDIV_MPU,
 340         CLKDIV_AXI,
 341         CLKDIV_MCU,
 342         CLKDIV_APB1,
 343         CLKDIV_APB2,
 344         CLKDIV_APB3,
 345         CLKDIV_APB4,
 346         CLKDIV_APB5,
 347         CLKDIV_RTC,
 348         CLKDIV_MCO1,
 349         CLKDIV_MCO2,
 350         CLKDIV_NB
 351 };
 352
 353 enum stm32mp1_pllcfg {
 354         PLLCFG_M,
 355         PLLCFG_N,
 356         PLLCFG_P,
 357         PLLCFG_Q,
 358         PLLCFG_R,
 359         PLLCFG_O,
 360         PLLCFG_NB
 361 };
 362
 363 enum stm32mp1_pllcsg {
 364         PLLCSG_MOD_PER,
 365         PLLCSG_INC_STEP,
 366         PLLCSG_SSCG_MODE,
 367         PLLCSG_NB
 368 };
 369
 370 enum stm32mp1_plltype {
 371         PLL_800,
 372         PLL_1600,
 373         PLL_TYPE_NB
 374 };
 375
 376 struct stm32mp1_pll {
 377         u8 refclk_min;
 378         u8 refclk_max;
 379         u8 divn_max;
 380 };
 381
 382 struct stm32mp1_clk_gate {
 383         u16 offset;
 384         u8 bit;
 385         u8 index;
 386         u8 set_clr;
 387         u8 sel;
 388         u8 fixed;
 389 };
 390
 391 struct stm32mp1_clk_sel {
 392         u16 offset;
 393         u8 src;
 394         u8 msk;
 395         u8 nb_parent;
 396         const u8 *parent;
 397 };
 398
 399 #define REFCLK_SIZE 4
 400 struct stm32mp1_clk_pll {
 401         enum stm32mp1_plltype plltype;
 402         u16 rckxselr;
 403         u16 pllxcfgr1;
 404         u16 pllxcfgr2;
 405         u16 pllxfracr;
 406         u16 pllxcr;
 407         u16 pllxcsgr;
 408         u8 refclk[REFCLK_SIZE];
 409 };
 410
 411 struct stm32mp1_clk_data {
 412         const struct stm32mp1_clk_gate *gate;
 413         const struct stm32mp1_clk_sel *sel;
 414         const struct stm32mp1_clk_pll *pll;
 415         const int nb_gate;
 416 };
 417
 418 struct stm32mp1_clk_priv {
 419         fdt_addr_t base;
 420         const struct stm32mp1_clk_data *data;
 421         ulong osc[NB_OSC];
 422         struct udevice *osc_dev[NB_OSC];
 423 };
 424
 425 #define STM32MP1_CLK(off, b, idx, s)            \
 426         {                                       \
 427                 .offset = (off),                \
 428                 .bit = (b),                     \
 429                 .index = (idx),                 \
 430                 .set_clr = 0,                   \
 431                 .sel = (s),                     \
 432                 .fixed = _UNKNOWN_ID,           \
 433         }
 434
 435 #define STM32MP1_CLK_F(off, b, idx, f)          \
 436         {                                       \
 437                 .offset = (off),                \
 438                 .bit = (b),                     \
 439                 .index = (idx),                 \
 440                 .set_clr = 0,                   \
 441                 .sel = _UNKNOWN_SEL,            \
 442                 .fixed = (f),                   \
 443         }
 444
 445 #define STM32MP1_CLK_SET_CLR(off, b, idx, s)    \
 446         {                                       \
 447                 .offset = (off),                \
 448                 .bit = (b),                     \
 449                 .index = (idx),                 \
 450                 .set_clr = 1,                   \
 451                 .sel = (s),                     \
 452                 .fixed = _UNKNOWN_ID,           \
 453         }
 454
 455 #define STM32MP1_CLK_SET_CLR_F(off, b, idx, f)  \
 456         {                                       \
 457                 .offset = (off),                \
 458                 .bit = (b),                     \
 459                 .index = (idx),                 \
 460                 .set_clr = 1,                   \
 461                 .sel = _UNKNOWN_SEL,            \
 462                 .fixed = (f),                   \
 463         }
 464
 465 #define STM32MP1_CLK_PARENT(idx, off, s, m, p)   \
 466         [(idx)] = {                             \
 467                 .offset = (off),                \
 468                 .src = (s),                     \
 469                 .msk = (m),                     \
 470                 .parent = (p),                  \
 471                 .nb_parent = ARRAY_SIZE((p))    \
 472         }
 473
 474 #define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, off4, off5, off6,\
 475                         p1, p2, p3, p4) \
 476         [(idx)] = {                             \
 477                 .plltype = (type),                      \
 478                 .rckxselr = (off1),             \
 479                 .pllxcfgr1 = (off2),            \
 480                 .pllxcfgr2 = (off3),            \
 481                 .pllxfracr = (off4),            \
 482                 .pllxcr = (off5),               \
 483                 .pllxcsgr = (off6),             \
 484                 .refclk[0] = (p1),              \
 485                 .refclk[1] = (p2),              \
 486                 .refclk[2] = (p3),              \
 487                 .refclk[3] = (p4),              \
 488         }
 489
 490 static const u8 stm32mp1_clks[][2] = {
 491         {CK_PER, _CK_PER},
 492         {CK_MPU, _CK_MPU},
 493         {CK_AXI, _ACLK},
 494         {CK_MCU, _CK_MCU},
 495         {CK_HSE, _HSE},
 496         {CK_CSI, _CSI},
 497         {CK_LSI, _LSI},
 498         {CK_LSE, _LSE},
 499         {CK_HSI, _HSI},
 500         {CK_HSE_DIV2, _HSE_KER_DIV2},
 501 };
 502
 503 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
 504         STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL),
 505         STM32MP1_CLK(RCC_DDRITFCR, 1, DDRC1LP, _UNKNOWN_SEL),
 506         STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL),
 507         STM32MP1_CLK(RCC_DDRITFCR, 3, DDRC2LP, _UNKNOWN_SEL),
 508         STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
 509         STM32MP1_CLK(RCC_DDRITFCR, 5, DDRPHYCLP, _UNKNOWN_SEL),
 510         STM32MP1_CLK(RCC_DDRITFCR, 6, DDRCAPB, _UNKNOWN_SEL),
 511         STM32MP1_CLK(RCC_DDRITFCR, 7, DDRCAPBLP, _UNKNOWN_SEL),
 512         STM32MP1_CLK(RCC_DDRITFCR, 8, AXIDCG, _UNKNOWN_SEL),
 513         STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL),
 514         STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL),
 515
 516         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
 517         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
 518         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
 519         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL),
 520         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL),
 521         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL),
 522         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL),
 523         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL),
 524         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL),
 525         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
 526
 527         STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 8, SPI1_K, _SPI1_SEL),
 528         STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
 529
 530         STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3),
 531
 532         STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 0, LTDC_PX, _PLL4_Q),
 533         STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 4, DSI_PX, _PLL4_Q),
 534         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 4, DSI_K, _DSI_SEL),
 535         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
 536         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
 537         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
 538
 539         STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
 540         STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5),
 541         STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
 542
 543         STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB2ENSETR, 5, ADC12, _HCLK2),
 544         STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 5, ADC12_K, _ADC12_SEL),
 545         STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
 546         STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
 547
 548         STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 11, HSEM, _UNKNOWN_SEL),
 549         STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 12, IPCC, _UNKNOWN_SEL),
 550
 551         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
 552         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
 553         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
 554         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL),
 555         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL),
 556         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL),
 557         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL),
 558         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL),
 559         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL),
 560         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL),
 561         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
 562
 563         STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
 564
 565         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK_K, _ETH_SEL),
 566         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL),
 567         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL),
 568         STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK),
 569         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
 570         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
 571         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL),
 572         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL),
 573         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL),
 574
 575         STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
 576
 577         STM32MP1_CLK(RCC_BDCR, 20, RTC, _RTC_SEL),
 578 };
 579
 580 static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
 581 static const u8 i2c35_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
 582 static const u8 i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER};
 583 static const u8 uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
 584                                         _HSE_KER};
 585 static const u8 uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 586                                          _HSE_KER};
 587 static const u8 uart35_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 588                                          _HSE_KER};
 589 static const u8 uart78_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 590                                          _HSE_KER};
 591 static const u8 sdmmc12_parents[] = {_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER};
 592 static const u8 sdmmc3_parents[] = {_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER};
 593 static const u8 eth_parents[] = {_PLL4_P, _PLL3_Q};
 594 static const u8 qspi_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
 595 static const u8 fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
 596 static const u8 usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2};
 597 static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48};
 598 static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER};
 599 static const u8 dsi_parents[] = {_DSI_PHY, _PLL4_P};
 600 static const u8 adc_parents[] = {_PLL4_R, _CK_PER, _PLL3_Q};
 601 static const u8 spi_parents[] = {_PLL4_P, _PLL3_Q, _I2S_CKIN, _CK_PER,
 602                                  _PLL3_R};
 603 static const u8 rtc_parents[] = {_UNKNOWN_ID, _LSE, _LSI, _HSE};
 604
 605 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
 606         STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents),
 607         STM32MP1_CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents),
 608         STM32MP1_CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents),
 609         STM32MP1_CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents),
 610         STM32MP1_CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7,
 611                             uart24_parents),
 612         STM32MP1_CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7,
 613                             uart35_parents),
 614         STM32MP1_CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7,
 615                             uart78_parents),
 616         STM32MP1_CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7,
 617                             sdmmc12_parents),
 618         STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7,
 619                             sdmmc3_parents),
 620         STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents),
 621         STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents),
 622         STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents),
 623         STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents),
 624         STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
 625         STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
 626         STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents),
 627         STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x1, adc_parents),
 628         STM32MP1_CLK_PARENT(_SPI1_SEL, RCC_SPI2S1CKSELR, 0, 0x7, spi_parents),
 629         STM32MP1_CLK_PARENT(_RTC_SEL, RCC_BDCR, RCC_BDCR_RTCSRC_SHIFT,
 630                             (RCC_BDCR_RTCSRC_MASK >> RCC_BDCR_RTCSRC_SHIFT),
 631                             rtc_parents),
 632 };
 633
 634 #ifdef STM32MP1_CLOCK_TREE_INIT
 635 /* define characteristic of PLL according type */
 636 #define DIVN_MIN        24
 637 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
 638         [PLL_800] = {
 639                 .refclk_min = 4,
 640                 .refclk_max = 16,
 641                 .divn_max = 99,
 642                 },
 643         [PLL_1600] = {
 644                 .refclk_min = 8,
 645                 .refclk_max = 16,
 646                 .divn_max = 199,
 647                 },
 648 };
 649 #endif /* STM32MP1_CLOCK_TREE_INIT */
 650
 651 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = {
 652         STM32MP1_CLK_PLL(_PLL1, PLL_1600,
 653                          RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2,
 654                          RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR,
 655                          _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
 656         STM32MP1_CLK_PLL(_PLL2, PLL_1600,
 657                          RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2,
 658                          RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR,
 659                          _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
 660         STM32MP1_CLK_PLL(_PLL3, PLL_800,
 661                          RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2,
 662                          RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR,
 663                          _HSI, _HSE, _CSI, _UNKNOWN_ID),
 664         STM32MP1_CLK_PLL(_PLL4, PLL_800,
 665                          RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2,
 666                          RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR,
 667                          _HSI, _HSE, _CSI, _I2S_CKIN),
 668 };
 669
 670 /* Prescaler table lookups for clock computation */
 671 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */
 672 static const u8 stm32mp1_mcu_div[16] = {
 673         0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9
 674 };
 675
 676 /* div = /1 /2 /4 /8 /16 : same divider for pmu and apbx*/
 677 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div
 678 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div
 679 static const u8 stm32mp1_mpu_apbx_div[8] = {
 680         0, 1, 2, 3, 4, 4, 4, 4
 681 };
 682
 683 /* div = /1 /2 /3 /4 */
 684 static const u8 stm32mp1_axi_div[8] = {
 685         1, 2, 3, 4, 4, 4, 4, 4
 686 };
 687
 688 static const __maybe_unused
 689 char * const stm32mp1_clk_parent_name[_PARENT_NB] = {
 690         [_HSI] = "HSI",
 691         [_HSE] = "HSE",
 692         [_CSI] = "CSI",
 693         [_LSI] = "LSI",
 694         [_LSE] = "LSE",
 695         [_I2S_CKIN] = "I2S_CKIN",
 696         [_HSI_KER] = "HSI_KER",
 697         [_HSE_KER] = "HSE_KER",
 698         [_HSE_KER_DIV2] = "HSE_KER_DIV2",
 699         [_CSI_KER] = "CSI_KER",
 700         [_PLL1_P] = "PLL1_P",
 701         [_PLL1_Q] = "PLL1_Q",
 702         [_PLL1_R] = "PLL1_R",
 703         [_PLL2_P] = "PLL2_P",
 704         [_PLL2_Q] = "PLL2_Q",
 705         [_PLL2_R] = "PLL2_R",
 706         [_PLL3_P] = "PLL3_P",
 707         [_PLL3_Q] = "PLL3_Q",
 708         [_PLL3_R] = "PLL3_R",
 709         [_PLL4_P] = "PLL4_P",
 710         [_PLL4_Q] = "PLL4_Q",
 711         [_PLL4_R] = "PLL4_R",
 712         [_ACLK] = "ACLK",
 713         [_PCLK1] = "PCLK1",
 714         [_PCLK2] = "PCLK2",
 715         [_PCLK3] = "PCLK3",
 716         [_PCLK4] = "PCLK4",
 717         [_PCLK5] = "PCLK5",
 718         [_HCLK6] = "KCLK6",
 719         [_HCLK2] = "HCLK2",
 720         [_CK_PER] = "CK_PER",
 721         [_CK_MPU] = "CK_MPU",
 722         [_CK_MCU] = "CK_MCU",
 723         [_USB_PHY_48] = "USB_PHY_48",
 724         [_DSI_PHY] = "DSI_PHY_PLL",
 725 };
 726
 727 static const __maybe_unused
 728 char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
 729         [_I2C12_SEL] = "I2C12",
 730         [_I2C35_SEL] = "I2C35",
 731         [_I2C46_SEL] = "I2C46",
 732         [_UART6_SEL] = "UART6",
 733         [_UART24_SEL] = "UART24",
 734         [_UART35_SEL] = "UART35",
 735         [_UART78_SEL] = "UART78",
 736         [_SDMMC12_SEL] = "SDMMC12",
 737         [_SDMMC3_SEL] = "SDMMC3",
 738         [_ETH_SEL] = "ETH",
 739         [_QSPI_SEL] = "QSPI",
 740         [_FMC_SEL] = "FMC",
 741         [_USBPHY_SEL] = "USBPHY",
 742         [_USBO_SEL] = "USBO",
 743         [_STGEN_SEL] = "STGEN",
 744         [_DSI_SEL] = "DSI",
 745         [_ADC12_SEL] = "ADC12",
 746         [_SPI1_SEL] = "SPI1",
 747         [_RTC_SEL] = "RTC",
 748 };
 749
 750 static const struct stm32mp1_clk_data stm32mp1_data = {
 751         .gate = stm32mp1_clk_gate,
 752         .sel = stm32mp1_clk_sel,
 753         .pll = stm32mp1_clk_pll,
 754         .nb_gate = ARRAY_SIZE(stm32mp1_clk_gate),
 755 };
 756
 757 static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx)
 758 {
 759         if (idx >= NB_OSC) {
 760                 debug("%s: clk id %d not found\n", __func__, idx);
 761                 return 0;
 762         }
 763
 764         return priv->osc[idx];
 765 }
 766
 767 static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id)
 768 {
 769         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 770         int i, nb_clks = priv->data->nb_gate;
 771
 772         for (i = 0; i < nb_clks; i++) {
 773                 if (gate[i].index == id)
 774                         break;
 775         }
 776
 777         if (i == nb_clks) {
 778                 printf("%s: clk id %d not found\n", __func__, (u32)id);
 779                 return -EINVAL;
 780         }
 781
 782         return i;
 783 }
 784
 785 static int stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv,
 786                                 int i)
 787 {
 788         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 789
 790         if (gate[i].sel > _PARENT_SEL_NB) {
 791                 printf("%s: parents for clk id %d not found\n",
 792                        __func__, i);
 793                 return -EINVAL;
 794         }
 795
 796         return gate[i].sel;
 797 }
 798
 799 static int stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv *priv,
 800                                          int i)
 801 {
 802         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 803
 804         if (gate[i].fixed == _UNKNOWN_ID)
 805                 return -ENOENT;
 806
 807         return gate[i].fixed;
 808 }
 809
 810 static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv,
 811                                    unsigned long id)
 812 {
 813         const struct stm32mp1_clk_sel *sel = priv->data->sel;
 814         int i;
 815         int s, p;
 816         unsigned int idx;
 817
 818         for (idx = 0; idx < ARRAY_SIZE(stm32mp1_clks); idx++)
 819                 if (stm32mp1_clks[idx][0] == id)
 820                         return stm32mp1_clks[idx][1];
 821
 822         i = stm32mp1_clk_get_id(priv, id);
 823         if (i < 0)
 824                 return i;
 825
 826         p = stm32mp1_clk_get_fixed_parent(priv, i);
 827         if (p >= 0 && p < _PARENT_NB)
 828                 return p;
 829
 830         s = stm32mp1_clk_get_sel(priv, i);
 831         if (s < 0)
 832                 return s;
 833
 834         p = (readl(priv->base + sel[s].offset) >> sel[s].src) & sel[s].msk;
 835
 836         if (p < sel[s].nb_parent) {
 837 #ifdef DEBUG
 838                 debug("%s: %s clock is the parent %s of clk id %d\n", __func__,
 839                       stm32mp1_clk_parent_name[sel[s].parent[p]],
 840                       stm32mp1_clk_parent_sel_name[s],
 841                       (u32)id);
 842 #endif
 843                 return sel[s].parent[p];
 844         }
 845
 846         pr_err("%s: no parents defined for clk id %d\n",
 847                __func__, (u32)id);
 848
 849         return -EINVAL;
 850 }
 851
 852 static ulong  pll_get_fref_ck(struct stm32mp1_clk_priv *priv,
 853                               int pll_id)
 854 {
 855         const struct stm32mp1_clk_pll *pll = priv->data->pll;
 856         u32 selr;
 857         int src;
 858         ulong refclk;
 859
 860         /* Get current refclk */
 861         selr = readl(priv->base + pll[pll_id].rckxselr);
 862         src = selr & RCC_SELR_SRC_MASK;
 863
 864         refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]);
 865
 866         return refclk;
 867 }
 868
 869 /*
 870  * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL
 871  * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1)
 872  * - PLL3 & PLL4 => return VCO     with Fpll_y_ck = FVCO / (DIVy + 1)
 873  * => in all the case Fpll_y_ck = pll_get_fvco() / (DIVy + 1)
 874  */
 875 static ulong pll_get_fvco(struct stm32mp1_clk_priv *priv,
 876                           int pll_id)
 877 {
 878         const struct stm32mp1_clk_pll *pll = priv->data->pll;
 879         int divm, divn;
 880         ulong refclk, fvco;
 881         u32 cfgr1, fracr;
 882
 883         cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1);
 884         fracr = readl(priv->base + pll[pll_id].pllxfracr);
 885
 886         divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
 887         divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
 888
 889         refclk = pll_get_fref_ck(priv, pll_id);
 890
 891         /* with FRACV :
 892          *   Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1)
 893          * without FRACV
 894          *   Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1)
 895          */
 896         if (fracr & RCC_PLLNFRACR_FRACLE) {
 897                 u32 fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK)
 898                             >> RCC_PLLNFRACR_FRACV_SHIFT;
 899                 fvco = (ulong)lldiv((unsigned long long)refclk *
 900                                      (((divn + 1) << 13) + fracv),
 901                                      ((unsigned long long)(divm + 1)) << 13);
 902         } else {
 903                 fvco = (ulong)(refclk * (divn + 1) / (divm + 1));
 904         }
 905
 906         return fvco;
 907 }
 908
 909 static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
 910                                     int pll_id, int div_id)
 911 {
 912         const struct stm32mp1_clk_pll *pll = priv->data->pll;
 913         int divy;
 914         ulong dfout;
 915         u32 cfgr2;
 916
 917         if (div_id >= _DIV_NB)
 918                 return 0;
 919
 920         cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2);
 921         divy = (cfgr2 >> RCC_PLLNCFGR2_SHIFT(div_id)) & RCC_PLLNCFGR2_DIVX_MASK;
 922
 923         dfout = pll_get_fvco(priv, pll_id) / (divy + 1);
 924
 925         return dfout;
 926 }
 927
 928 static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
 929 {
 930         u32 reg;
 931         ulong clock = 0;
 932
 933         switch (p) {
 934         case _CK_MPU:
 935         /* MPU sub system */
 936                 reg = readl(priv->base + RCC_MPCKSELR);
 937                 switch (reg & RCC_SELR_SRC_MASK) {
 938                 case RCC_MPCKSELR_HSI:
 939                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
 940                         break;
 941                 case RCC_MPCKSELR_HSE:
 942                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
 943                         break;
 944                 case RCC_MPCKSELR_PLL:
 945                 case RCC_MPCKSELR_PLL_MPUDIV:
 946                         clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P);
 947                         if (p == RCC_MPCKSELR_PLL_MPUDIV) {
 948                                 reg = readl(priv->base + RCC_MPCKDIVR);
 949                                 clock /= stm32mp1_mpu_div[reg &
 950                                                           RCC_MPUDIV_MASK];
 951                         }
 952                         break;
 953                 }
 954                 break;
 955         /* AXI sub system */
 956         case _ACLK:
 957         case _HCLK2:
 958         case _HCLK6:
 959         case _PCLK4:
 960         case _PCLK5:
 961                 reg = readl(priv->base + RCC_ASSCKSELR);
 962                 switch (reg & RCC_SELR_SRC_MASK) {
 963                 case RCC_ASSCKSELR_HSI:
 964                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
 965                         break;
 966                 case RCC_ASSCKSELR_HSE:
 967                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
 968                         break;
 969                 case RCC_ASSCKSELR_PLL:
 970                         clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P);
 971                         break;
 972                 }
 973
 974                 /* System clock divider */
 975                 reg = readl(priv->base + RCC_AXIDIVR);
 976                 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK];
 977
 978                 switch (p) {
 979                 case _PCLK4:
 980                         reg = readl(priv->base + RCC_APB4DIVR);
 981                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
 982                         break;
 983                 case _PCLK5:
 984                         reg = readl(priv->base + RCC_APB5DIVR);
 985                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
 986                         break;
 987                 default:
 988                         break;
 989                 }
 990                 break;
 991         /* MCU sub system */
 992         case _CK_MCU:
 993         case _PCLK1:
 994         case _PCLK2:
 995         case _PCLK3:
 996                 reg = readl(priv->base + RCC_MSSCKSELR);
 997                 switch (reg & RCC_SELR_SRC_MASK) {
 998                 case RCC_MSSCKSELR_HSI:
 999                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
1000                         break;
1001                 case RCC_MSSCKSELR_HSE:
1002                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
1003                         break;
1004                 case RCC_MSSCKSELR_CSI:
1005                         clock = stm32mp1_clk_get_fixed(priv, _CSI);
1006                         break;
1007                 case RCC_MSSCKSELR_PLL:
1008                         clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_P);
1009                         break;
1010                 }
1011
1012                 /* MCU clock divider */
1013                 reg = readl(priv->base + RCC_MCUDIVR);
1014                 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK];
1015
1016                 switch (p) {
1017                 case _PCLK1:
1018                         reg = readl(priv->base + RCC_APB1DIVR);
1019                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1020                         break;
1021                 case _PCLK2:
1022                         reg = readl(priv->base + RCC_APB2DIVR);
1023                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1024                         break;
1025                 case _PCLK3:
1026                         reg = readl(priv->base + RCC_APB3DIVR);
1027                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1028                         break;
1029                 case _CK_MCU:
1030                 default:
1031                         break;
1032                 }
1033                 break;
1034         case _CK_PER:
1035                 reg = readl(priv->base + RCC_CPERCKSELR);
1036                 switch (reg & RCC_SELR_SRC_MASK) {
1037                 case RCC_CPERCKSELR_HSI:
1038                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
1039                         break;
1040                 case RCC_CPERCKSELR_HSE:
1041                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
1042                         break;
1043                 case RCC_CPERCKSELR_CSI:
1044                         clock = stm32mp1_clk_get_fixed(priv, _CSI);
1045                         break;
1046                 }
1047                 break;
1048         case _HSI:
1049         case _HSI_KER:
1050                 clock = stm32mp1_clk_get_fixed(priv, _HSI);
1051                 break;
1052         case _CSI:
1053         case _CSI_KER:
1054                 clock = stm32mp1_clk_get_fixed(priv, _CSI);
1055                 break;
1056         case _HSE:
1057         case _HSE_KER:
1058         case _HSE_KER_DIV2:
1059                 clock = stm32mp1_clk_get_fixed(priv, _HSE);
1060                 if (p == _HSE_KER_DIV2)
1061                         clock >>= 1;
1062                 break;
1063         case _LSI:
1064                 clock = stm32mp1_clk_get_fixed(priv, _LSI);
1065                 break;
1066         case _LSE:
1067                 clock = stm32mp1_clk_get_fixed(priv, _LSE);
1068                 break;
1069         /* PLL */
1070         case _PLL1_P:
1071         case _PLL1_Q:
1072         case _PLL1_R:
1073                 clock = stm32mp1_read_pll_freq(priv, _PLL1, p - _PLL1_P);
1074                 break;
1075         case _PLL2_P:
1076         case _PLL2_Q:
1077         case _PLL2_R:
1078                 clock = stm32mp1_read_pll_freq(priv, _PLL2, p - _PLL2_P);
1079                 break;
1080         case _PLL3_P:
1081         case _PLL3_Q:
1082         case _PLL3_R:
1083                 clock = stm32mp1_read_pll_freq(priv, _PLL3, p - _PLL3_P);
1084                 break;
1085         case _PLL4_P:
1086         case _PLL4_Q:
1087         case _PLL4_R:
1088                 clock = stm32mp1_read_pll_freq(priv, _PLL4, p - _PLL4_P);
1089                 break;
1090         /* other */
1091         case _USB_PHY_48:
1092                 clock = 48000000;
1093                 break;
1094         case _DSI_PHY:
1095         {
1096                 struct clk clk;
1097                 struct udevice *dev = NULL;
1098
1099                 if (!uclass_get_device_by_name(UCLASS_CLK, "ck_dsi_phy",
1100                                                &dev)) {
1101                         if (clk_request(dev, &clk)) {
1102                                 pr_err("ck_dsi_phy request");
1103                         } else {
1104                                 clk.id = 0;
1105                                 clock = clk_get_rate(&clk);
1106                         }
1107                 }
1108                 break;
1109         }
1110         default:
1111                 break;
1112         }
1113
1114         debug("%s(%d) clock = %lx : %ld kHz\n",
1115               __func__, p, clock, clock / 1000);
1116
1117         return clock;
1118 }
1119
1120 static int stm32mp1_clk_enable(struct clk *clk)
1121 {
1122         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1123         const struct stm32mp1_clk_gate *gate = priv->data->gate;
1124         int i = stm32mp1_clk_get_id(priv, clk->id);
1125
1126         if (i < 0)
1127                 return i;
1128
1129         if (gate[i].set_clr)
1130                 writel(BIT(gate[i].bit), priv->base + gate[i].offset);
1131         else
1132                 setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1133
1134         debug("%s: id clock %d has been enabled\n", __func__, (u32)clk->id);
1135
1136         return 0;
1137 }
1138
1139 static int stm32mp1_clk_disable(struct clk *clk)
1140 {
1141         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1142         const struct stm32mp1_clk_gate *gate = priv->data->gate;
1143         int i = stm32mp1_clk_get_id(priv, clk->id);
1144
1145         if (i < 0)
1146                 return i;
1147
1148         if (gate[i].set_clr)
1149                 writel(BIT(gate[i].bit),
1150                        priv->base + gate[i].offset
1151                        + RCC_MP_ENCLRR_OFFSET);
1152         else
1153                 clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1154
1155         debug("%s: id clock %d has been disabled\n", __func__, (u32)clk->id);
1156
1157         return 0;
1158 }
1159
1160 static ulong stm32mp1_clk_get_rate(struct clk *clk)
1161 {
1162         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1163         int p = stm32mp1_clk_get_parent(priv, clk->id);
1164         ulong rate;
1165
1166         if (p < 0)
1167                 return 0;
1168
1169         rate = stm32mp1_clk_get(priv, p);
1170
1171 #ifdef DEBUG
1172         debug("%s: computed rate for id clock %d is %d (parent is %s)\n",
1173               __func__, (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]);
1174 #endif
1175         return rate;
1176 }
1177
1178 #ifdef STM32MP1_CLOCK_TREE_INIT
1179 static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset,
1180                                 u32 mask_on)
1181 {
1182         u32 address = rcc + offset;
1183
1184         if (enable)
1185                 setbits_le32(address, mask_on);
1186         else
1187                 clrbits_le32(address, mask_on);
1188 }
1189
1190 static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on)
1191 {
1192         writel(mask_on, rcc + (enable ? RCC_OCENSETR : RCC_OCENCLRR));
1193 }
1194
1195 static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset,
1196                              u32 mask_rdy)
1197 {
1198         u32 mask_test = 0;
1199         u32 address = rcc + offset;
1200         u32 val;
1201         int ret;
1202
1203         if (enable)
1204                 mask_test = mask_rdy;
1205
1206         ret = readl_poll_timeout(address, val,
1207                                  (val & mask_rdy) == mask_test,
1208                                  TIMEOUT_1S);
1209
1210         if (ret)
1211                 pr_err("OSC %x @ %x timeout for enable=%d : 0x%x\n",
1212                        mask_rdy, address, enable, readl(address));
1213
1214         return ret;
1215 }
1216
1217 static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int digbyp,
1218                                 int lsedrv)
1219 {
1220         u32 value;
1221
1222         if (digbyp)
1223                 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_DIGBYP);
1224
1225         if (bypass || digbyp)
1226                 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP);
1227
1228         /*
1229          * warning: not recommended to switch directly from "high drive"
1230          * to "medium low drive", and vice-versa.
1231          */
1232         value = (readl(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK)
1233                 >> RCC_BDCR_LSEDRV_SHIFT;
1234
1235         while (value != lsedrv) {
1236                 if (value > lsedrv)
1237                         value--;
1238                 else
1239                         value++;
1240
1241                 clrsetbits_le32(rcc + RCC_BDCR,
1242                                 RCC_BDCR_LSEDRV_MASK,
1243                                 value << RCC_BDCR_LSEDRV_SHIFT);
1244         }
1245
1246         stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON);
1247 }
1248
1249 static void stm32mp1_lse_wait(fdt_addr_t rcc)
1250 {
1251         stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY);
1252 }
1253
1254 static void stm32mp1_lsi_set(fdt_addr_t rcc, int enable)
1255 {
1256         stm32mp1_ls_osc_set(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSION);
1257         stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY);
1258 }
1259
1260 static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int digbyp, int css)
1261 {
1262         if (digbyp)
1263                 writel(RCC_OCENR_DIGBYP, rcc + RCC_OCENSETR);
1264         if (bypass || digbyp)
1265                 writel(RCC_OCENR_HSEBYP, rcc + RCC_OCENSETR);
1266
1267         stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON);
1268         stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY);
1269
1270         if (css)
1271                 writel(RCC_OCENR_HSECSSON, rcc + RCC_OCENSETR);
1272 }
1273
1274 static void stm32mp1_csi_set(fdt_addr_t rcc, int enable)
1275 {
1276         stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_CSION);
1277         stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY);
1278 }
1279
1280 static void stm32mp1_hsi_set(fdt_addr_t rcc, int enable)
1281 {
1282         stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_HSION);
1283         stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_HSIRDY);
1284 }
1285
1286 static int stm32mp1_set_hsidiv(fdt_addr_t rcc, u8 hsidiv)
1287 {
1288         u32 address = rcc + RCC_OCRDYR;
1289         u32 val;
1290         int ret;
1291
1292         clrsetbits_le32(rcc + RCC_HSICFGR,
1293                         RCC_HSICFGR_HSIDIV_MASK,
1294                         RCC_HSICFGR_HSIDIV_MASK & hsidiv);
1295
1296         ret = readl_poll_timeout(address, val,
1297                                  val & RCC_OCRDYR_HSIDIVRDY,
1298                                  TIMEOUT_200MS);
1299         if (ret)
1300                 pr_err("HSIDIV failed @ 0x%x: 0x%x\n",
1301                        address, readl(address));
1302
1303         return ret;
1304 }
1305
1306 static int stm32mp1_hsidiv(fdt_addr_t rcc, ulong hsifreq)
1307 {
1308         u8 hsidiv;
1309         u32 hsidivfreq = MAX_HSI_HZ;
1310
1311         for (hsidiv = 0; hsidiv < 4; hsidiv++,
1312              hsidivfreq = hsidivfreq / 2)
1313                 if (hsidivfreq == hsifreq)
1314                         break;
1315
1316         if (hsidiv == 4) {
1317                 pr_err("clk-hsi frequency invalid");
1318                 return -1;
1319         }
1320
1321         if (hsidiv > 0)
1322                 return stm32mp1_set_hsidiv(rcc, hsidiv);
1323
1324         return 0;
1325 }
1326
1327 static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id)
1328 {
1329         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1330
1331         clrsetbits_le32(priv->base + pll[pll_id].pllxcr,
1332                         RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN |
1333                         RCC_PLLNCR_DIVREN,
1334                         RCC_PLLNCR_PLLON);
1335 }
1336
1337 static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output)
1338 {
1339         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1340         u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1341         u32 val;
1342         int ret;
1343
1344         ret = readl_poll_timeout(pllxcr, val, val & RCC_PLLNCR_PLLRDY,
1345                                  TIMEOUT_200MS);
1346
1347         if (ret) {
1348                 pr_err("PLL%d start failed @ 0x%x: 0x%x\n",
1349                        pll_id, pllxcr, readl(pllxcr));
1350                 return ret;
1351         }
1352
1353         /* start the requested output */
1354         setbits_le32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT);
1355
1356         return 0;
1357 }
1358
1359 static int pll_stop(struct stm32mp1_clk_priv *priv, int pll_id)
1360 {
1361         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1362         u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1363         u32 val;
1364
1365         /* stop all output */
1366         clrbits_le32(pllxcr,
1367                      RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN);
1368
1369         /* stop PLL */
1370         clrbits_le32(pllxcr, RCC_PLLNCR_PLLON);
1371
1372         /* wait PLL stopped */
1373         return readl_poll_timeout(pllxcr, val, (val & RCC_PLLNCR_PLLRDY) == 0,
1374                                   TIMEOUT_200MS);
1375 }
1376
1377 static void pll_config_output(struct stm32mp1_clk_priv *priv,
1378                               int pll_id, u32 *pllcfg)
1379 {
1380         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1381         fdt_addr_t rcc = priv->base;
1382         u32 value;
1383
1384         value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT)
1385                 & RCC_PLLNCFGR2_DIVP_MASK;
1386         value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT)
1387                  & RCC_PLLNCFGR2_DIVQ_MASK;
1388         value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT)
1389                  & RCC_PLLNCFGR2_DIVR_MASK;
1390         writel(value, rcc + pll[pll_id].pllxcfgr2);
1391 }
1392
1393 static int pll_config(struct stm32mp1_clk_priv *priv, int pll_id,
1394                       u32 *pllcfg, u32 fracv)
1395 {
1396         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1397         fdt_addr_t rcc = priv->base;
1398         enum stm32mp1_plltype type = pll[pll_id].plltype;
1399         int src;
1400         ulong refclk;
1401         u8 ifrge = 0;
1402         u32 value;
1403
1404         src = readl(priv->base + pll[pll_id].rckxselr) & RCC_SELR_SRC_MASK;
1405
1406         refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]) /
1407                  (pllcfg[PLLCFG_M] + 1);
1408
1409         if (refclk < (stm32mp1_pll[type].refclk_min * 1000000) ||
1410             refclk > (stm32mp1_pll[type].refclk_max * 1000000)) {
1411                 debug("invalid refclk = %x\n", (u32)refclk);
1412                 return -EINVAL;
1413         }
1414         if (type == PLL_800 && refclk >= 8000000)
1415                 ifrge = 1;
1416
1417         value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT)
1418                  & RCC_PLLNCFGR1_DIVN_MASK;
1419         value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT)
1420                  & RCC_PLLNCFGR1_DIVM_MASK;
1421         value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT)
1422                  & RCC_PLLNCFGR1_IFRGE_MASK;
1423         writel(value, rcc + pll[pll_id].pllxcfgr1);
1424
1425         /* fractional configuration: load sigma-delta modulator (SDM) */
1426
1427         /* Write into FRACV the new fractional value , and FRACLE to 0 */
1428         writel(fracv << RCC_PLLNFRACR_FRACV_SHIFT,
1429                rcc + pll[pll_id].pllxfracr);
1430
1431         /* Write FRACLE to 1 : FRACV value is loaded into the SDM */
1432         setbits_le32(rcc + pll[pll_id].pllxfracr,
1433                      RCC_PLLNFRACR_FRACLE);
1434
1435         pll_config_output(priv, pll_id, pllcfg);
1436
1437         return 0;
1438 }
1439
1440 static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg)
1441 {
1442         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1443         u32 pllxcsg;
1444
1445         pllxcsg = ((csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) &
1446                     RCC_PLLNCSGR_MOD_PER_MASK) |
1447                   ((csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) &
1448                     RCC_PLLNCSGR_INC_STEP_MASK) |
1449                   ((csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) &
1450                     RCC_PLLNCSGR_SSCG_MODE_MASK);
1451
1452         writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr);
1453
1454         setbits_le32(priv->base + pll[pll_id].pllxcr, RCC_PLLNCR_SSCG_CTRL);
1455 }
1456
1457 static  __maybe_unused int pll_set_rate(struct udevice *dev,
1458                                         int pll_id,
1459                                         int div_id,
1460                                         unsigned long clk_rate)
1461 {
1462         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1463         unsigned int pllcfg[PLLCFG_NB];
1464         ofnode plloff;
1465         char name[12];
1466         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1467         enum stm32mp1_plltype type = pll[pll_id].plltype;
1468         int divm, divn, divy;
1469         int ret;
1470         ulong fck_ref;
1471         u32 fracv;
1472         u64 value;
1473
1474         if (div_id > _DIV_NB)
1475                 return -EINVAL;
1476
1477         sprintf(name, "st,pll@%d", pll_id);
1478         plloff = dev_read_subnode(dev, name);
1479         if (!ofnode_valid(plloff))
1480                 return -FDT_ERR_NOTFOUND;
1481
1482         ret = ofnode_read_u32_array(plloff, "cfg",
1483                                     pllcfg, PLLCFG_NB);
1484         if (ret < 0)
1485                 return -FDT_ERR_NOTFOUND;
1486
1487         fck_ref = pll_get_fref_ck(priv, pll_id);
1488
1489         divm = pllcfg[PLLCFG_M];
1490         /* select output divider = 0: for _DIV_P, 1:_DIV_Q 2:_DIV_R */
1491         divy = pllcfg[PLLCFG_P + div_id];
1492
1493         /* For: PLL1 & PLL2 => VCO is * 2 but ck_pll_y is also / 2
1494          * So same final result than PLL2 et 4
1495          * with FRACV
1496          * Fck_pll_y = Fck_ref * ((DIVN + 1) + FRACV / 2^13)
1497          *             / (DIVy + 1) * (DIVM + 1)
1498          * value = (DIVN + 1) * 2^13 + FRACV / 2^13
1499          *       = Fck_pll_y (DIVy + 1) * (DIVM + 1) * 2^13 / Fck_ref
1500          */
1501         value = ((u64)clk_rate * (divy + 1) * (divm + 1)) << 13;
1502         value = lldiv(value, fck_ref);
1503
1504         divn = (value >> 13) - 1;
1505         if (divn < DIVN_MIN ||
1506             divn > stm32mp1_pll[type].divn_max) {
1507                 pr_err("divn invalid = %d", divn);
1508                 return -EINVAL;
1509         }
1510         fracv = value - ((divn + 1) << 13);
1511         pllcfg[PLLCFG_N] = divn;
1512
1513         /* reconfigure PLL */
1514         pll_stop(priv, pll_id);
1515         pll_config(priv, pll_id, pllcfg, fracv);
1516         pll_start(priv, pll_id);
1517         pll_output(priv, pll_id, pllcfg[PLLCFG_O]);
1518
1519         return 0;
1520 }
1521
1522 static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc)
1523 {
1524         u32 address = priv->base + (clksrc >> 4);
1525         u32 val;
1526         int ret;
1527
1528         clrsetbits_le32(address, RCC_SELR_SRC_MASK, clksrc & RCC_SELR_SRC_MASK);
1529         ret = readl_poll_timeout(address, val, val & RCC_SELR_SRCRDY,
1530                                  TIMEOUT_200MS);
1531         if (ret)
1532                 pr_err("CLKSRC %x start failed @ 0x%x: 0x%x\n",
1533                        clksrc, address, readl(address));
1534
1535         return ret;
1536 }
1537
1538 static void stgen_config(struct stm32mp1_clk_priv *priv)
1539 {
1540         int p;
1541         u32 stgenc, cntfid0;
1542         ulong rate;
1543
1544         stgenc = STM32_STGEN_BASE;
1545         cntfid0 = readl(stgenc + STGENC_CNTFID0);
1546         p = stm32mp1_clk_get_parent(priv, STGEN_K);
1547         rate = stm32mp1_clk_get(priv, p);
1548
1549         if (cntfid0 != rate) {
1550                 u64 counter;
1551
1552                 pr_debug("System Generic Counter (STGEN) update\n");
1553                 clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1554                 counter = (u64)readl(stgenc + STGENC_CNTCVL);
1555                 counter |= ((u64)(readl(stgenc + STGENC_CNTCVU))) << 32;
1556                 counter = lldiv(counter * (u64)rate, cntfid0);
1557                 writel((u32)counter, stgenc + STGENC_CNTCVL);
1558                 writel((u32)(counter >> 32), stgenc + STGENC_CNTCVU);
1559                 writel(rate, stgenc + STGENC_CNTFID0);
1560                 setbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1561
1562                 __asm__ volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (rate));
1563
1564                 /* need to update gd->arch.timer_rate_hz with new frequency */
1565                 timer_init();
1566         }
1567 }
1568
1569 static int set_clkdiv(unsigned int clkdiv, u32 address)
1570 {
1571         u32 val;
1572         int ret;
1573
1574         clrsetbits_le32(address, RCC_DIVR_DIV_MASK, clkdiv & RCC_DIVR_DIV_MASK);
1575         ret = readl_poll_timeout(address, val, val & RCC_DIVR_DIVRDY,
1576                                  TIMEOUT_200MS);
1577         if (ret)
1578                 pr_err("CLKDIV %x start failed @ 0x%x: 0x%x\n",
1579                        clkdiv, address, readl(address));
1580
1581         return ret;
1582 }
1583
1584 static void stm32mp1_mco_csg(struct stm32mp1_clk_priv *priv,
1585                              u32 clksrc, u32 clkdiv)
1586 {
1587         u32 address = priv->base + (clksrc >> 4);
1588
1589         /*
1590          * binding clksrc : bit15-4 offset
1591          *                  bit3:   disable
1592          *                  bit2-0: MCOSEL[2:0]
1593          */
1594         if (clksrc & 0x8) {
1595                 clrbits_le32(address, RCC_MCOCFG_MCOON);
1596         } else {
1597                 clrsetbits_le32(address,
1598                                 RCC_MCOCFG_MCOSRC_MASK,
1599                                 clksrc & RCC_MCOCFG_MCOSRC_MASK);
1600                 clrsetbits_le32(address,
1601                                 RCC_MCOCFG_MCODIV_MASK,
1602                                 clkdiv << RCC_MCOCFG_MCODIV_SHIFT);
1603                 setbits_le32(address, RCC_MCOCFG_MCOON);
1604         }
1605 }
1606
1607 static void set_rtcsrc(struct stm32mp1_clk_priv *priv,
1608                        unsigned int clksrc,
1609                        int lse_css)
1610 {
1611         u32 address = priv->base + RCC_BDCR;
1612
1613         if (readl(address) & RCC_BDCR_RTCCKEN)
1614                 goto skip_rtc;
1615
1616         if (clksrc == CLK_RTC_DISABLED)
1617                 goto skip_rtc;
1618
1619         clrsetbits_le32(address,
1620                         RCC_BDCR_RTCSRC_MASK,
1621                         clksrc << RCC_BDCR_RTCSRC_SHIFT);
1622
1623         setbits_le32(address, RCC_BDCR_RTCCKEN);
1624
1625 skip_rtc:
1626         if (lse_css)
1627                 setbits_le32(address, RCC_BDCR_LSECSSON);
1628 }
1629
1630 static void pkcs_config(struct stm32mp1_clk_priv *priv, u32 pkcs)
1631 {
1632         u32 address = priv->base + ((pkcs >> 4) & 0xFFF);
1633         u32 value = pkcs & 0xF;
1634         u32 mask = 0xF;
1635
1636         if (pkcs & BIT(31)) {
1637                 mask <<= 4;
1638                 value <<= 4;
1639         }
1640         clrsetbits_le32(address, mask, value);
1641 }
1642
1643 static int stm32mp1_clktree(struct udevice *dev)
1644 {
1645         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1646         fdt_addr_t rcc = priv->base;
1647         unsigned int clksrc[CLKSRC_NB];
1648         unsigned int clkdiv[CLKDIV_NB];
1649         unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
1650         ofnode plloff[_PLL_NB];
1651         int ret;
1652         int i, len;
1653         int lse_css = 0;
1654         const u32 *pkcs_cell;
1655
1656         /* check mandatory field */
1657         ret = dev_read_u32_array(dev, "st,clksrc", clksrc, CLKSRC_NB);
1658         if (ret < 0) {
1659                 debug("field st,clksrc invalid: error %d\n", ret);
1660                 return -FDT_ERR_NOTFOUND;
1661         }
1662
1663         ret = dev_read_u32_array(dev, "st,clkdiv", clkdiv, CLKDIV_NB);
1664         if (ret < 0) {
1665                 debug("field st,clkdiv invalid: error %d\n", ret);
1666                 return -FDT_ERR_NOTFOUND;
1667         }
1668
1669         /* check mandatory field in each pll */
1670         for (i = 0; i < _PLL_NB; i++) {
1671                 char name[12];
1672
1673                 sprintf(name, "st,pll@%d", i);
1674                 plloff[i] = dev_read_subnode(dev, name);
1675                 if (!ofnode_valid(plloff[i]))
1676                         continue;
1677                 ret = ofnode_read_u32_array(plloff[i], "cfg",
1678                                             pllcfg[i], PLLCFG_NB);
1679                 if (ret < 0) {
1680                         debug("field cfg invalid: error %d\n", ret);
1681                         return -FDT_ERR_NOTFOUND;
1682                 }
1683         }
1684
1685         debug("configuration MCO\n");
1686         stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]);
1687         stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]);
1688
1689         debug("switch ON osillator\n");
1690         /*
1691          * switch ON oscillator found in device-tree,
1692          * HSI already ON after bootrom
1693          */
1694         if (priv->osc[_LSI])
1695                 stm32mp1_lsi_set(rcc, 1);
1696
1697         if (priv->osc[_LSE]) {
1698                 int bypass, digbyp, lsedrv;
1699                 struct udevice *dev = priv->osc_dev[_LSE];
1700
1701                 bypass = dev_read_bool(dev, "st,bypass");
1702                 digbyp = dev_read_bool(dev, "st,digbypass");
1703                 lse_css = dev_read_bool(dev, "st,css");
1704                 lsedrv = dev_read_u32_default(dev, "st,drive",
1705                                               LSEDRV_MEDIUM_HIGH);
1706
1707                 stm32mp1_lse_enable(rcc, bypass, digbyp, lsedrv);
1708         }
1709
1710         if (priv->osc[_HSE]) {
1711                 int bypass, digbyp, css;
1712                 struct udevice *dev = priv->osc_dev[_HSE];
1713
1714                 bypass = dev_read_bool(dev, "st,bypass");
1715                 digbyp = dev_read_bool(dev, "st,digbypass");
1716                 css = dev_read_bool(dev, "st,css");
1717
1718                 stm32mp1_hse_enable(rcc, bypass, digbyp, css);
1719         }
1720         /* CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR)
1721          * => switch on CSI even if node is not present in device tree
1722          */
1723         stm32mp1_csi_set(rcc, 1);
1724
1725         /* come back to HSI */
1726         debug("come back to HSI\n");
1727         set_clksrc(priv, CLK_MPU_HSI);
1728         set_clksrc(priv, CLK_AXI_HSI);
1729         set_clksrc(priv, CLK_MCU_HSI);
1730
1731         debug("pll stop\n");
1732         for (i = 0; i < _PLL_NB; i++)
1733                 pll_stop(priv, i);
1734
1735         /* configure HSIDIV */
1736         debug("configure HSIDIV\n");
1737         if (priv->osc[_HSI]) {
1738                 stm32mp1_hsidiv(rcc, priv->osc[_HSI]);
1739                 stgen_config(priv);
1740         }
1741
1742         /* select DIV */
1743         debug("select DIV\n");
1744         /* no ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */
1745         writel(clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK, rcc + RCC_MPCKDIVR);
1746         set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR);
1747         set_clkdiv(clkdiv[CLKDIV_APB4], rcc + RCC_APB4DIVR);
1748         set_clkdiv(clkdiv[CLKDIV_APB5], rcc + RCC_APB5DIVR);
1749         set_clkdiv(clkdiv[CLKDIV_MCU], rcc + RCC_MCUDIVR);
1750         set_clkdiv(clkdiv[CLKDIV_APB1], rcc + RCC_APB1DIVR);
1751         set_clkdiv(clkdiv[CLKDIV_APB2], rcc + RCC_APB2DIVR);
1752         set_clkdiv(clkdiv[CLKDIV_APB3], rcc + RCC_APB3DIVR);
1753
1754         /* no ready bit for RTC */
1755         writel(clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK, rcc + RCC_RTCDIVR);
1756
1757         /* configure PLLs source */
1758         debug("configure PLLs source\n");
1759         set_clksrc(priv, clksrc[CLKSRC_PLL12]);
1760         set_clksrc(priv, clksrc[CLKSRC_PLL3]);
1761         set_clksrc(priv, clksrc[CLKSRC_PLL4]);
1762
1763         /* configure and start PLLs */
1764         debug("configure PLLs\n");
1765         for (i = 0; i < _PLL_NB; i++) {
1766                 u32 fracv;
1767                 u32 csg[PLLCSG_NB];
1768
1769                 debug("configure PLL %d @ %d\n", i,
1770                       ofnode_to_offset(plloff[i]));
1771                 if (!ofnode_valid(plloff[i]))
1772                         continue;
1773
1774                 fracv = ofnode_read_u32_default(plloff[i], "frac", 0);
1775                 pll_config(priv, i, pllcfg[i], fracv);
1776                 ret = ofnode_read_u32_array(plloff[i], "csg", csg, PLLCSG_NB);
1777                 if (!ret) {
1778                         pll_csg(priv, i, csg);
1779                 } else if (ret != -FDT_ERR_NOTFOUND) {
1780                         debug("invalid csg node for pll@%d res=%d\n", i, ret);
1781                         return ret;
1782                 }
1783                 pll_start(priv, i);
1784         }
1785
1786         /* wait and start PLLs ouptut when ready */
1787         for (i = 0; i < _PLL_NB; i++) {
1788                 if (!ofnode_valid(plloff[i]))
1789                         continue;
1790                 debug("output PLL %d\n", i);
1791                 pll_output(priv, i, pllcfg[i][PLLCFG_O]);
1792         }
1793
1794         /* wait LSE ready before to use it */
1795         if (priv->osc[_LSE])
1796                 stm32mp1_lse_wait(rcc);
1797
1798         /* configure with expected clock source */
1799         debug("CLKSRC\n");
1800         set_clksrc(priv, clksrc[CLKSRC_MPU]);
1801         set_clksrc(priv, clksrc[CLKSRC_AXI]);
1802         set_clksrc(priv, clksrc[CLKSRC_MCU]);
1803         set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css);
1804
1805         /* configure PKCK */
1806         debug("PKCK\n");
1807         pkcs_cell = dev_read_prop(dev, "st,pkcs", &len);
1808         if (pkcs_cell) {
1809                 bool ckper_disabled = false;
1810
1811                 for (i = 0; i < len / sizeof(u32); i++) {
1812                         u32 pkcs = (u32)fdt32_to_cpu(pkcs_cell[i]);
1813
1814                         if (pkcs == CLK_CKPER_DISABLED) {
1815                                 ckper_disabled = true;
1816                                 continue;
1817                         }
1818                         pkcs_config(priv, pkcs);
1819                 }
1820                 /* CKPER is source for some peripheral clock
1821                  * (FMC-NAND / QPSI-NOR) and switching source is allowed
1822                  * only if previous clock is still ON
1823                  * => deactivated CKPER only after switching clock
1824                  */
1825                 if (ckper_disabled)
1826                         pkcs_config(priv, CLK_CKPER_DISABLED);
1827         }
1828
1829         /* STGEN clock source can change with CLK_STGEN_XXX */
1830         stgen_config(priv);
1831
1832         debug("oscillator off\n");
1833         /* switch OFF HSI if not found in device-tree */
1834         if (!priv->osc[_HSI])
1835                 stm32mp1_hsi_set(rcc, 0);
1836
1837         /* Software Self-Refresh mode (SSR) during DDR initilialization */
1838         clrsetbits_le32(priv->base + RCC_DDRITFCR,
1839                         RCC_DDRITFCR_DDRCKMOD_MASK,
1840                         RCC_DDRITFCR_DDRCKMOD_SSR <<
1841                         RCC_DDRITFCR_DDRCKMOD_SHIFT);
1842
1843         return 0;
1844 }
1845 #endif /* STM32MP1_CLOCK_TREE_INIT */
1846
1847 static int pll_set_output_rate(struct udevice *dev,
1848                                int pll_id,
1849                                int div_id,
1850                                unsigned long clk_rate)
1851 {
1852         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1853         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1854         u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1855         int div;
1856         ulong fvco;
1857
1858         if (div_id > _DIV_NB)
1859                 return -EINVAL;
1860
1861         fvco = pll_get_fvco(priv, pll_id);
1862
1863         if (fvco <= clk_rate)
1864                 div = 1;
1865         else
1866                 div = DIV_ROUND_UP(fvco, clk_rate);
1867
1868         if (div > 128)
1869                 div = 128;
1870
1871         /* stop the requested output */
1872         clrbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
1873         /* change divider */
1874         clrsetbits_le32(priv->base + pll[pll_id].pllxcfgr2,
1875                         RCC_PLLNCFGR2_DIVX_MASK << RCC_PLLNCFGR2_SHIFT(div_id),
1876                         (div - 1) << RCC_PLLNCFGR2_SHIFT(div_id));
1877         /* start the requested output */
1878         setbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
1879
1880         return 0;
1881 }
1882
1883 static ulong stm32mp1_clk_set_rate(struct clk *clk, unsigned long clk_rate)
1884 {
1885         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1886         int p;
1887
1888         switch (clk->id) {
1889 #if defined(STM32MP1_CLOCK_TREE_INIT) && \
1890         defined(CONFIG_STM32MP1_DDR_INTERACTIVE)
1891         case DDRPHYC:
1892                 break;
1893 #endif
1894         case LTDC_PX:
1895         case DSI_PX:
1896                 break;
1897         default:
1898                 pr_err("not supported");
1899                 return -EINVAL;
1900         }
1901
1902         p = stm32mp1_clk_get_parent(priv, clk->id);
1903 #ifdef DEBUG
1904         debug("%s: parent = %d:%s\n", __func__, p, stm32mp1_clk_parent_name[p]);
1905 #endif
1906         if (p < 0)
1907                 return -EINVAL;
1908
1909         switch (p) {
1910 #if defined(STM32MP1_CLOCK_TREE_INIT) && \
1911         defined(CONFIG_STM32MP1_DDR_INTERACTIVE)
1912         case _PLL2_R: /* DDRPHYC */
1913         {
1914                 /* only for change DDR clock in interactive mode */
1915                 ulong result;
1916
1917                 set_clksrc(priv, CLK_AXI_HSI);
1918                 result = pll_set_rate(clk->dev,  _PLL2, _DIV_R, clk_rate);
1919                 set_clksrc(priv, CLK_AXI_PLL2P);
1920                 return result;
1921         }
1922 #endif
1923
1924         case _PLL4_Q:
1925                 /* for LTDC_PX and DSI_PX case */
1926                 return pll_set_output_rate(clk->dev, _PLL4, _DIV_Q, clk_rate);
1927         }
1928
1929         return -EINVAL;
1930 }
1931
1932 static void stm32mp1_osc_clk_init(const char *name,
1933                                   struct stm32mp1_clk_priv *priv,
1934                                   int index)
1935 {
1936         struct clk clk;
1937         struct udevice *dev = NULL;
1938
1939         priv->osc[index] = 0;
1940         clk.id = 0;
1941         if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) {
1942                 if (clk_request(dev, &clk))
1943                         pr_err("%s request", name);
1944                 else
1945                         priv->osc[index] = clk_get_rate(&clk);
1946         }
1947         priv->osc_dev[index] = dev;
1948 }
1949
1950 static void stm32mp1_osc_init(struct udevice *dev)
1951 {
1952         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1953         int i;
1954         const char *name[NB_OSC] = {
1955                 [_LSI] = "clk-lsi",
1956                 [_LSE] = "clk-lse",
1957                 [_HSI] = "clk-hsi",
1958                 [_HSE] = "clk-hse",
1959                 [_CSI] = "clk-csi",
1960                 [_I2S_CKIN] = "i2s_ckin",
1961         };
1962
1963         for (i = 0; i < NB_OSC; i++) {
1964                 stm32mp1_osc_clk_init(name[i], priv, i);
1965                 debug("%d: %s => %x\n", i, name[i], (u32)priv->osc[i]);
1966         }
1967 }
1968
1969 static void  __maybe_unused stm32mp1_clk_dump(struct stm32mp1_clk_priv *priv)
1970 {
1971         char buf[32];
1972         int i, s, p;
1973
1974         printf("Clocks:\n");
1975         for (i = 0; i < _PARENT_NB; i++) {
1976                 printf("- %s : %s MHz\n",
1977                        stm32mp1_clk_parent_name[i],
1978                        strmhz(buf, stm32mp1_clk_get(priv, i)));
1979         }
1980         printf("Source Clocks:\n");
1981         for (i = 0; i < _PARENT_SEL_NB; i++) {
1982                 p = (readl(priv->base + priv->data->sel[i].offset) >>
1983                      priv->data->sel[i].src) & priv->data->sel[i].msk;
1984                 if (p < priv->data->sel[i].nb_parent) {
1985                         s = priv->data->sel[i].parent[p];
1986                         printf("- %s(%d) => parent %s(%d)\n",
1987                                stm32mp1_clk_parent_sel_name[i], i,
1988                                stm32mp1_clk_parent_name[s], s);
1989                 } else {
1990                         printf("- %s(%d) => parent index %d is invalid\n",
1991                                stm32mp1_clk_parent_sel_name[i], i, p);
1992                 }
1993         }
1994 }
1995
1996 #ifdef CONFIG_CMD_CLK
1997 int soc_clk_dump(void)
1998 {
1999         struct udevice *dev;
2000         struct stm32mp1_clk_priv *priv;
2001         int ret;
2002
2003         ret = uclass_get_device_by_driver(UCLASS_CLK,
2004                                           DM_GET_DRIVER(stm32mp1_clock),
2005                                           &dev);
2006         if (ret)
2007                 return ret;
2008
2009         priv = dev_get_priv(dev);
2010
2011         stm32mp1_clk_dump(priv);
2012
2013         return 0;
2014 }
2015 #endif
2016
2017 static int stm32mp1_clk_probe(struct udevice *dev)
2018 {
2019         int result = 0;
2020         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
2021
2022         priv->base = dev_read_addr(dev->parent);
2023         if (priv->base == FDT_ADDR_T_NONE)
2024                 return -EINVAL;
2025
2026         priv->data = (void *)&stm32mp1_data;
2027
2028         if (!priv->data->gate || !priv->data->sel ||
2029             !priv->data->pll)
2030                 return -EINVAL;
2031
2032         stm32mp1_osc_init(dev);
2033
2034 #ifdef STM32MP1_CLOCK_TREE_INIT
2035         /* clock tree init is done only one time, before relocation */
2036         if (!(gd->flags & GD_FLG_RELOC))
2037                 result = stm32mp1_clktree(dev);
2038 #endif
2039
2040 #ifndef CONFIG_SPL_BUILD
2041 #if defined(DEBUG)
2042         /* display debug information for probe after relocation */
2043         if (gd->flags & GD_FLG_RELOC)
2044                 stm32mp1_clk_dump(priv);
2045 #endif
2046
2047         gd->cpu_clk = stm32mp1_clk_get(priv, _CK_MPU);
2048         gd->bus_clk = stm32mp1_clk_get(priv, _ACLK);
2049         /* DDRPHYC father */
2050         gd->mem_clk = stm32mp1_clk_get(priv, _PLL2_R);
2051 #if defined(CONFIG_DISPLAY_CPUINFO)
2052         if (gd->flags & GD_FLG_RELOC) {
2053                 char buf[32];
2054
2055                 printf("Clocks:\n");
2056                 printf("- MPU : %s MHz\n", strmhz(buf, gd->cpu_clk));
2057                 printf("- MCU : %s MHz\n",
2058                        strmhz(buf, stm32mp1_clk_get(priv, _CK_MCU)));
2059                 printf("- AXI : %s MHz\n", strmhz(buf, gd->bus_clk));
2060                 printf("- PER : %s MHz\n",
2061                        strmhz(buf, stm32mp1_clk_get(priv, _CK_PER)));
2062                 printf("- DDR : %s MHz\n", strmhz(buf, gd->mem_clk));
2063         }
2064 #endif /* CONFIG_DISPLAY_CPUINFO */
2065 #endif
2066
2067         return result;
2068 }
2069
2070 static const struct clk_ops stm32mp1_clk_ops = {
2071         .enable = stm32mp1_clk_enable,
2072         .disable = stm32mp1_clk_disable,
2073         .get_rate = stm32mp1_clk_get_rate,
2074         .set_rate = stm32mp1_clk_set_rate,
2075 };
2076
2077 U_BOOT_DRIVER(stm32mp1_clock) = {
2078         .name = "stm32mp1_clk",
2079         .id = UCLASS_CLK,
2080         .ops = &stm32mp1_clk_ops,
2081         .priv_auto_alloc_size = sizeof(struct stm32mp1_clk_priv),
2082         .probe = stm32mp1_clk_probe,
2083 };