drivers/clk/clk_stm32mp1.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   4  */
   5
   6 #include <common.h>
   7 #include <clk-uclass.h>
   8 #include <div64.h>
   9 #include <dm.h>
  10 #include <regmap.h>
  11 #include <spl.h>
  12 #include <syscon.h>
  13 #include <linux/io.h>
  14 #include <linux/iopoll.h>
  15 #include <dt-bindings/clock/stm32mp1-clks.h>
  16 #include <dt-bindings/clock/stm32mp1-clksrc.h>
  17
  18 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
  19 /* activate clock tree initialization in the driver */
  20 #define STM32MP1_CLOCK_TREE_INIT
  21 #endif
  22
  23 #define MAX_HSI_HZ              64000000
  24
  25 /* TIMEOUT */
  26 #define TIMEOUT_200MS           200000
  27 #define TIMEOUT_1S              1000000
  28
  29 /* STGEN registers */
  30 #define STGENC_CNTCR            0x00
  31 #define STGENC_CNTSR            0x04
  32 #define STGENC_CNTCVL           0x08
  33 #define STGENC_CNTCVU           0x0C
  34 #define STGENC_CNTFID0          0x20
  35
  36 #define STGENC_CNTCR_EN         BIT(0)
  37
  38 /* RCC registers */
  39 #define RCC_OCENSETR            0x0C
  40 #define RCC_OCENCLRR            0x10
  41 #define RCC_HSICFGR             0x18
  42 #define RCC_MPCKSELR            0x20
  43 #define RCC_ASSCKSELR           0x24
  44 #define RCC_RCK12SELR           0x28
  45 #define RCC_MPCKDIVR            0x2C
  46 #define RCC_AXIDIVR             0x30
  47 #define RCC_APB4DIVR            0x3C
  48 #define RCC_APB5DIVR            0x40
  49 #define RCC_RTCDIVR             0x44
  50 #define RCC_MSSCKSELR           0x48
  51 #define RCC_PLL1CR              0x80
  52 #define RCC_PLL1CFGR1           0x84
  53 #define RCC_PLL1CFGR2           0x88
  54 #define RCC_PLL1FRACR           0x8C
  55 #define RCC_PLL1CSGR            0x90
  56 #define RCC_PLL2CR              0x94
  57 #define RCC_PLL2CFGR1           0x98
  58 #define RCC_PLL2CFGR2           0x9C
  59 #define RCC_PLL2FRACR           0xA0
  60 #define RCC_PLL2CSGR            0xA4
  61 #define RCC_I2C46CKSELR         0xC0
  62 #define RCC_CPERCKSELR          0xD0
  63 #define RCC_STGENCKSELR         0xD4
  64 #define RCC_DDRITFCR            0xD8
  65 #define RCC_BDCR                0x140
  66 #define RCC_RDLSICR             0x144
  67 #define RCC_MP_APB4ENSETR       0x200
  68 #define RCC_MP_APB5ENSETR       0x208
  69 #define RCC_MP_AHB5ENSETR       0x210
  70 #define RCC_MP_AHB6ENSETR       0x218
  71 #define RCC_OCRDYR              0x808
  72 #define RCC_DBGCFGR             0x80C
  73 #define RCC_RCK3SELR            0x820
  74 #define RCC_RCK4SELR            0x824
  75 #define RCC_MCUDIVR             0x830
  76 #define RCC_APB1DIVR            0x834
  77 #define RCC_APB2DIVR            0x838
  78 #define RCC_APB3DIVR            0x83C
  79 #define RCC_PLL3CR              0x880
  80 #define RCC_PLL3CFGR1           0x884
  81 #define RCC_PLL3CFGR2           0x888
  82 #define RCC_PLL3FRACR           0x88C
  83 #define RCC_PLL3CSGR            0x890
  84 #define RCC_PLL4CR              0x894
  85 #define RCC_PLL4CFGR1           0x898
  86 #define RCC_PLL4CFGR2           0x89C
  87 #define RCC_PLL4FRACR           0x8A0
  88 #define RCC_PLL4CSGR            0x8A4
  89 #define RCC_I2C12CKSELR         0x8C0
  90 #define RCC_I2C35CKSELR         0x8C4
  91 #define RCC_UART6CKSELR         0x8E4
  92 #define RCC_UART24CKSELR        0x8E8
  93 #define RCC_UART35CKSELR        0x8EC
  94 #define RCC_UART78CKSELR        0x8F0
  95 #define RCC_SDMMC12CKSELR       0x8F4
  96 #define RCC_SDMMC3CKSELR        0x8F8
  97 #define RCC_ETHCKSELR           0x8FC
  98 #define RCC_QSPICKSELR          0x900
  99 #define RCC_FMCCKSELR           0x904
 100 #define RCC_USBCKSELR           0x91C
 101 #define RCC_DSICKSELR           0x924
 102 #define RCC_MP_APB1ENSETR       0xA00
 103 #define RCC_MP_APB2ENSETR       0XA08
 104 #define RCC_MP_APB3ENSETR       0xA10
 105 #define RCC_MP_AHB2ENSETR       0xA18
 106 #define RCC_MP_AHB4ENSETR       0xA28
 107
 108 /* used for most of SELR register */
 109 #define RCC_SELR_SRC_MASK       GENMASK(2, 0)
 110 #define RCC_SELR_SRCRDY         BIT(31)
 111
 112 /* Values of RCC_MPCKSELR register */
 113 #define RCC_MPCKSELR_HSI        0
 114 #define RCC_MPCKSELR_HSE        1
 115 #define RCC_MPCKSELR_PLL        2
 116 #define RCC_MPCKSELR_PLL_MPUDIV 3
 117
 118 /* Values of RCC_ASSCKSELR register */
 119 #define RCC_ASSCKSELR_HSI       0
 120 #define RCC_ASSCKSELR_HSE       1
 121 #define RCC_ASSCKSELR_PLL       2
 122
 123 /* Values of RCC_MSSCKSELR register */
 124 #define RCC_MSSCKSELR_HSI       0
 125 #define RCC_MSSCKSELR_HSE       1
 126 #define RCC_MSSCKSELR_CSI       2
 127 #define RCC_MSSCKSELR_PLL       3
 128
 129 /* Values of RCC_CPERCKSELR register */
 130 #define RCC_CPERCKSELR_HSI      0
 131 #define RCC_CPERCKSELR_CSI      1
 132 #define RCC_CPERCKSELR_HSE      2
 133
 134 /* used for most of DIVR register : max div for RTC */
 135 #define RCC_DIVR_DIV_MASK       GENMASK(5, 0)
 136 #define RCC_DIVR_DIVRDY         BIT(31)
 137
 138 /* Masks for specific DIVR registers */
 139 #define RCC_APBXDIV_MASK        GENMASK(2, 0)
 140 #define RCC_MPUDIV_MASK         GENMASK(2, 0)
 141 #define RCC_AXIDIV_MASK         GENMASK(2, 0)
 142 #define RCC_MCUDIV_MASK         GENMASK(3, 0)
 143
 144 /*  offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
 145 #define RCC_MP_ENCLRR_OFFSET    4
 146
 147 /* Fields of RCC_BDCR register */
 148 #define RCC_BDCR_LSEON          BIT(0)
 149 #define RCC_BDCR_LSEBYP         BIT(1)
 150 #define RCC_BDCR_LSERDY         BIT(2)
 151 #define RCC_BDCR_LSEDRV_MASK    GENMASK(5, 4)
 152 #define RCC_BDCR_LSEDRV_SHIFT   4
 153 #define RCC_BDCR_LSECSSON       BIT(8)
 154 #define RCC_BDCR_RTCCKEN        BIT(20)
 155 #define RCC_BDCR_RTCSRC_MASK    GENMASK(17, 16)
 156 #define RCC_BDCR_RTCSRC_SHIFT   16
 157
 158 /* Fields of RCC_RDLSICR register */
 159 #define RCC_RDLSICR_LSION       BIT(0)
 160 #define RCC_RDLSICR_LSIRDY      BIT(1)
 161
 162 /* used for ALL PLLNCR registers */
 163 #define RCC_PLLNCR_PLLON        BIT(0)
 164 #define RCC_PLLNCR_PLLRDY       BIT(1)
 165 #define RCC_PLLNCR_DIVPEN       BIT(4)
 166 #define RCC_PLLNCR_DIVQEN       BIT(5)
 167 #define RCC_PLLNCR_DIVREN       BIT(6)
 168 #define RCC_PLLNCR_DIVEN_SHIFT  4
 169
 170 /* used for ALL PLLNCFGR1 registers */
 171 #define RCC_PLLNCFGR1_DIVM_SHIFT        16
 172 #define RCC_PLLNCFGR1_DIVM_MASK         GENMASK(21, 16)
 173 #define RCC_PLLNCFGR1_DIVN_SHIFT        0
 174 #define RCC_PLLNCFGR1_DIVN_MASK         GENMASK(8, 0)
 175 /* only for PLL3 and PLL4 */
 176 #define RCC_PLLNCFGR1_IFRGE_SHIFT       24
 177 #define RCC_PLLNCFGR1_IFRGE_MASK        GENMASK(25, 24)
 178
 179 /* used for ALL PLLNCFGR2 registers , using stm32mp1_div_id */
 180 #define RCC_PLLNCFGR2_SHIFT(div_id)     ((div_id) * 8)
 181 #define RCC_PLLNCFGR2_DIVX_MASK         GENMASK(6, 0)
 182 #define RCC_PLLNCFGR2_DIVP_SHIFT        RCC_PLLNCFGR2_SHIFT(_DIV_P)
 183 #define RCC_PLLNCFGR2_DIVP_MASK         GENMASK(6, 0)
 184 #define RCC_PLLNCFGR2_DIVQ_SHIFT        RCC_PLLNCFGR2_SHIFT(_DIV_Q)
 185 #define RCC_PLLNCFGR2_DIVQ_MASK         GENMASK(14, 8)
 186 #define RCC_PLLNCFGR2_DIVR_SHIFT        RCC_PLLNCFGR2_SHIFT(_DIV_R)
 187 #define RCC_PLLNCFGR2_DIVR_MASK         GENMASK(22, 16)
 188
 189 /* used for ALL PLLNFRACR registers */
 190 #define RCC_PLLNFRACR_FRACV_SHIFT       3
 191 #define RCC_PLLNFRACR_FRACV_MASK        GENMASK(15, 3)
 192 #define RCC_PLLNFRACR_FRACLE            BIT(16)
 193
 194 /* used for ALL PLLNCSGR registers */
 195 #define RCC_PLLNCSGR_INC_STEP_SHIFT     16
 196 #define RCC_PLLNCSGR_INC_STEP_MASK      GENMASK(30, 16)
 197 #define RCC_PLLNCSGR_MOD_PER_SHIFT      0
 198 #define RCC_PLLNCSGR_MOD_PER_MASK       GENMASK(12, 0)
 199 #define RCC_PLLNCSGR_SSCG_MODE_SHIFT    15
 200 #define RCC_PLLNCSGR_SSCG_MODE_MASK     BIT(15)
 201
 202 /* used for RCC_OCENSETR and RCC_OCENCLRR registers */
 203 #define RCC_OCENR_HSION                 BIT(0)
 204 #define RCC_OCENR_CSION                 BIT(4)
 205 #define RCC_OCENR_HSEON                 BIT(8)
 206 #define RCC_OCENR_HSEBYP                BIT(10)
 207 #define RCC_OCENR_HSECSSON              BIT(11)
 208
 209 /* Fields of RCC_OCRDYR register */
 210 #define RCC_OCRDYR_HSIRDY               BIT(0)
 211 #define RCC_OCRDYR_HSIDIVRDY            BIT(2)
 212 #define RCC_OCRDYR_CSIRDY               BIT(4)
 213 #define RCC_OCRDYR_HSERDY               BIT(8)
 214
 215 /* Fields of DDRITFCR register */
 216 #define RCC_DDRITFCR_DDRCKMOD_MASK      GENMASK(22, 20)
 217 #define RCC_DDRITFCR_DDRCKMOD_SHIFT     20
 218 #define RCC_DDRITFCR_DDRCKMOD_SSR       0
 219
 220 /* Fields of RCC_HSICFGR register */
 221 #define RCC_HSICFGR_HSIDIV_MASK         GENMASK(1, 0)
 222
 223 /* used for MCO related operations */
 224 #define RCC_MCOCFG_MCOON                BIT(12)
 225 #define RCC_MCOCFG_MCODIV_MASK          GENMASK(7, 4)
 226 #define RCC_MCOCFG_MCODIV_SHIFT         4
 227 #define RCC_MCOCFG_MCOSRC_MASK          GENMASK(2, 0)
 228
 229 enum stm32mp1_parent_id {
 230 /*
 231  * _HSI, _HSE, _CSI, _LSI, _LSE should not be moved
 232  * they are used as index in osc[] as entry point
 233  */
 234         _HSI,
 235         _HSE,
 236         _CSI,
 237         _LSI,
 238         _LSE,
 239         _I2S_CKIN,
 240         _USB_PHY_48,
 241         NB_OSC,
 242
 243 /* other parent source */
 244         _HSI_KER = NB_OSC,
 245         _HSE_KER,
 246         _HSE_KER_DIV2,
 247         _CSI_KER,
 248         _PLL1_P,
 249         _PLL1_Q,
 250         _PLL1_R,
 251         _PLL2_P,
 252         _PLL2_Q,
 253         _PLL2_R,
 254         _PLL3_P,
 255         _PLL3_Q,
 256         _PLL3_R,
 257         _PLL4_P,
 258         _PLL4_Q,
 259         _PLL4_R,
 260         _ACLK,
 261         _PCLK1,
 262         _PCLK2,
 263         _PCLK3,
 264         _PCLK4,
 265         _PCLK5,
 266         _HCLK6,
 267         _HCLK2,
 268         _CK_PER,
 269         _CK_MPU,
 270         _CK_MCU,
 271         _DSI_PHY,
 272         _PARENT_NB,
 273         _UNKNOWN_ID = 0xff,
 274 };
 275
 276 enum stm32mp1_parent_sel {
 277         _I2C12_SEL,
 278         _I2C35_SEL,
 279         _I2C46_SEL,
 280         _UART6_SEL,
 281         _UART24_SEL,
 282         _UART35_SEL,
 283         _UART78_SEL,
 284         _SDMMC12_SEL,
 285         _SDMMC3_SEL,
 286         _ETH_SEL,
 287         _QSPI_SEL,
 288         _FMC_SEL,
 289         _USBPHY_SEL,
 290         _USBO_SEL,
 291         _STGEN_SEL,
 292         _DSI_SEL,
 293         _PARENT_SEL_NB,
 294         _UNKNOWN_SEL = 0xff,
 295 };
 296
 297 enum stm32mp1_pll_id {
 298         _PLL1,
 299         _PLL2,
 300         _PLL3,
 301         _PLL4,
 302         _PLL_NB
 303 };
 304
 305 enum stm32mp1_div_id {
 306         _DIV_P,
 307         _DIV_Q,
 308         _DIV_R,
 309         _DIV_NB,
 310 };
 311
 312 enum stm32mp1_clksrc_id {
 313         CLKSRC_MPU,
 314         CLKSRC_AXI,
 315         CLKSRC_MCU,
 316         CLKSRC_PLL12,
 317         CLKSRC_PLL3,
 318         CLKSRC_PLL4,
 319         CLKSRC_RTC,
 320         CLKSRC_MCO1,
 321         CLKSRC_MCO2,
 322         CLKSRC_NB
 323 };
 324
 325 enum stm32mp1_clkdiv_id {
 326         CLKDIV_MPU,
 327         CLKDIV_AXI,
 328         CLKDIV_MCU,
 329         CLKDIV_APB1,
 330         CLKDIV_APB2,
 331         CLKDIV_APB3,
 332         CLKDIV_APB4,
 333         CLKDIV_APB5,
 334         CLKDIV_RTC,
 335         CLKDIV_MCO1,
 336         CLKDIV_MCO2,
 337         CLKDIV_NB
 338 };
 339
 340 enum stm32mp1_pllcfg {
 341         PLLCFG_M,
 342         PLLCFG_N,
 343         PLLCFG_P,
 344         PLLCFG_Q,
 345         PLLCFG_R,
 346         PLLCFG_O,
 347         PLLCFG_NB
 348 };
 349
 350 enum stm32mp1_pllcsg {
 351         PLLCSG_MOD_PER,
 352         PLLCSG_INC_STEP,
 353         PLLCSG_SSCG_MODE,
 354         PLLCSG_NB
 355 };
 356
 357 enum stm32mp1_plltype {
 358         PLL_800,
 359         PLL_1600,
 360         PLL_TYPE_NB
 361 };
 362
 363 struct stm32mp1_pll {
 364         u8 refclk_min;
 365         u8 refclk_max;
 366         u8 divn_max;
 367 };
 368
 369 struct stm32mp1_clk_gate {
 370         u16 offset;
 371         u8 bit;
 372         u8 index;
 373         u8 set_clr;
 374         u8 sel;
 375         u8 fixed;
 376 };
 377
 378 struct stm32mp1_clk_sel {
 379         u16 offset;
 380         u8 src;
 381         u8 msk;
 382         u8 nb_parent;
 383         const u8 *parent;
 384 };
 385
 386 #define REFCLK_SIZE 4
 387 struct stm32mp1_clk_pll {
 388         enum stm32mp1_plltype plltype;
 389         u16 rckxselr;
 390         u16 pllxcfgr1;
 391         u16 pllxcfgr2;
 392         u16 pllxfracr;
 393         u16 pllxcr;
 394         u16 pllxcsgr;
 395         u8 refclk[REFCLK_SIZE];
 396 };
 397
 398 struct stm32mp1_clk_data {
 399         const struct stm32mp1_clk_gate *gate;
 400         const struct stm32mp1_clk_sel *sel;
 401         const struct stm32mp1_clk_pll *pll;
 402         const int nb_gate;
 403 };
 404
 405 struct stm32mp1_clk_priv {
 406         fdt_addr_t base;
 407         const struct stm32mp1_clk_data *data;
 408         ulong osc[NB_OSC];
 409         struct udevice *osc_dev[NB_OSC];
 410 };
 411
 412 #define STM32MP1_CLK(off, b, idx, s)            \
 413         {                                       \
 414                 .offset = (off),                \
 415                 .bit = (b),                     \
 416                 .index = (idx),                 \
 417                 .set_clr = 0,                   \
 418                 .sel = (s),                     \
 419                 .fixed = _UNKNOWN_ID,           \
 420         }
 421
 422 #define STM32MP1_CLK_F(off, b, idx, f)          \
 423         {                                       \
 424                 .offset = (off),                \
 425                 .bit = (b),                     \
 426                 .index = (idx),                 \
 427                 .set_clr = 0,                   \
 428                 .sel = _UNKNOWN_SEL,            \
 429                 .fixed = (f),                   \
 430         }
 431
 432 #define STM32MP1_CLK_SET_CLR(off, b, idx, s)    \
 433         {                                       \
 434                 .offset = (off),                \
 435                 .bit = (b),                     \
 436                 .index = (idx),                 \
 437                 .set_clr = 1,                   \
 438                 .sel = (s),                     \
 439                 .fixed = _UNKNOWN_ID,           \
 440         }
 441
 442 #define STM32MP1_CLK_SET_CLR_F(off, b, idx, f)  \
 443         {                                       \
 444                 .offset = (off),                \
 445                 .bit = (b),                     \
 446                 .index = (idx),                 \
 447                 .set_clr = 1,                   \
 448                 .sel = _UNKNOWN_SEL,            \
 449                 .fixed = (f),                   \
 450         }
 451
 452 #define STM32MP1_CLK_PARENT(idx, off, s, m, p)   \
 453         [(idx)] = {                             \
 454                 .offset = (off),                \
 455                 .src = (s),                     \
 456                 .msk = (m),                     \
 457                 .parent = (p),                  \
 458                 .nb_parent = ARRAY_SIZE((p))    \
 459         }
 460
 461 #define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, off4, off5, off6,\
 462                         p1, p2, p3, p4) \
 463         [(idx)] = {                             \
 464                 .plltype = (type),                      \
 465                 .rckxselr = (off1),             \
 466                 .pllxcfgr1 = (off2),            \
 467                 .pllxcfgr2 = (off3),            \
 468                 .pllxfracr = (off4),            \
 469                 .pllxcr = (off5),               \
 470                 .pllxcsgr = (off6),             \
 471                 .refclk[0] = (p1),              \
 472                 .refclk[1] = (p2),              \
 473                 .refclk[2] = (p3),              \
 474                 .refclk[3] = (p4),              \
 475         }
 476
 477 static const u8 stm32mp1_clks[][2] = {
 478         {CK_PER, _CK_PER},
 479         {CK_MPU, _CK_MPU},
 480         {CK_AXI, _ACLK},
 481         {CK_MCU, _CK_MCU},
 482         {CK_HSE, _HSE},
 483         {CK_CSI, _CSI},
 484         {CK_LSI, _LSI},
 485         {CK_LSE, _LSE},
 486         {CK_HSI, _HSI},
 487         {CK_HSE_DIV2, _HSE_KER_DIV2},
 488 };
 489
 490 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
 491         STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL),
 492         STM32MP1_CLK(RCC_DDRITFCR, 1, DDRC1LP, _UNKNOWN_SEL),
 493         STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL),
 494         STM32MP1_CLK(RCC_DDRITFCR, 3, DDRC2LP, _UNKNOWN_SEL),
 495         STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
 496         STM32MP1_CLK(RCC_DDRITFCR, 5, DDRPHYCLP, _UNKNOWN_SEL),
 497         STM32MP1_CLK(RCC_DDRITFCR, 6, DDRCAPB, _UNKNOWN_SEL),
 498         STM32MP1_CLK(RCC_DDRITFCR, 7, DDRCAPBLP, _UNKNOWN_SEL),
 499         STM32MP1_CLK(RCC_DDRITFCR, 8, AXIDCG, _UNKNOWN_SEL),
 500         STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL),
 501         STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL),
 502
 503         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
 504         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
 505         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
 506         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL),
 507         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL),
 508         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL),
 509         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL),
 510         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL),
 511         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL),
 512         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
 513
 514         STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
 515
 516         STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3),
 517
 518         STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 0, LTDC_PX, _PLL4_Q),
 519         STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 4, DSI_PX, _PLL4_Q),
 520         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 4, DSI_K, _DSI_SEL),
 521         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
 522         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
 523         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
 524
 525         STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
 526         STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
 527
 528         STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
 529         STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
 530
 531         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
 532         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
 533         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
 534         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL),
 535         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL),
 536         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL),
 537         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL),
 538         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL),
 539         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL),
 540         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL),
 541         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
 542
 543         STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
 544
 545         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK, _UNKNOWN_SEL),
 546         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL),
 547         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL),
 548         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 10, ETHMAC_K, _ETH_SEL),
 549         STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK),
 550         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
 551         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
 552         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL),
 553         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL),
 554         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL),
 555
 556         STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
 557 };
 558
 559 static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
 560 static const u8 i2c35_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
 561 static const u8 i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER};
 562 static const u8 uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
 563                                         _HSE_KER};
 564 static const u8 uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 565                                          _HSE_KER};
 566 static const u8 uart35_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 567                                          _HSE_KER};
 568 static const u8 uart78_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 569                                          _HSE_KER};
 570 static const u8 sdmmc12_parents[] = {_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER};
 571 static const u8 sdmmc3_parents[] = {_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER};
 572 static const u8 eth_parents[] = {_PLL4_P, _PLL3_Q};
 573 static const u8 qspi_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
 574 static const u8 fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
 575 static const u8 usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2};
 576 static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48};
 577 static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER};
 578 static const u8 dsi_parents[] = {_DSI_PHY, _PLL4_P};
 579
 580 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
 581         STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents),
 582         STM32MP1_CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents),
 583         STM32MP1_CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents),
 584         STM32MP1_CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents),
 585         STM32MP1_CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7,
 586                             uart24_parents),
 587         STM32MP1_CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7,
 588                             uart35_parents),
 589         STM32MP1_CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7,
 590                             uart78_parents),
 591         STM32MP1_CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7,
 592                             sdmmc12_parents),
 593         STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7,
 594                             sdmmc3_parents),
 595         STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents),
 596         STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents),
 597         STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents),
 598         STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents),
 599         STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
 600         STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
 601         STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents),
 602 };
 603
 604 #ifdef STM32MP1_CLOCK_TREE_INIT
 605 /* define characteristic of PLL according type */
 606 #define DIVN_MIN        24
 607 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
 608         [PLL_800] = {
 609                 .refclk_min = 4,
 610                 .refclk_max = 16,
 611                 .divn_max = 99,
 612                 },
 613         [PLL_1600] = {
 614                 .refclk_min = 8,
 615                 .refclk_max = 16,
 616                 .divn_max = 199,
 617                 },
 618 };
 619 #endif /* STM32MP1_CLOCK_TREE_INIT */
 620
 621 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = {
 622         STM32MP1_CLK_PLL(_PLL1, PLL_1600,
 623                          RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2,
 624                          RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR,
 625                          _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
 626         STM32MP1_CLK_PLL(_PLL2, PLL_1600,
 627                          RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2,
 628                          RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR,
 629                          _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
 630         STM32MP1_CLK_PLL(_PLL3, PLL_800,
 631                          RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2,
 632                          RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR,
 633                          _HSI, _HSE, _CSI, _UNKNOWN_ID),
 634         STM32MP1_CLK_PLL(_PLL4, PLL_800,
 635                          RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2,
 636                          RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR,
 637                          _HSI, _HSE, _CSI, _I2S_CKIN),
 638 };
 639
 640 /* Prescaler table lookups for clock computation */
 641 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */
 642 static const u8 stm32mp1_mcu_div[16] = {
 643         0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9
 644 };
 645
 646 /* div = /1 /2 /4 /8 /16 : same divider for pmu and apbx*/
 647 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div
 648 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div
 649 static const u8 stm32mp1_mpu_apbx_div[8] = {
 650         0, 1, 2, 3, 4, 4, 4, 4
 651 };
 652
 653 /* div = /1 /2 /3 /4 */
 654 static const u8 stm32mp1_axi_div[8] = {
 655         1, 2, 3, 4, 4, 4, 4, 4
 656 };
 657
 658 #ifdef DEBUG
 659 static const char * const stm32mp1_clk_parent_name[_PARENT_NB] = {
 660         [_HSI] = "HSI",
 661         [_HSE] = "HSE",
 662         [_CSI] = "CSI",
 663         [_LSI] = "LSI",
 664         [_LSE] = "LSE",
 665         [_I2S_CKIN] = "I2S_CKIN",
 666         [_HSI_KER] = "HSI_KER",
 667         [_HSE_KER] = "HSE_KER",
 668         [_HSE_KER_DIV2] = "HSE_KER_DIV2",
 669         [_CSI_KER] = "CSI_KER",
 670         [_PLL1_P] = "PLL1_P",
 671         [_PLL1_Q] = "PLL1_Q",
 672         [_PLL1_R] = "PLL1_R",
 673         [_PLL2_P] = "PLL2_P",
 674         [_PLL2_Q] = "PLL2_Q",
 675         [_PLL2_R] = "PLL2_R",
 676         [_PLL3_P] = "PLL3_P",
 677         [_PLL3_Q] = "PLL3_Q",
 678         [_PLL3_R] = "PLL3_R",
 679         [_PLL4_P] = "PLL4_P",
 680         [_PLL4_Q] = "PLL4_Q",
 681         [_PLL4_R] = "PLL4_R",
 682         [_ACLK] = "ACLK",
 683         [_PCLK1] = "PCLK1",
 684         [_PCLK2] = "PCLK2",
 685         [_PCLK3] = "PCLK3",
 686         [_PCLK4] = "PCLK4",
 687         [_PCLK5] = "PCLK5",
 688         [_HCLK6] = "KCLK6",
 689         [_HCLK2] = "HCLK2",
 690         [_CK_PER] = "CK_PER",
 691         [_CK_MPU] = "CK_MPU",
 692         [_CK_MCU] = "CK_MCU",
 693         [_USB_PHY_48] = "USB_PHY_48",
 694         [_DSI_PHY] = "DSI_PHY_PLL",
 695 };
 696
 697 static const char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
 698         [_I2C12_SEL] = "I2C12",
 699         [_I2C35_SEL] = "I2C35",
 700         [_I2C46_SEL] = "I2C46",
 701         [_UART6_SEL] = "UART6",
 702         [_UART24_SEL] = "UART24",
 703         [_UART35_SEL] = "UART35",
 704         [_UART78_SEL] = "UART78",
 705         [_SDMMC12_SEL] = "SDMMC12",
 706         [_SDMMC3_SEL] = "SDMMC3",
 707         [_ETH_SEL] = "ETH",
 708         [_QSPI_SEL] = "QSPI",
 709         [_FMC_SEL] = "FMC",
 710         [_USBPHY_SEL] = "USBPHY",
 711         [_USBO_SEL] = "USBO",
 712         [_STGEN_SEL] = "STGEN",
 713         [_DSI_SEL] = "DSI",
 714 };
 715 #endif
 716
 717 static const struct stm32mp1_clk_data stm32mp1_data = {
 718         .gate = stm32mp1_clk_gate,
 719         .sel = stm32mp1_clk_sel,
 720         .pll = stm32mp1_clk_pll,
 721         .nb_gate = ARRAY_SIZE(stm32mp1_clk_gate),
 722 };
 723
 724 static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx)
 725 {
 726         if (idx >= NB_OSC) {
 727                 debug("%s: clk id %d not found\n", __func__, idx);
 728                 return 0;
 729         }
 730
 731         debug("%s: clk id %d = %x : %ld kHz\n", __func__, idx,
 732               (u32)priv->osc[idx], priv->osc[idx] / 1000);
 733
 734         return priv->osc[idx];
 735 }
 736
 737 static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id)
 738 {
 739         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 740         int i, nb_clks = priv->data->nb_gate;
 741
 742         for (i = 0; i < nb_clks; i++) {
 743                 if (gate[i].index == id)
 744                         break;
 745         }
 746
 747         if (i == nb_clks) {
 748                 printf("%s: clk id %d not found\n", __func__, (u32)id);
 749                 return -EINVAL;
 750         }
 751
 752         return i;
 753 }
 754
 755 static int stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv,
 756                                 int i)
 757 {
 758         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 759
 760         if (gate[i].sel > _PARENT_SEL_NB) {
 761                 printf("%s: parents for clk id %d not found\n",
 762                        __func__, i);
 763                 return -EINVAL;
 764         }
 765
 766         return gate[i].sel;
 767 }
 768
 769 static int stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv *priv,
 770                                          int i)
 771 {
 772         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 773
 774         if (gate[i].fixed == _UNKNOWN_ID)
 775                 return -ENOENT;
 776
 777         return gate[i].fixed;
 778 }
 779
 780 static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv,
 781                                    unsigned long id)
 782 {
 783         const struct stm32mp1_clk_sel *sel = priv->data->sel;
 784         int i;
 785         int s, p;
 786
 787         for (i = 0; i < ARRAY_SIZE(stm32mp1_clks); i++)
 788                 if (stm32mp1_clks[i][0] == id)
 789                         return stm32mp1_clks[i][1];
 790
 791         i = stm32mp1_clk_get_id(priv, id);
 792         if (i < 0)
 793                 return i;
 794
 795         p = stm32mp1_clk_get_fixed_parent(priv, i);
 796         if (p >= 0 && p < _PARENT_NB)
 797                 return p;
 798
 799         s = stm32mp1_clk_get_sel(priv, i);
 800         if (s < 0)
 801                 return s;
 802
 803         p = (readl(priv->base + sel[s].offset) >> sel[s].src) & sel[s].msk;
 804
 805         if (p < sel[s].nb_parent) {
 806 #ifdef DEBUG
 807                 debug("%s: %s clock is the parent %s of clk id %d\n", __func__,
 808                       stm32mp1_clk_parent_name[sel[s].parent[p]],
 809                       stm32mp1_clk_parent_sel_name[s],
 810                       (u32)id);
 811 #endif
 812                 return sel[s].parent[p];
 813         }
 814
 815         pr_err("%s: no parents defined for clk id %d\n",
 816                __func__, (u32)id);
 817
 818         return -EINVAL;
 819 }
 820
 821 static ulong  pll_get_fref_ck(struct stm32mp1_clk_priv *priv,
 822                               int pll_id)
 823 {
 824         const struct stm32mp1_clk_pll *pll = priv->data->pll;
 825         u32 selr;
 826         int src;
 827         ulong refclk;
 828
 829         /* Get current refclk */
 830         selr = readl(priv->base + pll[pll_id].rckxselr);
 831         src = selr & RCC_SELR_SRC_MASK;
 832
 833         refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]);
 834         debug("PLL%d : selr=%x refclk = %d kHz\n",
 835               pll_id, selr, (u32)(refclk / 1000));
 836
 837         return refclk;
 838 }
 839
 840 /*
 841  * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL
 842  * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1)
 843  * - PLL3 & PLL4 => return VCO     with Fpll_y_ck = FVCO / (DIVy + 1)
 844  * => in all the case Fpll_y_ck = pll_get_fvco() / (DIVy + 1)
 845  */
 846 static ulong pll_get_fvco(struct stm32mp1_clk_priv *priv,
 847                           int pll_id)
 848 {
 849         const struct stm32mp1_clk_pll *pll = priv->data->pll;
 850         int divm, divn;
 851         ulong refclk, fvco;
 852         u32 cfgr1, fracr;
 853
 854         cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1);
 855         fracr = readl(priv->base + pll[pll_id].pllxfracr);
 856
 857         divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
 858         divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
 859
 860         debug("PLL%d : cfgr1=%x fracr=%x DIVN=%d DIVM=%d\n",
 861               pll_id, cfgr1, fracr, divn, divm);
 862
 863         refclk = pll_get_fref_ck(priv, pll_id);
 864
 865         /* with FRACV :
 866          *   Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1)
 867          * without FRACV
 868          *   Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1)
 869          */
 870         if (fracr & RCC_PLLNFRACR_FRACLE) {
 871                 u32 fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK)
 872                             >> RCC_PLLNFRACR_FRACV_SHIFT;
 873                 fvco = (ulong)lldiv((unsigned long long)refclk *
 874                                      (((divn + 1) << 13) + fracv),
 875                                      ((unsigned long long)(divm + 1)) << 13);
 876         } else {
 877                 fvco = (ulong)(refclk * (divn + 1) / (divm + 1));
 878         }
 879         debug("PLL%d : %s = %ld\n", pll_id, __func__, fvco);
 880
 881         return fvco;
 882 }
 883
 884 static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
 885                                     int pll_id, int div_id)
 886 {
 887         const struct stm32mp1_clk_pll *pll = priv->data->pll;
 888         int divy;
 889         ulong dfout;
 890         u32 cfgr2;
 891
 892         debug("%s(%d, %d)\n", __func__, pll_id, div_id);
 893         if (div_id >= _DIV_NB)
 894                 return 0;
 895
 896         cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2);
 897         divy = (cfgr2 >> RCC_PLLNCFGR2_SHIFT(div_id)) & RCC_PLLNCFGR2_DIVX_MASK;
 898
 899         debug("PLL%d : cfgr2=%x DIVY=%d\n", pll_id, cfgr2, divy);
 900
 901         dfout = pll_get_fvco(priv, pll_id) / (divy + 1);
 902         debug("        => dfout = %d kHz\n", (u32)(dfout / 1000));
 903
 904         return dfout;
 905 }
 906
 907 static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
 908 {
 909         u32 reg;
 910         ulong clock = 0;
 911
 912         switch (p) {
 913         case _CK_MPU:
 914         /* MPU sub system */
 915                 reg = readl(priv->base + RCC_MPCKSELR);
 916                 switch (reg & RCC_SELR_SRC_MASK) {
 917                 case RCC_MPCKSELR_HSI:
 918                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
 919                         break;
 920                 case RCC_MPCKSELR_HSE:
 921                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
 922                         break;
 923                 case RCC_MPCKSELR_PLL:
 924                 case RCC_MPCKSELR_PLL_MPUDIV:
 925                         clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P);
 926                         if (p == RCC_MPCKSELR_PLL_MPUDIV) {
 927                                 reg = readl(priv->base + RCC_MPCKDIVR);
 928                                 clock /= stm32mp1_mpu_div[reg &
 929                                                           RCC_MPUDIV_MASK];
 930                         }
 931                         break;
 932                 }
 933                 break;
 934         /* AXI sub system */
 935         case _ACLK:
 936         case _HCLK2:
 937         case _HCLK6:
 938         case _PCLK4:
 939         case _PCLK5:
 940                 reg = readl(priv->base + RCC_ASSCKSELR);
 941                 switch (reg & RCC_SELR_SRC_MASK) {
 942                 case RCC_ASSCKSELR_HSI:
 943                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
 944                         break;
 945                 case RCC_ASSCKSELR_HSE:
 946                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
 947                         break;
 948                 case RCC_ASSCKSELR_PLL:
 949                         clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P);
 950                         break;
 951                 }
 952
 953                 /* System clock divider */
 954                 reg = readl(priv->base + RCC_AXIDIVR);
 955                 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK];
 956
 957                 switch (p) {
 958                 case _PCLK4:
 959                         reg = readl(priv->base + RCC_APB4DIVR);
 960                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
 961                         break;
 962                 case _PCLK5:
 963                         reg = readl(priv->base + RCC_APB5DIVR);
 964                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
 965                         break;
 966                 default:
 967                         break;
 968                 }
 969                 break;
 970         /* MCU sub system */
 971         case _CK_MCU:
 972         case _PCLK1:
 973         case _PCLK2:
 974         case _PCLK3:
 975                 reg = readl(priv->base + RCC_MSSCKSELR);
 976                 switch (reg & RCC_SELR_SRC_MASK) {
 977                 case RCC_MSSCKSELR_HSI:
 978                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
 979                         break;
 980                 case RCC_MSSCKSELR_HSE:
 981                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
 982                         break;
 983                 case RCC_MSSCKSELR_CSI:
 984                         clock = stm32mp1_clk_get_fixed(priv, _CSI);
 985                         break;
 986                 case RCC_MSSCKSELR_PLL:
 987                         clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_P);
 988                         break;
 989                 }
 990
 991                 /* MCU clock divider */
 992                 reg = readl(priv->base + RCC_MCUDIVR);
 993                 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK];
 994
 995                 switch (p) {
 996                 case _PCLK1:
 997                         reg = readl(priv->base + RCC_APB1DIVR);
 998                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
 999                         break;
1000                 case _PCLK2:
1001                         reg = readl(priv->base + RCC_APB2DIVR);
1002                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1003                         break;
1004                 case _PCLK3:
1005                         reg = readl(priv->base + RCC_APB3DIVR);
1006                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1007                         break;
1008                 case _CK_MCU:
1009                 default:
1010                         break;
1011                 }
1012                 break;
1013         case _CK_PER:
1014                 reg = readl(priv->base + RCC_CPERCKSELR);
1015                 switch (reg & RCC_SELR_SRC_MASK) {
1016                 case RCC_CPERCKSELR_HSI:
1017                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
1018                         break;
1019                 case RCC_CPERCKSELR_HSE:
1020                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
1021                         break;
1022                 case RCC_CPERCKSELR_CSI:
1023                         clock = stm32mp1_clk_get_fixed(priv, _CSI);
1024                         break;
1025                 }
1026                 break;
1027         case _HSI:
1028         case _HSI_KER:
1029                 clock = stm32mp1_clk_get_fixed(priv, _HSI);
1030                 break;
1031         case _CSI:
1032         case _CSI_KER:
1033                 clock = stm32mp1_clk_get_fixed(priv, _CSI);
1034                 break;
1035         case _HSE:
1036         case _HSE_KER:
1037         case _HSE_KER_DIV2:
1038                 clock = stm32mp1_clk_get_fixed(priv, _HSE);
1039                 if (p == _HSE_KER_DIV2)
1040                         clock >>= 1;
1041                 break;
1042         case _LSI:
1043                 clock = stm32mp1_clk_get_fixed(priv, _LSI);
1044                 break;
1045         case _LSE:
1046                 clock = stm32mp1_clk_get_fixed(priv, _LSE);
1047                 break;
1048         /* PLL */
1049         case _PLL1_P:
1050         case _PLL1_Q:
1051         case _PLL1_R:
1052                 clock = stm32mp1_read_pll_freq(priv, _PLL1, p - _PLL1_P);
1053                 break;
1054         case _PLL2_P:
1055         case _PLL2_Q:
1056         case _PLL2_R:
1057                 clock = stm32mp1_read_pll_freq(priv, _PLL2, p - _PLL2_P);
1058                 break;
1059         case _PLL3_P:
1060         case _PLL3_Q:
1061         case _PLL3_R:
1062                 clock = stm32mp1_read_pll_freq(priv, _PLL3, p - _PLL3_P);
1063                 break;
1064         case _PLL4_P:
1065         case _PLL4_Q:
1066         case _PLL4_R:
1067                 clock = stm32mp1_read_pll_freq(priv, _PLL4, p - _PLL4_P);
1068                 break;
1069         /* other */
1070         case _USB_PHY_48:
1071                 clock = stm32mp1_clk_get_fixed(priv, _USB_PHY_48);
1072                 break;
1073         case _DSI_PHY:
1074         {
1075                 struct clk clk;
1076                 struct udevice *dev = NULL;
1077
1078                 if (!uclass_get_device_by_name(UCLASS_CLK, "ck_dsi_phy",
1079                                                &dev)) {
1080                         if (clk_request(dev, &clk)) {
1081                                 pr_err("ck_dsi_phy request");
1082                         } else {
1083                                 clk.id = 0;
1084                                 clock = clk_get_rate(&clk);
1085                         }
1086                 }
1087                 break;
1088         }
1089         default:
1090                 break;
1091         }
1092
1093         debug("%s(%d) clock = %lx : %ld kHz\n",
1094               __func__, p, clock, clock / 1000);
1095
1096         return clock;
1097 }
1098
1099 static int stm32mp1_clk_enable(struct clk *clk)
1100 {
1101         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1102         const struct stm32mp1_clk_gate *gate = priv->data->gate;
1103         int i = stm32mp1_clk_get_id(priv, clk->id);
1104
1105         if (i < 0)
1106                 return i;
1107
1108         if (gate[i].set_clr)
1109                 writel(BIT(gate[i].bit), priv->base + gate[i].offset);
1110         else
1111                 setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1112
1113         debug("%s: id clock %d has been enabled\n", __func__, (u32)clk->id);
1114
1115         return 0;
1116 }
1117
1118 static int stm32mp1_clk_disable(struct clk *clk)
1119 {
1120         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1121         const struct stm32mp1_clk_gate *gate = priv->data->gate;
1122         int i = stm32mp1_clk_get_id(priv, clk->id);
1123
1124         if (i < 0)
1125                 return i;
1126
1127         if (gate[i].set_clr)
1128                 writel(BIT(gate[i].bit),
1129                        priv->base + gate[i].offset
1130                        + RCC_MP_ENCLRR_OFFSET);
1131         else
1132                 clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1133
1134         debug("%s: id clock %d has been disabled\n", __func__, (u32)clk->id);
1135
1136         return 0;
1137 }
1138
1139 static ulong stm32mp1_clk_get_rate(struct clk *clk)
1140 {
1141         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1142         int p = stm32mp1_clk_get_parent(priv, clk->id);
1143         ulong rate;
1144
1145         if (p < 0)
1146                 return 0;
1147
1148         rate = stm32mp1_clk_get(priv, p);
1149
1150 #ifdef DEBUG
1151         debug("%s: computed rate for id clock %d is %d (parent is %s)\n",
1152               __func__, (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]);
1153 #endif
1154         return rate;
1155 }
1156
1157 #ifdef STM32MP1_CLOCK_TREE_INIT
1158 static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset,
1159                                 u32 mask_on)
1160 {
1161         u32 address = rcc + offset;
1162
1163         if (enable)
1164                 setbits_le32(address, mask_on);
1165         else
1166                 clrbits_le32(address, mask_on);
1167 }
1168
1169 static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on)
1170 {
1171         if (enable)
1172                 setbits_le32(rcc + RCC_OCENSETR, mask_on);
1173         else
1174                 setbits_le32(rcc + RCC_OCENCLRR, mask_on);
1175 }
1176
1177 static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset,
1178                              u32 mask_rdy)
1179 {
1180         u32 mask_test = 0;
1181         u32 address = rcc + offset;
1182         u32 val;
1183         int ret;
1184
1185         if (enable)
1186                 mask_test = mask_rdy;
1187
1188         ret = readl_poll_timeout(address, val,
1189                                  (val & mask_rdy) == mask_test,
1190                                  TIMEOUT_1S);
1191
1192         if (ret)
1193                 pr_err("OSC %x @ %x timeout for enable=%d : 0x%x\n",
1194                        mask_rdy, address, enable, readl(address));
1195
1196         return ret;
1197 }
1198
1199 static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int lsedrv)
1200 {
1201         u32 value;
1202
1203         if (bypass)
1204                 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP);
1205
1206         /*
1207          * warning: not recommended to switch directly from "high drive"
1208          * to "medium low drive", and vice-versa.
1209          */
1210         value = (readl(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK)
1211                 >> RCC_BDCR_LSEDRV_SHIFT;
1212
1213         while (value != lsedrv) {
1214                 if (value > lsedrv)
1215                         value--;
1216                 else
1217                         value++;
1218
1219                 clrsetbits_le32(rcc + RCC_BDCR,
1220                                 RCC_BDCR_LSEDRV_MASK,
1221                                 value << RCC_BDCR_LSEDRV_SHIFT);
1222         }
1223
1224         stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON);
1225 }
1226
1227 static void stm32mp1_lse_wait(fdt_addr_t rcc)
1228 {
1229         stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY);
1230 }
1231
1232 static void stm32mp1_lsi_set(fdt_addr_t rcc, int enable)
1233 {
1234         stm32mp1_ls_osc_set(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSION);
1235         stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY);
1236 }
1237
1238 static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int css)
1239 {
1240         if (bypass)
1241                 setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_HSEBYP);
1242
1243         stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON);
1244         stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY);
1245
1246         if (css)
1247                 setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_HSECSSON);
1248 }
1249
1250 static void stm32mp1_csi_set(fdt_addr_t rcc, int enable)
1251 {
1252         stm32mp1_ls_osc_set(enable, rcc, RCC_OCENSETR, RCC_OCENR_CSION);
1253         stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY);
1254 }
1255
1256 static void stm32mp1_hsi_set(fdt_addr_t rcc, int enable)
1257 {
1258         stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_HSION);
1259         stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_HSIRDY);
1260 }
1261
1262 static int stm32mp1_set_hsidiv(fdt_addr_t rcc, u8 hsidiv)
1263 {
1264         u32 address = rcc + RCC_OCRDYR;
1265         u32 val;
1266         int ret;
1267
1268         clrsetbits_le32(rcc + RCC_HSICFGR,
1269                         RCC_HSICFGR_HSIDIV_MASK,
1270                         RCC_HSICFGR_HSIDIV_MASK & hsidiv);
1271
1272         ret = readl_poll_timeout(address, val,
1273                                  val & RCC_OCRDYR_HSIDIVRDY,
1274                                  TIMEOUT_200MS);
1275         if (ret)
1276                 pr_err("HSIDIV failed @ 0x%x: 0x%x\n",
1277                        address, readl(address));
1278
1279         return ret;
1280 }
1281
1282 static int stm32mp1_hsidiv(fdt_addr_t rcc, ulong hsifreq)
1283 {
1284         u8 hsidiv;
1285         u32 hsidivfreq = MAX_HSI_HZ;
1286
1287         for (hsidiv = 0; hsidiv < 4; hsidiv++,
1288              hsidivfreq = hsidivfreq / 2)
1289                 if (hsidivfreq == hsifreq)
1290                         break;
1291
1292         if (hsidiv == 4) {
1293                 pr_err("clk-hsi frequency invalid");
1294                 return -1;
1295         }
1296
1297         if (hsidiv > 0)
1298                 return stm32mp1_set_hsidiv(rcc, hsidiv);
1299
1300         return 0;
1301 }
1302
1303 static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id)
1304 {
1305         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1306
1307         writel(RCC_PLLNCR_PLLON, priv->base + pll[pll_id].pllxcr);
1308 }
1309
1310 static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output)
1311 {
1312         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1313         u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1314         u32 val;
1315         int ret;
1316
1317         ret = readl_poll_timeout(pllxcr, val, val & RCC_PLLNCR_PLLRDY,
1318                                  TIMEOUT_200MS);
1319
1320         if (ret) {
1321                 pr_err("PLL%d start failed @ 0x%x: 0x%x\n",
1322                        pll_id, pllxcr, readl(pllxcr));
1323                 return ret;
1324         }
1325
1326         /* start the requested output */
1327         setbits_le32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT);
1328
1329         return 0;
1330 }
1331
1332 static int pll_stop(struct stm32mp1_clk_priv *priv, int pll_id)
1333 {
1334         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1335         u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1336         u32 val;
1337
1338         /* stop all output */
1339         clrbits_le32(pllxcr,
1340                      RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN);
1341
1342         /* stop PLL */
1343         clrbits_le32(pllxcr, RCC_PLLNCR_PLLON);
1344
1345         /* wait PLL stopped */
1346         return readl_poll_timeout(pllxcr, val, (val & RCC_PLLNCR_PLLRDY) == 0,
1347                                   TIMEOUT_200MS);
1348 }
1349
1350 static void pll_config_output(struct stm32mp1_clk_priv *priv,
1351                               int pll_id, u32 *pllcfg)
1352 {
1353         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1354         fdt_addr_t rcc = priv->base;
1355         u32 value;
1356
1357         value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT)
1358                 & RCC_PLLNCFGR2_DIVP_MASK;
1359         value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT)
1360                  & RCC_PLLNCFGR2_DIVQ_MASK;
1361         value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT)
1362                  & RCC_PLLNCFGR2_DIVR_MASK;
1363         writel(value, rcc + pll[pll_id].pllxcfgr2);
1364 }
1365
1366 static int pll_config(struct stm32mp1_clk_priv *priv, int pll_id,
1367                       u32 *pllcfg, u32 fracv)
1368 {
1369         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1370         fdt_addr_t rcc = priv->base;
1371         enum stm32mp1_plltype type = pll[pll_id].plltype;
1372         int src;
1373         ulong refclk;
1374         u8 ifrge = 0;
1375         u32 value;
1376
1377         src = readl(priv->base + pll[pll_id].rckxselr) & RCC_SELR_SRC_MASK;
1378
1379         refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]) /
1380                  (pllcfg[PLLCFG_M] + 1);
1381
1382         if (refclk < (stm32mp1_pll[type].refclk_min * 1000000) ||
1383             refclk > (stm32mp1_pll[type].refclk_max * 1000000)) {
1384                 debug("invalid refclk = %x\n", (u32)refclk);
1385                 return -EINVAL;
1386         }
1387         if (type == PLL_800 && refclk >= 8000000)
1388                 ifrge = 1;
1389
1390         value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT)
1391                  & RCC_PLLNCFGR1_DIVN_MASK;
1392         value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT)
1393                  & RCC_PLLNCFGR1_DIVM_MASK;
1394         value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT)
1395                  & RCC_PLLNCFGR1_IFRGE_MASK;
1396         writel(value, rcc + pll[pll_id].pllxcfgr1);
1397
1398         /* fractional configuration: load sigma-delta modulator (SDM) */
1399
1400         /* Write into FRACV the new fractional value , and FRACLE to 0 */
1401         writel(fracv << RCC_PLLNFRACR_FRACV_SHIFT,
1402                rcc + pll[pll_id].pllxfracr);
1403
1404         /* Write FRACLE to 1 : FRACV value is loaded into the SDM */
1405         setbits_le32(rcc + pll[pll_id].pllxfracr,
1406                      RCC_PLLNFRACR_FRACLE);
1407
1408         pll_config_output(priv, pll_id, pllcfg);
1409
1410         return 0;
1411 }
1412
1413 static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg)
1414 {
1415         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1416         u32 pllxcsg;
1417
1418         pllxcsg = ((csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) &
1419                     RCC_PLLNCSGR_MOD_PER_MASK) |
1420                   ((csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) &
1421                     RCC_PLLNCSGR_INC_STEP_MASK) |
1422                   ((csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) &
1423                     RCC_PLLNCSGR_SSCG_MODE_MASK);
1424
1425         writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr);
1426 }
1427
1428 static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc)
1429 {
1430         u32 address = priv->base + (clksrc >> 4);
1431         u32 val;
1432         int ret;
1433
1434         clrsetbits_le32(address, RCC_SELR_SRC_MASK, clksrc & RCC_SELR_SRC_MASK);
1435         ret = readl_poll_timeout(address, val, val & RCC_SELR_SRCRDY,
1436                                  TIMEOUT_200MS);
1437         if (ret)
1438                 pr_err("CLKSRC %x start failed @ 0x%x: 0x%x\n",
1439                        clksrc, address, readl(address));
1440
1441         return ret;
1442 }
1443
1444 static void stgen_config(struct stm32mp1_clk_priv *priv)
1445 {
1446         int p;
1447         u32 stgenc, cntfid0;
1448         ulong rate;
1449
1450         stgenc = (u32)syscon_get_first_range(STM32MP_SYSCON_STGEN);
1451
1452         cntfid0 = readl(stgenc + STGENC_CNTFID0);
1453         p = stm32mp1_clk_get_parent(priv, STGEN_K);
1454         rate = stm32mp1_clk_get(priv, p);
1455
1456         if (cntfid0 != rate) {
1457                 pr_debug("System Generic Counter (STGEN) update\n");
1458                 clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1459                 writel(0x0, stgenc + STGENC_CNTCVL);
1460                 writel(0x0, stgenc + STGENC_CNTCVU);
1461                 writel(rate, stgenc + STGENC_CNTFID0);
1462                 setbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1463
1464                 __asm__ volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (rate));
1465
1466                 /* need to update gd->arch.timer_rate_hz with new frequency */
1467                 timer_init();
1468                 pr_debug("gd->arch.timer_rate_hz = %x\n",
1469                          (u32)gd->arch.timer_rate_hz);
1470                 pr_debug("Tick = %x\n", (u32)(get_ticks()));
1471         }
1472 }
1473
1474 static int set_clkdiv(unsigned int clkdiv, u32 address)
1475 {
1476         u32 val;
1477         int ret;
1478
1479         clrsetbits_le32(address, RCC_DIVR_DIV_MASK, clkdiv & RCC_DIVR_DIV_MASK);
1480         ret = readl_poll_timeout(address, val, val & RCC_DIVR_DIVRDY,
1481                                  TIMEOUT_200MS);
1482         if (ret)
1483                 pr_err("CLKDIV %x start failed @ 0x%x: 0x%x\n",
1484                        clkdiv, address, readl(address));
1485
1486         return ret;
1487 }
1488
1489 static void stm32mp1_mco_csg(struct stm32mp1_clk_priv *priv,
1490                              u32 clksrc, u32 clkdiv)
1491 {
1492         u32 address = priv->base + (clksrc >> 4);
1493
1494         /*
1495          * binding clksrc : bit15-4 offset
1496          *                  bit3:   disable
1497          *                  bit2-0: MCOSEL[2:0]
1498          */
1499         if (clksrc & 0x8) {
1500                 clrbits_le32(address, RCC_MCOCFG_MCOON);
1501         } else {
1502                 clrsetbits_le32(address,
1503                                 RCC_MCOCFG_MCOSRC_MASK,
1504                                 clksrc & RCC_MCOCFG_MCOSRC_MASK);
1505                 clrsetbits_le32(address,
1506                                 RCC_MCOCFG_MCODIV_MASK,
1507                                 clkdiv << RCC_MCOCFG_MCODIV_SHIFT);
1508                 setbits_le32(address, RCC_MCOCFG_MCOON);
1509         }
1510 }
1511
1512 static void set_rtcsrc(struct stm32mp1_clk_priv *priv,
1513                        unsigned int clksrc,
1514                        int lse_css)
1515 {
1516         u32 address = priv->base + RCC_BDCR;
1517
1518         if (readl(address) & RCC_BDCR_RTCCKEN)
1519                 goto skip_rtc;
1520
1521         if (clksrc == CLK_RTC_DISABLED)
1522                 goto skip_rtc;
1523
1524         clrsetbits_le32(address,
1525                         RCC_BDCR_RTCSRC_MASK,
1526                         clksrc << RCC_BDCR_RTCSRC_SHIFT);
1527
1528         setbits_le32(address, RCC_BDCR_RTCCKEN);
1529
1530 skip_rtc:
1531         if (lse_css)
1532                 setbits_le32(address, RCC_BDCR_LSECSSON);
1533 }
1534
1535 static void pkcs_config(struct stm32mp1_clk_priv *priv, u32 pkcs)
1536 {
1537         u32 address = priv->base + ((pkcs >> 4) & 0xFFF);
1538         u32 value = pkcs & 0xF;
1539         u32 mask = 0xF;
1540
1541         if (pkcs & BIT(31)) {
1542                 mask <<= 4;
1543                 value <<= 4;
1544         }
1545         clrsetbits_le32(address, mask, value);
1546 }
1547
1548 static int stm32mp1_clktree(struct udevice *dev)
1549 {
1550         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1551         fdt_addr_t rcc = priv->base;
1552         unsigned int clksrc[CLKSRC_NB];
1553         unsigned int clkdiv[CLKDIV_NB];
1554         unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
1555         ofnode plloff[_PLL_NB];
1556         int ret;
1557         int i, len;
1558         int lse_css = 0;
1559         const u32 *pkcs_cell;
1560
1561         /* check mandatory field */
1562         ret = dev_read_u32_array(dev, "st,clksrc", clksrc, CLKSRC_NB);
1563         if (ret < 0) {
1564                 debug("field st,clksrc invalid: error %d\n", ret);
1565                 return -FDT_ERR_NOTFOUND;
1566         }
1567
1568         ret = dev_read_u32_array(dev, "st,clkdiv", clkdiv, CLKDIV_NB);
1569         if (ret < 0) {
1570                 debug("field st,clkdiv invalid: error %d\n", ret);
1571                 return -FDT_ERR_NOTFOUND;
1572         }
1573
1574         /* check mandatory field in each pll */
1575         for (i = 0; i < _PLL_NB; i++) {
1576                 char name[12];
1577
1578                 sprintf(name, "st,pll@%d", i);
1579                 plloff[i] = dev_read_subnode(dev, name);
1580                 if (!ofnode_valid(plloff[i]))
1581                         continue;
1582                 ret = ofnode_read_u32_array(plloff[i], "cfg",
1583                                             pllcfg[i], PLLCFG_NB);
1584                 if (ret < 0) {
1585                         debug("field cfg invalid: error %d\n", ret);
1586                         return -FDT_ERR_NOTFOUND;
1587                 }
1588         }
1589
1590         debug("configuration MCO\n");
1591         stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]);
1592         stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]);
1593
1594         debug("switch ON osillator\n");
1595         /*
1596          * switch ON oscillator found in device-tree,
1597          * HSI already ON after bootrom
1598          */
1599         if (priv->osc[_LSI])
1600                 stm32mp1_lsi_set(rcc, 1);
1601
1602         if (priv->osc[_LSE]) {
1603                 int bypass;
1604                 int lsedrv;
1605                 struct udevice *dev = priv->osc_dev[_LSE];
1606
1607                 bypass = dev_read_bool(dev, "st,bypass");
1608                 lse_css = dev_read_bool(dev, "st,css");
1609                 lsedrv = dev_read_u32_default(dev, "st,drive",
1610                                               LSEDRV_MEDIUM_HIGH);
1611
1612                 stm32mp1_lse_enable(rcc, bypass, lsedrv);
1613         }
1614
1615         if (priv->osc[_HSE]) {
1616                 int bypass, css;
1617                 struct udevice *dev = priv->osc_dev[_HSE];
1618
1619                 bypass = dev_read_bool(dev, "st,bypass");
1620                 css = dev_read_bool(dev, "st,css");
1621
1622                 stm32mp1_hse_enable(rcc, bypass, css);
1623         }
1624         /* CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR)
1625          * => switch on CSI even if node is not present in device tree
1626          */
1627         stm32mp1_csi_set(rcc, 1);
1628
1629         /* come back to HSI */
1630         debug("come back to HSI\n");
1631         set_clksrc(priv, CLK_MPU_HSI);
1632         set_clksrc(priv, CLK_AXI_HSI);
1633         set_clksrc(priv, CLK_MCU_HSI);
1634
1635         debug("pll stop\n");
1636         for (i = 0; i < _PLL_NB; i++)
1637                 pll_stop(priv, i);
1638
1639         /* configure HSIDIV */
1640         debug("configure HSIDIV\n");
1641         if (priv->osc[_HSI]) {
1642                 stm32mp1_hsidiv(rcc, priv->osc[_HSI]);
1643                 stgen_config(priv);
1644         }
1645
1646         /* select DIV */
1647         debug("select DIV\n");
1648         /* no ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */
1649         writel(clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK, rcc + RCC_MPCKDIVR);
1650         set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR);
1651         set_clkdiv(clkdiv[CLKDIV_APB4], rcc + RCC_APB4DIVR);
1652         set_clkdiv(clkdiv[CLKDIV_APB5], rcc + RCC_APB5DIVR);
1653         set_clkdiv(clkdiv[CLKDIV_MCU], rcc + RCC_MCUDIVR);
1654         set_clkdiv(clkdiv[CLKDIV_APB1], rcc + RCC_APB1DIVR);
1655         set_clkdiv(clkdiv[CLKDIV_APB2], rcc + RCC_APB2DIVR);
1656         set_clkdiv(clkdiv[CLKDIV_APB3], rcc + RCC_APB3DIVR);
1657
1658         /* no ready bit for RTC */
1659         writel(clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK, rcc + RCC_RTCDIVR);
1660
1661         /* configure PLLs source */
1662         debug("configure PLLs source\n");
1663         set_clksrc(priv, clksrc[CLKSRC_PLL12]);
1664         set_clksrc(priv, clksrc[CLKSRC_PLL3]);
1665         set_clksrc(priv, clksrc[CLKSRC_PLL4]);
1666
1667         /* configure and start PLLs */
1668         debug("configure PLLs\n");
1669         for (i = 0; i < _PLL_NB; i++) {
1670                 u32 fracv;
1671                 u32 csg[PLLCSG_NB];
1672
1673                 debug("configure PLL %d @ %d\n", i,
1674                       ofnode_to_offset(plloff[i]));
1675                 if (!ofnode_valid(plloff[i]))
1676                         continue;
1677
1678                 fracv = ofnode_read_u32_default(plloff[i], "frac", 0);
1679                 pll_config(priv, i, pllcfg[i], fracv);
1680                 ret = ofnode_read_u32_array(plloff[i], "csg", csg, PLLCSG_NB);
1681                 if (!ret) {
1682                         pll_csg(priv, i, csg);
1683                 } else if (ret != -FDT_ERR_NOTFOUND) {
1684                         debug("invalid csg node for pll@%d res=%d\n", i, ret);
1685                         return ret;
1686                 }
1687                 pll_start(priv, i);
1688         }
1689
1690         /* wait and start PLLs ouptut when ready */
1691         for (i = 0; i < _PLL_NB; i++) {
1692                 if (!ofnode_valid(plloff[i]))
1693                         continue;
1694                 debug("output PLL %d\n", i);
1695                 pll_output(priv, i, pllcfg[i][PLLCFG_O]);
1696         }
1697
1698         /* wait LSE ready before to use it */
1699         if (priv->osc[_LSE])
1700                 stm32mp1_lse_wait(rcc);
1701
1702         /* configure with expected clock source */
1703         debug("CLKSRC\n");
1704         set_clksrc(priv, clksrc[CLKSRC_MPU]);
1705         set_clksrc(priv, clksrc[CLKSRC_AXI]);
1706         set_clksrc(priv, clksrc[CLKSRC_MCU]);
1707         set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css);
1708
1709         /* configure PKCK */
1710         debug("PKCK\n");
1711         pkcs_cell = dev_read_prop(dev, "st,pkcs", &len);
1712         if (pkcs_cell) {
1713                 bool ckper_disabled = false;
1714
1715                 for (i = 0; i < len / sizeof(u32); i++) {
1716                         u32 pkcs = (u32)fdt32_to_cpu(pkcs_cell[i]);
1717
1718                         if (pkcs == CLK_CKPER_DISABLED) {
1719                                 ckper_disabled = true;
1720                                 continue;
1721                         }
1722                         pkcs_config(priv, pkcs);
1723                 }
1724                 /* CKPER is source for some peripheral clock
1725                  * (FMC-NAND / QPSI-NOR) and switching source is allowed
1726                  * only if previous clock is still ON
1727                  * => deactivated CKPER only after switching clock
1728                  */
1729                 if (ckper_disabled)
1730                         pkcs_config(priv, CLK_CKPER_DISABLED);
1731         }
1732
1733         /* STGEN clock source can change with CLK_STGEN_XXX */
1734         stgen_config(priv);
1735
1736         debug("oscillator off\n");
1737         /* switch OFF HSI if not found in device-tree */
1738         if (!priv->osc[_HSI])
1739                 stm32mp1_hsi_set(rcc, 0);
1740
1741         /* Software Self-Refresh mode (SSR) during DDR initilialization */
1742         clrsetbits_le32(priv->base + RCC_DDRITFCR,
1743                         RCC_DDRITFCR_DDRCKMOD_MASK,
1744                         RCC_DDRITFCR_DDRCKMOD_SSR <<
1745                         RCC_DDRITFCR_DDRCKMOD_SHIFT);
1746
1747         return 0;
1748 }
1749 #endif /* STM32MP1_CLOCK_TREE_INIT */
1750
1751 static int pll_set_output_rate(struct udevice *dev,
1752                                int pll_id,
1753                                int div_id,
1754                                unsigned long clk_rate)
1755 {
1756         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1757         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1758         u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1759         int div;
1760         ulong fvco;
1761
1762         if (div_id > _DIV_NB)
1763                 return -EINVAL;
1764
1765         fvco = pll_get_fvco(priv, pll_id);
1766
1767         if (fvco <= clk_rate)
1768                 div = 1;
1769         else
1770                 div = DIV_ROUND_UP(fvco, clk_rate);
1771
1772         if (div > 128)
1773                 div = 128;
1774
1775         debug("fvco = %ld, clk_rate = %ld, div=%d\n", fvco, clk_rate, div);
1776         /* stop the requested output */
1777         clrbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
1778         /* change divider */
1779         clrsetbits_le32(priv->base + pll[pll_id].pllxcfgr2,
1780                         RCC_PLLNCFGR2_DIVX_MASK << RCC_PLLNCFGR2_SHIFT(div_id),
1781                         (div - 1) << RCC_PLLNCFGR2_SHIFT(div_id));
1782         /* start the requested output */
1783         setbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
1784
1785         return 0;
1786 }
1787
1788 static ulong stm32mp1_clk_set_rate(struct clk *clk, unsigned long clk_rate)
1789 {
1790         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1791         int p;
1792
1793         switch (clk->id) {
1794         case LTDC_PX:
1795         case DSI_PX:
1796                 break;
1797         default:
1798                 pr_err("not supported");
1799                 return -EINVAL;
1800         }
1801
1802         p = stm32mp1_clk_get_parent(priv, clk->id);
1803         if (p < 0)
1804                 return -EINVAL;
1805
1806         switch (p) {
1807         case _PLL4_Q:
1808                 /* for LTDC_PX and DSI_PX case */
1809                 return pll_set_output_rate(clk->dev, _PLL4, _DIV_Q, clk_rate);
1810         }
1811
1812         return -EINVAL;
1813 }
1814
1815 static void stm32mp1_osc_clk_init(const char *name,
1816                                   struct stm32mp1_clk_priv *priv,
1817                                   int index)
1818 {
1819         struct clk clk;
1820         struct udevice *dev = NULL;
1821
1822         priv->osc[index] = 0;
1823         clk.id = 0;
1824         if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) {
1825                 if (clk_request(dev, &clk))
1826                         pr_err("%s request", name);
1827                 else
1828                         priv->osc[index] = clk_get_rate(&clk);
1829         }
1830         priv->osc_dev[index] = dev;
1831 }
1832
1833 static void stm32mp1_osc_init(struct udevice *dev)
1834 {
1835         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1836         int i;
1837         const char *name[NB_OSC] = {
1838                 [_LSI] = "clk-lsi",
1839                 [_LSE] = "clk-lse",
1840                 [_HSI] = "clk-hsi",
1841                 [_HSE] = "clk-hse",
1842                 [_CSI] = "clk-csi",
1843                 [_I2S_CKIN] = "i2s_ckin",
1844                 [_USB_PHY_48] = "ck_usbo_48m"};
1845
1846         for (i = 0; i < NB_OSC; i++) {
1847                 stm32mp1_osc_clk_init(name[i], priv, i);
1848                 debug("%d: %s => %x\n", i, name[i], (u32)priv->osc[i]);
1849         }
1850 }
1851
1852 static int stm32mp1_clk_probe(struct udevice *dev)
1853 {
1854         int result = 0;
1855         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1856
1857         priv->base = dev_read_addr(dev->parent);
1858         if (priv->base == FDT_ADDR_T_NONE)
1859                 return -EINVAL;
1860
1861         priv->data = (void *)&stm32mp1_data;
1862
1863         if (!priv->data->gate || !priv->data->sel ||
1864             !priv->data->pll)
1865                 return -EINVAL;
1866
1867         stm32mp1_osc_init(dev);
1868
1869 #ifdef STM32MP1_CLOCK_TREE_INIT
1870         /* clock tree init is done only one time, before relocation */
1871         if (!(gd->flags & GD_FLG_RELOC))
1872                 result = stm32mp1_clktree(dev);
1873 #endif
1874
1875         return result;
1876 }
1877
1878 static const struct clk_ops stm32mp1_clk_ops = {
1879         .enable = stm32mp1_clk_enable,
1880         .disable = stm32mp1_clk_disable,
1881         .get_rate = stm32mp1_clk_get_rate,
1882         .set_rate = stm32mp1_clk_set_rate,
1883 };
1884
1885 U_BOOT_DRIVER(stm32mp1_clock) = {
1886         .name = "stm32mp1_clk",
1887         .id = UCLASS_CLK,
1888         .ops = &stm32mp1_clk_ops,
1889         .priv_auto_alloc_size = sizeof(struct stm32mp1_clk_priv),
1890         .probe = stm32mp1_clk_probe,
1891 };