1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
7 #include <clk-uclass.h>
14 #include <linux/iopoll.h>
15 #include <dt-bindings/clock/stm32mp1-clks.h>
16 #include <dt-bindings/clock/stm32mp1-clksrc.h>
18 DECLARE_GLOBAL_DATA_PTR;
20 #ifndef CONFIG_STM32MP1_TRUSTED
21 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
22 /* activate clock tree initialization in the driver */
23 #define STM32MP1_CLOCK_TREE_INIT
27 #define MAX_HSI_HZ 64000000
30 #define TIMEOUT_200MS 200000
31 #define TIMEOUT_1S 1000000
34 #define STGENC_CNTCR 0x00
35 #define STGENC_CNTSR 0x04
36 #define STGENC_CNTCVL 0x08
37 #define STGENC_CNTCVU 0x0C
38 #define STGENC_CNTFID0 0x20
40 #define STGENC_CNTCR_EN BIT(0)
43 #define RCC_OCENSETR 0x0C
44 #define RCC_OCENCLRR 0x10
45 #define RCC_HSICFGR 0x18
46 #define RCC_MPCKSELR 0x20
47 #define RCC_ASSCKSELR 0x24
48 #define RCC_RCK12SELR 0x28
49 #define RCC_MPCKDIVR 0x2C
50 #define RCC_AXIDIVR 0x30
51 #define RCC_APB4DIVR 0x3C
52 #define RCC_APB5DIVR 0x40
53 #define RCC_RTCDIVR 0x44
54 #define RCC_MSSCKSELR 0x48
55 #define RCC_PLL1CR 0x80
56 #define RCC_PLL1CFGR1 0x84
57 #define RCC_PLL1CFGR2 0x88
58 #define RCC_PLL1FRACR 0x8C
59 #define RCC_PLL1CSGR 0x90
60 #define RCC_PLL2CR 0x94
61 #define RCC_PLL2CFGR1 0x98
62 #define RCC_PLL2CFGR2 0x9C
63 #define RCC_PLL2FRACR 0xA0
64 #define RCC_PLL2CSGR 0xA4
65 #define RCC_I2C46CKSELR 0xC0
66 #define RCC_CPERCKSELR 0xD0
67 #define RCC_STGENCKSELR 0xD4
68 #define RCC_DDRITFCR 0xD8
69 #define RCC_BDCR 0x140
70 #define RCC_RDLSICR 0x144
71 #define RCC_MP_APB4ENSETR 0x200
72 #define RCC_MP_APB5ENSETR 0x208
73 #define RCC_MP_AHB5ENSETR 0x210
74 #define RCC_MP_AHB6ENSETR 0x218
75 #define RCC_OCRDYR 0x808
76 #define RCC_DBGCFGR 0x80C
77 #define RCC_RCK3SELR 0x820
78 #define RCC_RCK4SELR 0x824
79 #define RCC_MCUDIVR 0x830
80 #define RCC_APB1DIVR 0x834
81 #define RCC_APB2DIVR 0x838
82 #define RCC_APB3DIVR 0x83C
83 #define RCC_PLL3CR 0x880
84 #define RCC_PLL3CFGR1 0x884
85 #define RCC_PLL3CFGR2 0x888
86 #define RCC_PLL3FRACR 0x88C
87 #define RCC_PLL3CSGR 0x890
88 #define RCC_PLL4CR 0x894
89 #define RCC_PLL4CFGR1 0x898
90 #define RCC_PLL4CFGR2 0x89C
91 #define RCC_PLL4FRACR 0x8A0
92 #define RCC_PLL4CSGR 0x8A4
93 #define RCC_I2C12CKSELR 0x8C0
94 #define RCC_I2C35CKSELR 0x8C4
95 #define RCC_SPI2S1CKSELR 0x8D8
96 #define RCC_UART6CKSELR 0x8E4
97 #define RCC_UART24CKSELR 0x8E8
98 #define RCC_UART35CKSELR 0x8EC
99 #define RCC_UART78CKSELR 0x8F0
100 #define RCC_SDMMC12CKSELR 0x8F4
101 #define RCC_SDMMC3CKSELR 0x8F8
102 #define RCC_ETHCKSELR 0x8FC
103 #define RCC_QSPICKSELR 0x900
104 #define RCC_FMCCKSELR 0x904
105 #define RCC_USBCKSELR 0x91C
106 #define RCC_DSICKSELR 0x924
107 #define RCC_ADCCKSELR 0x928
108 #define RCC_MP_APB1ENSETR 0xA00
109 #define RCC_MP_APB2ENSETR 0XA08
110 #define RCC_MP_APB3ENSETR 0xA10
111 #define RCC_MP_AHB2ENSETR 0xA18
112 #define RCC_MP_AHB3ENSETR 0xA20
113 #define RCC_MP_AHB4ENSETR 0xA28
115 /* used for most of SELR register */
116 #define RCC_SELR_SRC_MASK GENMASK(2, 0)
117 #define RCC_SELR_SRCRDY BIT(31)
119 /* Values of RCC_MPCKSELR register */
120 #define RCC_MPCKSELR_HSI 0
121 #define RCC_MPCKSELR_HSE 1
122 #define RCC_MPCKSELR_PLL 2
123 #define RCC_MPCKSELR_PLL_MPUDIV 3
125 /* Values of RCC_ASSCKSELR register */
126 #define RCC_ASSCKSELR_HSI 0
127 #define RCC_ASSCKSELR_HSE 1
128 #define RCC_ASSCKSELR_PLL 2
130 /* Values of RCC_MSSCKSELR register */
131 #define RCC_MSSCKSELR_HSI 0
132 #define RCC_MSSCKSELR_HSE 1
133 #define RCC_MSSCKSELR_CSI 2
134 #define RCC_MSSCKSELR_PLL 3
136 /* Values of RCC_CPERCKSELR register */
137 #define RCC_CPERCKSELR_HSI 0
138 #define RCC_CPERCKSELR_CSI 1
139 #define RCC_CPERCKSELR_HSE 2
141 /* used for most of DIVR register : max div for RTC */
142 #define RCC_DIVR_DIV_MASK GENMASK(5, 0)
143 #define RCC_DIVR_DIVRDY BIT(31)
145 /* Masks for specific DIVR registers */
146 #define RCC_APBXDIV_MASK GENMASK(2, 0)
147 #define RCC_MPUDIV_MASK GENMASK(2, 0)
148 #define RCC_AXIDIV_MASK GENMASK(2, 0)
149 #define RCC_MCUDIV_MASK GENMASK(3, 0)
151 /* offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
152 #define RCC_MP_ENCLRR_OFFSET 4
154 /* Fields of RCC_BDCR register */
155 #define RCC_BDCR_LSEON BIT(0)
156 #define RCC_BDCR_LSEBYP BIT(1)
157 #define RCC_BDCR_LSERDY BIT(2)
158 #define RCC_BDCR_DIGBYP BIT(3)
159 #define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4)
160 #define RCC_BDCR_LSEDRV_SHIFT 4
161 #define RCC_BDCR_LSECSSON BIT(8)
162 #define RCC_BDCR_RTCCKEN BIT(20)
163 #define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16)
164 #define RCC_BDCR_RTCSRC_SHIFT 16
166 /* Fields of RCC_RDLSICR register */
167 #define RCC_RDLSICR_LSION BIT(0)
168 #define RCC_RDLSICR_LSIRDY BIT(1)
170 /* used for ALL PLLNCR registers */
171 #define RCC_PLLNCR_PLLON BIT(0)
172 #define RCC_PLLNCR_PLLRDY BIT(1)
173 #define RCC_PLLNCR_SSCG_CTRL BIT(2)
174 #define RCC_PLLNCR_DIVPEN BIT(4)
175 #define RCC_PLLNCR_DIVQEN BIT(5)
176 #define RCC_PLLNCR_DIVREN BIT(6)
177 #define RCC_PLLNCR_DIVEN_SHIFT 4
179 /* used for ALL PLLNCFGR1 registers */
180 #define RCC_PLLNCFGR1_DIVM_SHIFT 16
181 #define RCC_PLLNCFGR1_DIVM_MASK GENMASK(21, 16)
182 #define RCC_PLLNCFGR1_DIVN_SHIFT 0
183 #define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0)
184 /* only for PLL3 and PLL4 */
185 #define RCC_PLLNCFGR1_IFRGE_SHIFT 24
186 #define RCC_PLLNCFGR1_IFRGE_MASK GENMASK(25, 24)
188 /* used for ALL PLLNCFGR2 registers , using stm32mp1_div_id */
189 #define RCC_PLLNCFGR2_SHIFT(div_id) ((div_id) * 8)
190 #define RCC_PLLNCFGR2_DIVX_MASK GENMASK(6, 0)
191 #define RCC_PLLNCFGR2_DIVP_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_P)
192 #define RCC_PLLNCFGR2_DIVP_MASK GENMASK(6, 0)
193 #define RCC_PLLNCFGR2_DIVQ_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_Q)
194 #define RCC_PLLNCFGR2_DIVQ_MASK GENMASK(14, 8)
195 #define RCC_PLLNCFGR2_DIVR_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_R)
196 #define RCC_PLLNCFGR2_DIVR_MASK GENMASK(22, 16)
198 /* used for ALL PLLNFRACR registers */
199 #define RCC_PLLNFRACR_FRACV_SHIFT 3
200 #define RCC_PLLNFRACR_FRACV_MASK GENMASK(15, 3)
201 #define RCC_PLLNFRACR_FRACLE BIT(16)
203 /* used for ALL PLLNCSGR registers */
204 #define RCC_PLLNCSGR_INC_STEP_SHIFT 16
205 #define RCC_PLLNCSGR_INC_STEP_MASK GENMASK(30, 16)
206 #define RCC_PLLNCSGR_MOD_PER_SHIFT 0
207 #define RCC_PLLNCSGR_MOD_PER_MASK GENMASK(12, 0)
208 #define RCC_PLLNCSGR_SSCG_MODE_SHIFT 15
209 #define RCC_PLLNCSGR_SSCG_MODE_MASK BIT(15)
211 /* used for RCC_OCENSETR and RCC_OCENCLRR registers */
212 #define RCC_OCENR_HSION BIT(0)
213 #define RCC_OCENR_CSION BIT(4)
214 #define RCC_OCENR_DIGBYP BIT(7)
215 #define RCC_OCENR_HSEON BIT(8)
216 #define RCC_OCENR_HSEBYP BIT(10)
217 #define RCC_OCENR_HSECSSON BIT(11)
219 /* Fields of RCC_OCRDYR register */
220 #define RCC_OCRDYR_HSIRDY BIT(0)
221 #define RCC_OCRDYR_HSIDIVRDY BIT(2)
222 #define RCC_OCRDYR_CSIRDY BIT(4)
223 #define RCC_OCRDYR_HSERDY BIT(8)
225 /* Fields of DDRITFCR register */
226 #define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20)
227 #define RCC_DDRITFCR_DDRCKMOD_SHIFT 20
228 #define RCC_DDRITFCR_DDRCKMOD_SSR 0
230 /* Fields of RCC_HSICFGR register */
231 #define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0)
233 /* used for MCO related operations */
234 #define RCC_MCOCFG_MCOON BIT(12)
235 #define RCC_MCOCFG_MCODIV_MASK GENMASK(7, 4)
236 #define RCC_MCOCFG_MCODIV_SHIFT 4
237 #define RCC_MCOCFG_MCOSRC_MASK GENMASK(2, 0)
239 enum stm32mp1_parent_id {
241 * _HSI, _HSE, _CSI, _LSI, _LSE should not be moved
242 * they are used as index in osc[] as entry point
252 /* other parent source */
286 enum stm32mp1_parent_sel {
310 enum stm32mp1_pll_id {
318 enum stm32mp1_div_id {
325 enum stm32mp1_clksrc_id {
338 enum stm32mp1_clkdiv_id {
353 enum stm32mp1_pllcfg {
363 enum stm32mp1_pllcsg {
370 enum stm32mp1_plltype {
376 struct stm32mp1_pll {
382 struct stm32mp1_clk_gate {
391 struct stm32mp1_clk_sel {
399 #define REFCLK_SIZE 4
400 struct stm32mp1_clk_pll {
401 enum stm32mp1_plltype plltype;
408 u8 refclk[REFCLK_SIZE];
411 struct stm32mp1_clk_data {
412 const struct stm32mp1_clk_gate *gate;
413 const struct stm32mp1_clk_sel *sel;
414 const struct stm32mp1_clk_pll *pll;
418 struct stm32mp1_clk_priv {
420 const struct stm32mp1_clk_data *data;
422 struct udevice *osc_dev[NB_OSC];
425 #define STM32MP1_CLK(off, b, idx, s) \
432 .fixed = _UNKNOWN_ID, \
435 #define STM32MP1_CLK_F(off, b, idx, f) \
441 .sel = _UNKNOWN_SEL, \
445 #define STM32MP1_CLK_SET_CLR(off, b, idx, s) \
452 .fixed = _UNKNOWN_ID, \
455 #define STM32MP1_CLK_SET_CLR_F(off, b, idx, f) \
461 .sel = _UNKNOWN_SEL, \
465 #define STM32MP1_CLK_PARENT(idx, off, s, m, p) \
471 .nb_parent = ARRAY_SIZE((p)) \
474 #define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, off4, off5, off6,\
478 .rckxselr = (off1), \
479 .pllxcfgr1 = (off2), \
480 .pllxcfgr2 = (off3), \
481 .pllxfracr = (off4), \
483 .pllxcsgr = (off6), \
490 static const u8 stm32mp1_clks[][2] = {
500 {CK_HSE_DIV2, _HSE_KER_DIV2},
503 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
504 STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL),
505 STM32MP1_CLK(RCC_DDRITFCR, 1, DDRC1LP, _UNKNOWN_SEL),
506 STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL),
507 STM32MP1_CLK(RCC_DDRITFCR, 3, DDRC2LP, _UNKNOWN_SEL),
508 STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
509 STM32MP1_CLK(RCC_DDRITFCR, 5, DDRPHYCLP, _UNKNOWN_SEL),
510 STM32MP1_CLK(RCC_DDRITFCR, 6, DDRCAPB, _UNKNOWN_SEL),
511 STM32MP1_CLK(RCC_DDRITFCR, 7, DDRCAPBLP, _UNKNOWN_SEL),
512 STM32MP1_CLK(RCC_DDRITFCR, 8, AXIDCG, _UNKNOWN_SEL),
513 STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL),
514 STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL),
516 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
517 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
518 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
519 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL),
520 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL),
521 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL),
522 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL),
523 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL),
524 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL),
525 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
527 STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 8, SPI1_K, _SPI1_SEL),
528 STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
530 STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3),
532 STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 0, LTDC_PX, _PLL4_Q),
533 STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 4, DSI_PX, _PLL4_Q),
534 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 4, DSI_K, _DSI_SEL),
535 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
536 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
537 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
539 STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
540 STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5),
541 STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
543 STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB2ENSETR, 5, ADC12, _HCLK2),
544 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 5, ADC12_K, _ADC12_SEL),
545 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
546 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
548 STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 11, HSEM, _UNKNOWN_SEL),
549 STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 12, IPCC, _UNKNOWN_SEL),
551 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
552 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
553 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
554 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL),
555 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL),
556 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL),
557 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL),
558 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL),
559 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL),
560 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL),
561 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
563 STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
565 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK_K, _ETH_SEL),
566 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL),
567 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL),
568 STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK),
569 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
570 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
571 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL),
572 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL),
573 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL),
575 STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
577 STM32MP1_CLK(RCC_BDCR, 20, RTC, _RTC_SEL),
580 static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
581 static const u8 i2c35_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
582 static const u8 i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER};
583 static const u8 uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
585 static const u8 uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
587 static const u8 uart35_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
589 static const u8 uart78_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
591 static const u8 sdmmc12_parents[] = {_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER};
592 static const u8 sdmmc3_parents[] = {_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER};
593 static const u8 eth_parents[] = {_PLL4_P, _PLL3_Q};
594 static const u8 qspi_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
595 static const u8 fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
596 static const u8 usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2};
597 static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48};
598 static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER};
599 static const u8 dsi_parents[] = {_DSI_PHY, _PLL4_P};
600 static const u8 adc_parents[] = {_PLL4_R, _CK_PER, _PLL3_Q};
601 static const u8 spi_parents[] = {_PLL4_P, _PLL3_Q, _I2S_CKIN, _CK_PER,
603 static const u8 rtc_parents[] = {_UNKNOWN_ID, _LSE, _LSI, _HSE};
605 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
606 STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents),
607 STM32MP1_CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents),
608 STM32MP1_CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents),
609 STM32MP1_CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents),
610 STM32MP1_CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7,
612 STM32MP1_CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7,
614 STM32MP1_CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7,
616 STM32MP1_CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7,
618 STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7,
620 STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents),
621 STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents),
622 STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents),
623 STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents),
624 STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
625 STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
626 STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents),
627 STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x1, adc_parents),
628 STM32MP1_CLK_PARENT(_SPI1_SEL, RCC_SPI2S1CKSELR, 0, 0x7, spi_parents),
629 STM32MP1_CLK_PARENT(_RTC_SEL, RCC_BDCR, RCC_BDCR_RTCSRC_SHIFT,
630 (RCC_BDCR_RTCSRC_MASK >> RCC_BDCR_RTCSRC_SHIFT),
634 #ifdef STM32MP1_CLOCK_TREE_INIT
635 /* define characteristic of PLL according type */
637 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
649 #endif /* STM32MP1_CLOCK_TREE_INIT */
651 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = {
652 STM32MP1_CLK_PLL(_PLL1, PLL_1600,
653 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2,
654 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR,
655 _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
656 STM32MP1_CLK_PLL(_PLL2, PLL_1600,
657 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2,
658 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR,
659 _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
660 STM32MP1_CLK_PLL(_PLL3, PLL_800,
661 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2,
662 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR,
663 _HSI, _HSE, _CSI, _UNKNOWN_ID),
664 STM32MP1_CLK_PLL(_PLL4, PLL_800,
665 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2,
666 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR,
667 _HSI, _HSE, _CSI, _I2S_CKIN),
670 /* Prescaler table lookups for clock computation */
671 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */
672 static const u8 stm32mp1_mcu_div[16] = {
673 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9
676 /* div = /1 /2 /4 /8 /16 : same divider for pmu and apbx*/
677 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div
678 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div
679 static const u8 stm32mp1_mpu_apbx_div[8] = {
680 0, 1, 2, 3, 4, 4, 4, 4
683 /* div = /1 /2 /3 /4 */
684 static const u8 stm32mp1_axi_div[8] = {
685 1, 2, 3, 4, 4, 4, 4, 4
688 static const __maybe_unused
689 char * const stm32mp1_clk_parent_name[_PARENT_NB] = {
695 [_I2S_CKIN] = "I2S_CKIN",
696 [_HSI_KER] = "HSI_KER",
697 [_HSE_KER] = "HSE_KER",
698 [_HSE_KER_DIV2] = "HSE_KER_DIV2",
699 [_CSI_KER] = "CSI_KER",
700 [_PLL1_P] = "PLL1_P",
701 [_PLL1_Q] = "PLL1_Q",
702 [_PLL1_R] = "PLL1_R",
703 [_PLL2_P] = "PLL2_P",
704 [_PLL2_Q] = "PLL2_Q",
705 [_PLL2_R] = "PLL2_R",
706 [_PLL3_P] = "PLL3_P",
707 [_PLL3_Q] = "PLL3_Q",
708 [_PLL3_R] = "PLL3_R",
709 [_PLL4_P] = "PLL4_P",
710 [_PLL4_Q] = "PLL4_Q",
711 [_PLL4_R] = "PLL4_R",
720 [_CK_PER] = "CK_PER",
721 [_CK_MPU] = "CK_MPU",
722 [_CK_MCU] = "CK_MCU",
723 [_USB_PHY_48] = "USB_PHY_48",
724 [_DSI_PHY] = "DSI_PHY_PLL",
727 static const __maybe_unused
728 char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
729 [_I2C12_SEL] = "I2C12",
730 [_I2C35_SEL] = "I2C35",
731 [_I2C46_SEL] = "I2C46",
732 [_UART6_SEL] = "UART6",
733 [_UART24_SEL] = "UART24",
734 [_UART35_SEL] = "UART35",
735 [_UART78_SEL] = "UART78",
736 [_SDMMC12_SEL] = "SDMMC12",
737 [_SDMMC3_SEL] = "SDMMC3",
739 [_QSPI_SEL] = "QSPI",
741 [_USBPHY_SEL] = "USBPHY",
742 [_USBO_SEL] = "USBO",
743 [_STGEN_SEL] = "STGEN",
745 [_ADC12_SEL] = "ADC12",
746 [_SPI1_SEL] = "SPI1",
750 static const struct stm32mp1_clk_data stm32mp1_data = {
751 .gate = stm32mp1_clk_gate,
752 .sel = stm32mp1_clk_sel,
753 .pll = stm32mp1_clk_pll,
754 .nb_gate = ARRAY_SIZE(stm32mp1_clk_gate),
757 static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx)
760 debug("%s: clk id %d not found\n", __func__, idx);
764 return priv->osc[idx];
767 static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id)
769 const struct stm32mp1_clk_gate *gate = priv->data->gate;
770 int i, nb_clks = priv->data->nb_gate;
772 for (i = 0; i < nb_clks; i++) {
773 if (gate[i].index == id)
778 printf("%s: clk id %d not found\n", __func__, (u32)id);
785 static int stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv,
788 const struct stm32mp1_clk_gate *gate = priv->data->gate;
790 if (gate[i].sel > _PARENT_SEL_NB) {
791 printf("%s: parents for clk id %d not found\n",
799 static int stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv *priv,
802 const struct stm32mp1_clk_gate *gate = priv->data->gate;
804 if (gate[i].fixed == _UNKNOWN_ID)
807 return gate[i].fixed;
810 static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv,
813 const struct stm32mp1_clk_sel *sel = priv->data->sel;
818 for (idx = 0; idx < ARRAY_SIZE(stm32mp1_clks); idx++)
819 if (stm32mp1_clks[idx][0] == id)
820 return stm32mp1_clks[idx][1];
822 i = stm32mp1_clk_get_id(priv, id);
826 p = stm32mp1_clk_get_fixed_parent(priv, i);
827 if (p >= 0 && p < _PARENT_NB)
830 s = stm32mp1_clk_get_sel(priv, i);
834 p = (readl(priv->base + sel[s].offset) >> sel[s].src) & sel[s].msk;
836 if (p < sel[s].nb_parent) {
838 debug("%s: %s clock is the parent %s of clk id %d\n", __func__,
839 stm32mp1_clk_parent_name[sel[s].parent[p]],
840 stm32mp1_clk_parent_sel_name[s],
843 return sel[s].parent[p];
846 pr_err("%s: no parents defined for clk id %d\n",
852 static ulong pll_get_fref_ck(struct stm32mp1_clk_priv *priv,
855 const struct stm32mp1_clk_pll *pll = priv->data->pll;
860 /* Get current refclk */
861 selr = readl(priv->base + pll[pll_id].rckxselr);
862 src = selr & RCC_SELR_SRC_MASK;
864 refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]);
870 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL
871 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1)
872 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1)
873 * => in all the case Fpll_y_ck = pll_get_fvco() / (DIVy + 1)
875 static ulong pll_get_fvco(struct stm32mp1_clk_priv *priv,
878 const struct stm32mp1_clk_pll *pll = priv->data->pll;
883 cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1);
884 fracr = readl(priv->base + pll[pll_id].pllxfracr);
886 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
887 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
889 refclk = pll_get_fref_ck(priv, pll_id);
892 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1)
894 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1)
896 if (fracr & RCC_PLLNFRACR_FRACLE) {
897 u32 fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK)
898 >> RCC_PLLNFRACR_FRACV_SHIFT;
899 fvco = (ulong)lldiv((unsigned long long)refclk *
900 (((divn + 1) << 13) + fracv),
901 ((unsigned long long)(divm + 1)) << 13);
903 fvco = (ulong)(refclk * (divn + 1) / (divm + 1));
909 static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
910 int pll_id, int div_id)
912 const struct stm32mp1_clk_pll *pll = priv->data->pll;
917 if (div_id >= _DIV_NB)
920 cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2);
921 divy = (cfgr2 >> RCC_PLLNCFGR2_SHIFT(div_id)) & RCC_PLLNCFGR2_DIVX_MASK;
923 dfout = pll_get_fvco(priv, pll_id) / (divy + 1);
928 static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
936 reg = readl(priv->base + RCC_MPCKSELR);
937 switch (reg & RCC_SELR_SRC_MASK) {
938 case RCC_MPCKSELR_HSI:
939 clock = stm32mp1_clk_get_fixed(priv, _HSI);
941 case RCC_MPCKSELR_HSE:
942 clock = stm32mp1_clk_get_fixed(priv, _HSE);
944 case RCC_MPCKSELR_PLL:
945 case RCC_MPCKSELR_PLL_MPUDIV:
946 clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P);
947 if (p == RCC_MPCKSELR_PLL_MPUDIV) {
948 reg = readl(priv->base + RCC_MPCKDIVR);
949 clock /= stm32mp1_mpu_div[reg &
961 reg = readl(priv->base + RCC_ASSCKSELR);
962 switch (reg & RCC_SELR_SRC_MASK) {
963 case RCC_ASSCKSELR_HSI:
964 clock = stm32mp1_clk_get_fixed(priv, _HSI);
966 case RCC_ASSCKSELR_HSE:
967 clock = stm32mp1_clk_get_fixed(priv, _HSE);
969 case RCC_ASSCKSELR_PLL:
970 clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P);
974 /* System clock divider */
975 reg = readl(priv->base + RCC_AXIDIVR);
976 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK];
980 reg = readl(priv->base + RCC_APB4DIVR);
981 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
984 reg = readl(priv->base + RCC_APB5DIVR);
985 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
996 reg = readl(priv->base + RCC_MSSCKSELR);
997 switch (reg & RCC_SELR_SRC_MASK) {
998 case RCC_MSSCKSELR_HSI:
999 clock = stm32mp1_clk_get_fixed(priv, _HSI);
1001 case RCC_MSSCKSELR_HSE:
1002 clock = stm32mp1_clk_get_fixed(priv, _HSE);
1004 case RCC_MSSCKSELR_CSI:
1005 clock = stm32mp1_clk_get_fixed(priv, _CSI);
1007 case RCC_MSSCKSELR_PLL:
1008 clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_P);
1012 /* MCU clock divider */
1013 reg = readl(priv->base + RCC_MCUDIVR);
1014 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK];
1018 reg = readl(priv->base + RCC_APB1DIVR);
1019 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1022 reg = readl(priv->base + RCC_APB2DIVR);
1023 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1026 reg = readl(priv->base + RCC_APB3DIVR);
1027 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1035 reg = readl(priv->base + RCC_CPERCKSELR);
1036 switch (reg & RCC_SELR_SRC_MASK) {
1037 case RCC_CPERCKSELR_HSI:
1038 clock = stm32mp1_clk_get_fixed(priv, _HSI);
1040 case RCC_CPERCKSELR_HSE:
1041 clock = stm32mp1_clk_get_fixed(priv, _HSE);
1043 case RCC_CPERCKSELR_CSI:
1044 clock = stm32mp1_clk_get_fixed(priv, _CSI);
1050 clock = stm32mp1_clk_get_fixed(priv, _HSI);
1054 clock = stm32mp1_clk_get_fixed(priv, _CSI);
1059 clock = stm32mp1_clk_get_fixed(priv, _HSE);
1060 if (p == _HSE_KER_DIV2)
1064 clock = stm32mp1_clk_get_fixed(priv, _LSI);
1067 clock = stm32mp1_clk_get_fixed(priv, _LSE);
1073 clock = stm32mp1_read_pll_freq(priv, _PLL1, p - _PLL1_P);
1078 clock = stm32mp1_read_pll_freq(priv, _PLL2, p - _PLL2_P);
1083 clock = stm32mp1_read_pll_freq(priv, _PLL3, p - _PLL3_P);
1088 clock = stm32mp1_read_pll_freq(priv, _PLL4, p - _PLL4_P);
1097 struct udevice *dev = NULL;
1099 if (!uclass_get_device_by_name(UCLASS_CLK, "ck_dsi_phy",
1101 if (clk_request(dev, &clk)) {
1102 pr_err("ck_dsi_phy request");
1105 clock = clk_get_rate(&clk);
1114 debug("%s(%d) clock = %lx : %ld kHz\n",
1115 __func__, p, clock, clock / 1000);
1120 static int stm32mp1_clk_enable(struct clk *clk)
1122 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1123 const struct stm32mp1_clk_gate *gate = priv->data->gate;
1124 int i = stm32mp1_clk_get_id(priv, clk->id);
1129 if (gate[i].set_clr)
1130 writel(BIT(gate[i].bit), priv->base + gate[i].offset);
1132 setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1134 debug("%s: id clock %d has been enabled\n", __func__, (u32)clk->id);
1139 static int stm32mp1_clk_disable(struct clk *clk)
1141 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1142 const struct stm32mp1_clk_gate *gate = priv->data->gate;
1143 int i = stm32mp1_clk_get_id(priv, clk->id);
1148 if (gate[i].set_clr)
1149 writel(BIT(gate[i].bit),
1150 priv->base + gate[i].offset
1151 + RCC_MP_ENCLRR_OFFSET);
1153 clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1155 debug("%s: id clock %d has been disabled\n", __func__, (u32)clk->id);
1160 static ulong stm32mp1_clk_get_rate(struct clk *clk)
1162 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1163 int p = stm32mp1_clk_get_parent(priv, clk->id);
1169 rate = stm32mp1_clk_get(priv, p);
1172 debug("%s: computed rate for id clock %d is %d (parent is %s)\n",
1173 __func__, (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]);
1178 #ifdef STM32MP1_CLOCK_TREE_INIT
1179 static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset,
1182 u32 address = rcc + offset;
1185 setbits_le32(address, mask_on);
1187 clrbits_le32(address, mask_on);
1190 static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on)
1192 writel(mask_on, rcc + (enable ? RCC_OCENSETR : RCC_OCENCLRR));
1195 static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset,
1199 u32 address = rcc + offset;
1204 mask_test = mask_rdy;
1206 ret = readl_poll_timeout(address, val,
1207 (val & mask_rdy) == mask_test,
1211 pr_err("OSC %x @ %x timeout for enable=%d : 0x%x\n",
1212 mask_rdy, address, enable, readl(address));
1217 static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int digbyp,
1223 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_DIGBYP);
1225 if (bypass || digbyp)
1226 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP);
1229 * warning: not recommended to switch directly from "high drive"
1230 * to "medium low drive", and vice-versa.
1232 value = (readl(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK)
1233 >> RCC_BDCR_LSEDRV_SHIFT;
1235 while (value != lsedrv) {
1241 clrsetbits_le32(rcc + RCC_BDCR,
1242 RCC_BDCR_LSEDRV_MASK,
1243 value << RCC_BDCR_LSEDRV_SHIFT);
1246 stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON);
1249 static void stm32mp1_lse_wait(fdt_addr_t rcc)
1251 stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY);
1254 static void stm32mp1_lsi_set(fdt_addr_t rcc, int enable)
1256 stm32mp1_ls_osc_set(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSION);
1257 stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY);
1260 static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int digbyp, int css)
1263 writel(RCC_OCENR_DIGBYP, rcc + RCC_OCENSETR);
1264 if (bypass || digbyp)
1265 writel(RCC_OCENR_HSEBYP, rcc + RCC_OCENSETR);
1267 stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON);
1268 stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY);
1271 writel(RCC_OCENR_HSECSSON, rcc + RCC_OCENSETR);
1274 static void stm32mp1_csi_set(fdt_addr_t rcc, int enable)
1276 stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_CSION);
1277 stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY);
1280 static void stm32mp1_hsi_set(fdt_addr_t rcc, int enable)
1282 stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_HSION);
1283 stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_HSIRDY);
1286 static int stm32mp1_set_hsidiv(fdt_addr_t rcc, u8 hsidiv)
1288 u32 address = rcc + RCC_OCRDYR;
1292 clrsetbits_le32(rcc + RCC_HSICFGR,
1293 RCC_HSICFGR_HSIDIV_MASK,
1294 RCC_HSICFGR_HSIDIV_MASK & hsidiv);
1296 ret = readl_poll_timeout(address, val,
1297 val & RCC_OCRDYR_HSIDIVRDY,
1300 pr_err("HSIDIV failed @ 0x%x: 0x%x\n",
1301 address, readl(address));
1306 static int stm32mp1_hsidiv(fdt_addr_t rcc, ulong hsifreq)
1309 u32 hsidivfreq = MAX_HSI_HZ;
1311 for (hsidiv = 0; hsidiv < 4; hsidiv++,
1312 hsidivfreq = hsidivfreq / 2)
1313 if (hsidivfreq == hsifreq)
1317 pr_err("clk-hsi frequency invalid");
1322 return stm32mp1_set_hsidiv(rcc, hsidiv);
1327 static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id)
1329 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1331 clrsetbits_le32(priv->base + pll[pll_id].pllxcr,
1332 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN |
1337 static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output)
1339 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1340 u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1344 ret = readl_poll_timeout(pllxcr, val, val & RCC_PLLNCR_PLLRDY,
1348 pr_err("PLL%d start failed @ 0x%x: 0x%x\n",
1349 pll_id, pllxcr, readl(pllxcr));
1353 /* start the requested output */
1354 setbits_le32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT);
1359 static int pll_stop(struct stm32mp1_clk_priv *priv, int pll_id)
1361 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1362 u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1365 /* stop all output */
1366 clrbits_le32(pllxcr,
1367 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN);
1370 clrbits_le32(pllxcr, RCC_PLLNCR_PLLON);
1372 /* wait PLL stopped */
1373 return readl_poll_timeout(pllxcr, val, (val & RCC_PLLNCR_PLLRDY) == 0,
1377 static void pll_config_output(struct stm32mp1_clk_priv *priv,
1378 int pll_id, u32 *pllcfg)
1380 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1381 fdt_addr_t rcc = priv->base;
1384 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT)
1385 & RCC_PLLNCFGR2_DIVP_MASK;
1386 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT)
1387 & RCC_PLLNCFGR2_DIVQ_MASK;
1388 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT)
1389 & RCC_PLLNCFGR2_DIVR_MASK;
1390 writel(value, rcc + pll[pll_id].pllxcfgr2);
1393 static int pll_config(struct stm32mp1_clk_priv *priv, int pll_id,
1394 u32 *pllcfg, u32 fracv)
1396 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1397 fdt_addr_t rcc = priv->base;
1398 enum stm32mp1_plltype type = pll[pll_id].plltype;
1404 src = readl(priv->base + pll[pll_id].rckxselr) & RCC_SELR_SRC_MASK;
1406 refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]) /
1407 (pllcfg[PLLCFG_M] + 1);
1409 if (refclk < (stm32mp1_pll[type].refclk_min * 1000000) ||
1410 refclk > (stm32mp1_pll[type].refclk_max * 1000000)) {
1411 debug("invalid refclk = %x\n", (u32)refclk);
1414 if (type == PLL_800 && refclk >= 8000000)
1417 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT)
1418 & RCC_PLLNCFGR1_DIVN_MASK;
1419 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT)
1420 & RCC_PLLNCFGR1_DIVM_MASK;
1421 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT)
1422 & RCC_PLLNCFGR1_IFRGE_MASK;
1423 writel(value, rcc + pll[pll_id].pllxcfgr1);
1425 /* fractional configuration: load sigma-delta modulator (SDM) */
1427 /* Write into FRACV the new fractional value , and FRACLE to 0 */
1428 writel(fracv << RCC_PLLNFRACR_FRACV_SHIFT,
1429 rcc + pll[pll_id].pllxfracr);
1431 /* Write FRACLE to 1 : FRACV value is loaded into the SDM */
1432 setbits_le32(rcc + pll[pll_id].pllxfracr,
1433 RCC_PLLNFRACR_FRACLE);
1435 pll_config_output(priv, pll_id, pllcfg);
1440 static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg)
1442 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1445 pllxcsg = ((csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) &
1446 RCC_PLLNCSGR_MOD_PER_MASK) |
1447 ((csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) &
1448 RCC_PLLNCSGR_INC_STEP_MASK) |
1449 ((csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) &
1450 RCC_PLLNCSGR_SSCG_MODE_MASK);
1452 writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr);
1454 setbits_le32(priv->base + pll[pll_id].pllxcr, RCC_PLLNCR_SSCG_CTRL);
1457 static __maybe_unused int pll_set_rate(struct udevice *dev,
1460 unsigned long clk_rate)
1462 struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1463 unsigned int pllcfg[PLLCFG_NB];
1466 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1467 enum stm32mp1_plltype type = pll[pll_id].plltype;
1468 int divm, divn, divy;
1474 if (div_id > _DIV_NB)
1477 sprintf(name, "st,pll@%d", pll_id);
1478 plloff = dev_read_subnode(dev, name);
1479 if (!ofnode_valid(plloff))
1480 return -FDT_ERR_NOTFOUND;
1482 ret = ofnode_read_u32_array(plloff, "cfg",
1485 return -FDT_ERR_NOTFOUND;
1487 fck_ref = pll_get_fref_ck(priv, pll_id);
1489 divm = pllcfg[PLLCFG_M];
1490 /* select output divider = 0: for _DIV_P, 1:_DIV_Q 2:_DIV_R */
1491 divy = pllcfg[PLLCFG_P + div_id];
1493 /* For: PLL1 & PLL2 => VCO is * 2 but ck_pll_y is also / 2
1494 * So same final result than PLL2 et 4
1496 * Fck_pll_y = Fck_ref * ((DIVN + 1) + FRACV / 2^13)
1497 * / (DIVy + 1) * (DIVM + 1)
1498 * value = (DIVN + 1) * 2^13 + FRACV / 2^13
1499 * = Fck_pll_y (DIVy + 1) * (DIVM + 1) * 2^13 / Fck_ref
1501 value = ((u64)clk_rate * (divy + 1) * (divm + 1)) << 13;
1502 value = lldiv(value, fck_ref);
1504 divn = (value >> 13) - 1;
1505 if (divn < DIVN_MIN ||
1506 divn > stm32mp1_pll[type].divn_max) {
1507 pr_err("divn invalid = %d", divn);
1510 fracv = value - ((divn + 1) << 13);
1511 pllcfg[PLLCFG_N] = divn;
1513 /* reconfigure PLL */
1514 pll_stop(priv, pll_id);
1515 pll_config(priv, pll_id, pllcfg, fracv);
1516 pll_start(priv, pll_id);
1517 pll_output(priv, pll_id, pllcfg[PLLCFG_O]);
1522 static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc)
1524 u32 address = priv->base + (clksrc >> 4);
1528 clrsetbits_le32(address, RCC_SELR_SRC_MASK, clksrc & RCC_SELR_SRC_MASK);
1529 ret = readl_poll_timeout(address, val, val & RCC_SELR_SRCRDY,
1532 pr_err("CLKSRC %x start failed @ 0x%x: 0x%x\n",
1533 clksrc, address, readl(address));
1538 static void stgen_config(struct stm32mp1_clk_priv *priv)
1541 u32 stgenc, cntfid0;
1544 stgenc = STM32_STGEN_BASE;
1545 cntfid0 = readl(stgenc + STGENC_CNTFID0);
1546 p = stm32mp1_clk_get_parent(priv, STGEN_K);
1547 rate = stm32mp1_clk_get(priv, p);
1549 if (cntfid0 != rate) {
1552 pr_debug("System Generic Counter (STGEN) update\n");
1553 clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1554 counter = (u64)readl(stgenc + STGENC_CNTCVL);
1555 counter |= ((u64)(readl(stgenc + STGENC_CNTCVU))) << 32;
1556 counter = lldiv(counter * (u64)rate, cntfid0);
1557 writel((u32)counter, stgenc + STGENC_CNTCVL);
1558 writel((u32)(counter >> 32), stgenc + STGENC_CNTCVU);
1559 writel(rate, stgenc + STGENC_CNTFID0);
1560 setbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1562 __asm__ volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (rate));
1564 /* need to update gd->arch.timer_rate_hz with new frequency */
1569 static int set_clkdiv(unsigned int clkdiv, u32 address)
1574 clrsetbits_le32(address, RCC_DIVR_DIV_MASK, clkdiv & RCC_DIVR_DIV_MASK);
1575 ret = readl_poll_timeout(address, val, val & RCC_DIVR_DIVRDY,
1578 pr_err("CLKDIV %x start failed @ 0x%x: 0x%x\n",
1579 clkdiv, address, readl(address));
1584 static void stm32mp1_mco_csg(struct stm32mp1_clk_priv *priv,
1585 u32 clksrc, u32 clkdiv)
1587 u32 address = priv->base + (clksrc >> 4);
1590 * binding clksrc : bit15-4 offset
1592 * bit2-0: MCOSEL[2:0]
1595 clrbits_le32(address, RCC_MCOCFG_MCOON);
1597 clrsetbits_le32(address,
1598 RCC_MCOCFG_MCOSRC_MASK,
1599 clksrc & RCC_MCOCFG_MCOSRC_MASK);
1600 clrsetbits_le32(address,
1601 RCC_MCOCFG_MCODIV_MASK,
1602 clkdiv << RCC_MCOCFG_MCODIV_SHIFT);
1603 setbits_le32(address, RCC_MCOCFG_MCOON);
1607 static void set_rtcsrc(struct stm32mp1_clk_priv *priv,
1608 unsigned int clksrc,
1611 u32 address = priv->base + RCC_BDCR;
1613 if (readl(address) & RCC_BDCR_RTCCKEN)
1616 if (clksrc == CLK_RTC_DISABLED)
1619 clrsetbits_le32(address,
1620 RCC_BDCR_RTCSRC_MASK,
1621 clksrc << RCC_BDCR_RTCSRC_SHIFT);
1623 setbits_le32(address, RCC_BDCR_RTCCKEN);
1627 setbits_le32(address, RCC_BDCR_LSECSSON);
1630 static void pkcs_config(struct stm32mp1_clk_priv *priv, u32 pkcs)
1632 u32 address = priv->base + ((pkcs >> 4) & 0xFFF);
1633 u32 value = pkcs & 0xF;
1636 if (pkcs & BIT(31)) {
1640 clrsetbits_le32(address, mask, value);
1643 static int stm32mp1_clktree(struct udevice *dev)
1645 struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1646 fdt_addr_t rcc = priv->base;
1647 unsigned int clksrc[CLKSRC_NB];
1648 unsigned int clkdiv[CLKDIV_NB];
1649 unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
1650 ofnode plloff[_PLL_NB];
1654 const u32 *pkcs_cell;
1656 /* check mandatory field */
1657 ret = dev_read_u32_array(dev, "st,clksrc", clksrc, CLKSRC_NB);
1659 debug("field st,clksrc invalid: error %d\n", ret);
1660 return -FDT_ERR_NOTFOUND;
1663 ret = dev_read_u32_array(dev, "st,clkdiv", clkdiv, CLKDIV_NB);
1665 debug("field st,clkdiv invalid: error %d\n", ret);
1666 return -FDT_ERR_NOTFOUND;
1669 /* check mandatory field in each pll */
1670 for (i = 0; i < _PLL_NB; i++) {
1673 sprintf(name, "st,pll@%d", i);
1674 plloff[i] = dev_read_subnode(dev, name);
1675 if (!ofnode_valid(plloff[i]))
1677 ret = ofnode_read_u32_array(plloff[i], "cfg",
1678 pllcfg[i], PLLCFG_NB);
1680 debug("field cfg invalid: error %d\n", ret);
1681 return -FDT_ERR_NOTFOUND;
1685 debug("configuration MCO\n");
1686 stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]);
1687 stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]);
1689 debug("switch ON osillator\n");
1691 * switch ON oscillator found in device-tree,
1692 * HSI already ON after bootrom
1694 if (priv->osc[_LSI])
1695 stm32mp1_lsi_set(rcc, 1);
1697 if (priv->osc[_LSE]) {
1698 int bypass, digbyp, lsedrv;
1699 struct udevice *dev = priv->osc_dev[_LSE];
1701 bypass = dev_read_bool(dev, "st,bypass");
1702 digbyp = dev_read_bool(dev, "st,digbypass");
1703 lse_css = dev_read_bool(dev, "st,css");
1704 lsedrv = dev_read_u32_default(dev, "st,drive",
1705 LSEDRV_MEDIUM_HIGH);
1707 stm32mp1_lse_enable(rcc, bypass, digbyp, lsedrv);
1710 if (priv->osc[_HSE]) {
1711 int bypass, digbyp, css;
1712 struct udevice *dev = priv->osc_dev[_HSE];
1714 bypass = dev_read_bool(dev, "st,bypass");
1715 digbyp = dev_read_bool(dev, "st,digbypass");
1716 css = dev_read_bool(dev, "st,css");
1718 stm32mp1_hse_enable(rcc, bypass, digbyp, css);
1720 /* CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR)
1721 * => switch on CSI even if node is not present in device tree
1723 stm32mp1_csi_set(rcc, 1);
1725 /* come back to HSI */
1726 debug("come back to HSI\n");
1727 set_clksrc(priv, CLK_MPU_HSI);
1728 set_clksrc(priv, CLK_AXI_HSI);
1729 set_clksrc(priv, CLK_MCU_HSI);
1731 debug("pll stop\n");
1732 for (i = 0; i < _PLL_NB; i++)
1735 /* configure HSIDIV */
1736 debug("configure HSIDIV\n");
1737 if (priv->osc[_HSI]) {
1738 stm32mp1_hsidiv(rcc, priv->osc[_HSI]);
1743 debug("select DIV\n");
1744 /* no ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */
1745 writel(clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK, rcc + RCC_MPCKDIVR);
1746 set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR);
1747 set_clkdiv(clkdiv[CLKDIV_APB4], rcc + RCC_APB4DIVR);
1748 set_clkdiv(clkdiv[CLKDIV_APB5], rcc + RCC_APB5DIVR);
1749 set_clkdiv(clkdiv[CLKDIV_MCU], rcc + RCC_MCUDIVR);
1750 set_clkdiv(clkdiv[CLKDIV_APB1], rcc + RCC_APB1DIVR);
1751 set_clkdiv(clkdiv[CLKDIV_APB2], rcc + RCC_APB2DIVR);
1752 set_clkdiv(clkdiv[CLKDIV_APB3], rcc + RCC_APB3DIVR);
1754 /* no ready bit for RTC */
1755 writel(clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK, rcc + RCC_RTCDIVR);
1757 /* configure PLLs source */
1758 debug("configure PLLs source\n");
1759 set_clksrc(priv, clksrc[CLKSRC_PLL12]);
1760 set_clksrc(priv, clksrc[CLKSRC_PLL3]);
1761 set_clksrc(priv, clksrc[CLKSRC_PLL4]);
1763 /* configure and start PLLs */
1764 debug("configure PLLs\n");
1765 for (i = 0; i < _PLL_NB; i++) {
1769 debug("configure PLL %d @ %d\n", i,
1770 ofnode_to_offset(plloff[i]));
1771 if (!ofnode_valid(plloff[i]))
1774 fracv = ofnode_read_u32_default(plloff[i], "frac", 0);
1775 pll_config(priv, i, pllcfg[i], fracv);
1776 ret = ofnode_read_u32_array(plloff[i], "csg", csg, PLLCSG_NB);
1778 pll_csg(priv, i, csg);
1779 } else if (ret != -FDT_ERR_NOTFOUND) {
1780 debug("invalid csg node for pll@%d res=%d\n", i, ret);
1786 /* wait and start PLLs ouptut when ready */
1787 for (i = 0; i < _PLL_NB; i++) {
1788 if (!ofnode_valid(plloff[i]))
1790 debug("output PLL %d\n", i);
1791 pll_output(priv, i, pllcfg[i][PLLCFG_O]);
1794 /* wait LSE ready before to use it */
1795 if (priv->osc[_LSE])
1796 stm32mp1_lse_wait(rcc);
1798 /* configure with expected clock source */
1800 set_clksrc(priv, clksrc[CLKSRC_MPU]);
1801 set_clksrc(priv, clksrc[CLKSRC_AXI]);
1802 set_clksrc(priv, clksrc[CLKSRC_MCU]);
1803 set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css);
1805 /* configure PKCK */
1807 pkcs_cell = dev_read_prop(dev, "st,pkcs", &len);
1809 bool ckper_disabled = false;
1811 for (i = 0; i < len / sizeof(u32); i++) {
1812 u32 pkcs = (u32)fdt32_to_cpu(pkcs_cell[i]);
1814 if (pkcs == CLK_CKPER_DISABLED) {
1815 ckper_disabled = true;
1818 pkcs_config(priv, pkcs);
1820 /* CKPER is source for some peripheral clock
1821 * (FMC-NAND / QPSI-NOR) and switching source is allowed
1822 * only if previous clock is still ON
1823 * => deactivated CKPER only after switching clock
1826 pkcs_config(priv, CLK_CKPER_DISABLED);
1829 /* STGEN clock source can change with CLK_STGEN_XXX */
1832 debug("oscillator off\n");
1833 /* switch OFF HSI if not found in device-tree */
1834 if (!priv->osc[_HSI])
1835 stm32mp1_hsi_set(rcc, 0);
1837 /* Software Self-Refresh mode (SSR) during DDR initilialization */
1838 clrsetbits_le32(priv->base + RCC_DDRITFCR,
1839 RCC_DDRITFCR_DDRCKMOD_MASK,
1840 RCC_DDRITFCR_DDRCKMOD_SSR <<
1841 RCC_DDRITFCR_DDRCKMOD_SHIFT);
1845 #endif /* STM32MP1_CLOCK_TREE_INIT */
1847 static int pll_set_output_rate(struct udevice *dev,
1850 unsigned long clk_rate)
1852 struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1853 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1854 u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1858 if (div_id > _DIV_NB)
1861 fvco = pll_get_fvco(priv, pll_id);
1863 if (fvco <= clk_rate)
1866 div = DIV_ROUND_UP(fvco, clk_rate);
1871 /* stop the requested output */
1872 clrbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
1873 /* change divider */
1874 clrsetbits_le32(priv->base + pll[pll_id].pllxcfgr2,
1875 RCC_PLLNCFGR2_DIVX_MASK << RCC_PLLNCFGR2_SHIFT(div_id),
1876 (div - 1) << RCC_PLLNCFGR2_SHIFT(div_id));
1877 /* start the requested output */
1878 setbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
1883 static ulong stm32mp1_clk_set_rate(struct clk *clk, unsigned long clk_rate)
1885 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1889 #if defined(STM32MP1_CLOCK_TREE_INIT) && \
1890 defined(CONFIG_STM32MP1_DDR_INTERACTIVE)
1898 pr_err("not supported");
1902 p = stm32mp1_clk_get_parent(priv, clk->id);
1904 debug("%s: parent = %d:%s\n", __func__, p, stm32mp1_clk_parent_name[p]);
1910 #if defined(STM32MP1_CLOCK_TREE_INIT) && \
1911 defined(CONFIG_STM32MP1_DDR_INTERACTIVE)
1912 case _PLL2_R: /* DDRPHYC */
1914 /* only for change DDR clock in interactive mode */
1917 set_clksrc(priv, CLK_AXI_HSI);
1918 result = pll_set_rate(clk->dev, _PLL2, _DIV_R, clk_rate);
1919 set_clksrc(priv, CLK_AXI_PLL2P);
1925 /* for LTDC_PX and DSI_PX case */
1926 return pll_set_output_rate(clk->dev, _PLL4, _DIV_Q, clk_rate);
1932 static void stm32mp1_osc_clk_init(const char *name,
1933 struct stm32mp1_clk_priv *priv,
1937 struct udevice *dev = NULL;
1939 priv->osc[index] = 0;
1941 if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) {
1942 if (clk_request(dev, &clk))
1943 pr_err("%s request", name);
1945 priv->osc[index] = clk_get_rate(&clk);
1947 priv->osc_dev[index] = dev;
1950 static void stm32mp1_osc_init(struct udevice *dev)
1952 struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1954 const char *name[NB_OSC] = {
1960 [_I2S_CKIN] = "i2s_ckin",
1963 for (i = 0; i < NB_OSC; i++) {
1964 stm32mp1_osc_clk_init(name[i], priv, i);
1965 debug("%d: %s => %x\n", i, name[i], (u32)priv->osc[i]);
1969 static void __maybe_unused stm32mp1_clk_dump(struct stm32mp1_clk_priv *priv)
1974 printf("Clocks:\n");
1975 for (i = 0; i < _PARENT_NB; i++) {
1976 printf("- %s : %s MHz\n",
1977 stm32mp1_clk_parent_name[i],
1978 strmhz(buf, stm32mp1_clk_get(priv, i)));
1980 printf("Source Clocks:\n");
1981 for (i = 0; i < _PARENT_SEL_NB; i++) {
1982 p = (readl(priv->base + priv->data->sel[i].offset) >>
1983 priv->data->sel[i].src) & priv->data->sel[i].msk;
1984 if (p < priv->data->sel[i].nb_parent) {
1985 s = priv->data->sel[i].parent[p];
1986 printf("- %s(%d) => parent %s(%d)\n",
1987 stm32mp1_clk_parent_sel_name[i], i,
1988 stm32mp1_clk_parent_name[s], s);
1990 printf("- %s(%d) => parent index %d is invalid\n",
1991 stm32mp1_clk_parent_sel_name[i], i, p);
1996 #ifdef CONFIG_CMD_CLK
1997 int soc_clk_dump(void)
1999 struct udevice *dev;
2000 struct stm32mp1_clk_priv *priv;
2003 ret = uclass_get_device_by_driver(UCLASS_CLK,
2004 DM_GET_DRIVER(stm32mp1_clock),
2009 priv = dev_get_priv(dev);
2011 stm32mp1_clk_dump(priv);
2017 static int stm32mp1_clk_probe(struct udevice *dev)
2020 struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
2022 priv->base = dev_read_addr(dev->parent);
2023 if (priv->base == FDT_ADDR_T_NONE)
2026 priv->data = (void *)&stm32mp1_data;
2028 if (!priv->data->gate || !priv->data->sel ||
2032 stm32mp1_osc_init(dev);
2034 #ifdef STM32MP1_CLOCK_TREE_INIT
2035 /* clock tree init is done only one time, before relocation */
2036 if (!(gd->flags & GD_FLG_RELOC))
2037 result = stm32mp1_clktree(dev);
2040 #ifndef CONFIG_SPL_BUILD
2042 /* display debug information for probe after relocation */
2043 if (gd->flags & GD_FLG_RELOC)
2044 stm32mp1_clk_dump(priv);
2047 gd->cpu_clk = stm32mp1_clk_get(priv, _CK_MPU);
2048 gd->bus_clk = stm32mp1_clk_get(priv, _ACLK);
2049 /* DDRPHYC father */
2050 gd->mem_clk = stm32mp1_clk_get(priv, _PLL2_R);
2051 #if defined(CONFIG_DISPLAY_CPUINFO)
2052 if (gd->flags & GD_FLG_RELOC) {
2055 printf("Clocks:\n");
2056 printf("- MPU : %s MHz\n", strmhz(buf, gd->cpu_clk));
2057 printf("- MCU : %s MHz\n",
2058 strmhz(buf, stm32mp1_clk_get(priv, _CK_MCU)));
2059 printf("- AXI : %s MHz\n", strmhz(buf, gd->bus_clk));
2060 printf("- PER : %s MHz\n",
2061 strmhz(buf, stm32mp1_clk_get(priv, _CK_PER)));
2062 printf("- DDR : %s MHz\n", strmhz(buf, gd->mem_clk));
2064 #endif /* CONFIG_DISPLAY_CPUINFO */
2070 static const struct clk_ops stm32mp1_clk_ops = {
2071 .enable = stm32mp1_clk_enable,
2072 .disable = stm32mp1_clk_disable,
2073 .get_rate = stm32mp1_clk_get_rate,
2074 .set_rate = stm32mp1_clk_set_rate,
2077 U_BOOT_DRIVER(stm32mp1_clock) = {
2078 .name = "stm32mp1_clk",
2080 .ops = &stm32mp1_clk_ops,
2081 .priv_auto_alloc_size = sizeof(struct stm32mp1_clk_priv),
2082 .probe = stm32mp1_clk_probe,