drivers/clk/clk_stm32mp1.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   4  */
   5
   6 #include <common.h>
   7 #include <clk-uclass.h>
   8 #include <div64.h>
   9 #include <dm.h>
  10 #include <regmap.h>
  11 #include <spl.h>
  12 #include <syscon.h>
  13 #include <linux/io.h>
  14 #include <linux/iopoll.h>
  15 #include <dt-bindings/clock/stm32mp1-clks.h>
  16 #include <dt-bindings/clock/stm32mp1-clksrc.h>
  17
  18 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
  19 /* activate clock tree initialization in the driver */
  20 #define STM32MP1_CLOCK_TREE_INIT
  21 #endif
  22
  23 #define MAX_HSI_HZ              64000000
  24
  25 /* TIMEOUT */
  26 #define TIMEOUT_200MS           200000
  27 #define TIMEOUT_1S              1000000
  28
  29 /* STGEN registers */
  30 #define STGENC_CNTCR            0x00
  31 #define STGENC_CNTSR            0x04
  32 #define STGENC_CNTCVL           0x08
  33 #define STGENC_CNTCVU           0x0C
  34 #define STGENC_CNTFID0          0x20
  35
  36 #define STGENC_CNTCR_EN         BIT(0)
  37
  38 /* RCC registers */
  39 #define RCC_OCENSETR            0x0C
  40 #define RCC_OCENCLRR            0x10
  41 #define RCC_HSICFGR             0x18
  42 #define RCC_MPCKSELR            0x20
  43 #define RCC_ASSCKSELR           0x24
  44 #define RCC_RCK12SELR           0x28
  45 #define RCC_MPCKDIVR            0x2C
  46 #define RCC_AXIDIVR             0x30
  47 #define RCC_APB4DIVR            0x3C
  48 #define RCC_APB5DIVR            0x40
  49 #define RCC_RTCDIVR             0x44
  50 #define RCC_MSSCKSELR           0x48
  51 #define RCC_PLL1CR              0x80
  52 #define RCC_PLL1CFGR1           0x84
  53 #define RCC_PLL1CFGR2           0x88
  54 #define RCC_PLL1FRACR           0x8C
  55 #define RCC_PLL1CSGR            0x90
  56 #define RCC_PLL2CR              0x94
  57 #define RCC_PLL2CFGR1           0x98
  58 #define RCC_PLL2CFGR2           0x9C
  59 #define RCC_PLL2FRACR           0xA0
  60 #define RCC_PLL2CSGR            0xA4
  61 #define RCC_I2C46CKSELR         0xC0
  62 #define RCC_CPERCKSELR          0xD0
  63 #define RCC_STGENCKSELR         0xD4
  64 #define RCC_DDRITFCR            0xD8
  65 #define RCC_BDCR                0x140
  66 #define RCC_RDLSICR             0x144
  67 #define RCC_MP_APB4ENSETR       0x200
  68 #define RCC_MP_APB5ENSETR       0x208
  69 #define RCC_MP_AHB5ENSETR       0x210
  70 #define RCC_MP_AHB6ENSETR       0x218
  71 #define RCC_OCRDYR              0x808
  72 #define RCC_DBGCFGR             0x80C
  73 #define RCC_RCK3SELR            0x820
  74 #define RCC_RCK4SELR            0x824
  75 #define RCC_MCUDIVR             0x830
  76 #define RCC_APB1DIVR            0x834
  77 #define RCC_APB2DIVR            0x838
  78 #define RCC_APB3DIVR            0x83C
  79 #define RCC_PLL3CR              0x880
  80 #define RCC_PLL3CFGR1           0x884
  81 #define RCC_PLL3CFGR2           0x888
  82 #define RCC_PLL3FRACR           0x88C
  83 #define RCC_PLL3CSGR            0x890
  84 #define RCC_PLL4CR              0x894
  85 #define RCC_PLL4CFGR1           0x898
  86 #define RCC_PLL4CFGR2           0x89C
  87 #define RCC_PLL4FRACR           0x8A0
  88 #define RCC_PLL4CSGR            0x8A4
  89 #define RCC_I2C12CKSELR         0x8C0
  90 #define RCC_I2C35CKSELR         0x8C4
  91 #define RCC_UART6CKSELR         0x8E4
  92 #define RCC_UART24CKSELR        0x8E8
  93 #define RCC_UART35CKSELR        0x8EC
  94 #define RCC_UART78CKSELR        0x8F0
  95 #define RCC_SDMMC12CKSELR       0x8F4
  96 #define RCC_SDMMC3CKSELR        0x8F8
  97 #define RCC_ETHCKSELR           0x8FC
  98 #define RCC_QSPICKSELR          0x900
  99 #define RCC_FMCCKSELR           0x904
 100 #define RCC_USBCKSELR           0x91C
 101 #define RCC_MP_APB1ENSETR       0xA00
 102 #define RCC_MP_APB2ENSETR       0XA08
 103 #define RCC_MP_APB3ENSETR       0xA10
 104 #define RCC_MP_AHB2ENSETR       0xA18
 105 #define RCC_MP_AHB4ENSETR       0xA28
 106
 107 /* used for most of SELR register */
 108 #define RCC_SELR_SRC_MASK       GENMASK(2, 0)
 109 #define RCC_SELR_SRCRDY         BIT(31)
 110
 111 /* Values of RCC_MPCKSELR register */
 112 #define RCC_MPCKSELR_HSI        0
 113 #define RCC_MPCKSELR_HSE        1
 114 #define RCC_MPCKSELR_PLL        2
 115 #define RCC_MPCKSELR_PLL_MPUDIV 3
 116
 117 /* Values of RCC_ASSCKSELR register */
 118 #define RCC_ASSCKSELR_HSI       0
 119 #define RCC_ASSCKSELR_HSE       1
 120 #define RCC_ASSCKSELR_PLL       2
 121
 122 /* Values of RCC_MSSCKSELR register */
 123 #define RCC_MSSCKSELR_HSI       0
 124 #define RCC_MSSCKSELR_HSE       1
 125 #define RCC_MSSCKSELR_CSI       2
 126 #define RCC_MSSCKSELR_PLL       3
 127
 128 /* Values of RCC_CPERCKSELR register */
 129 #define RCC_CPERCKSELR_HSI      0
 130 #define RCC_CPERCKSELR_CSI      1
 131 #define RCC_CPERCKSELR_HSE      2
 132
 133 /* used for most of DIVR register : max div for RTC */
 134 #define RCC_DIVR_DIV_MASK       GENMASK(5, 0)
 135 #define RCC_DIVR_DIVRDY         BIT(31)
 136
 137 /* Masks for specific DIVR registers */
 138 #define RCC_APBXDIV_MASK        GENMASK(2, 0)
 139 #define RCC_MPUDIV_MASK         GENMASK(2, 0)
 140 #define RCC_AXIDIV_MASK         GENMASK(2, 0)
 141 #define RCC_MCUDIV_MASK         GENMASK(3, 0)
 142
 143 /*  offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
 144 #define RCC_MP_ENCLRR_OFFSET    4
 145
 146 /* Fields of RCC_BDCR register */
 147 #define RCC_BDCR_LSEON          BIT(0)
 148 #define RCC_BDCR_LSEBYP         BIT(1)
 149 #define RCC_BDCR_LSERDY         BIT(2)
 150 #define RCC_BDCR_LSEDRV_MASK    GENMASK(5, 4)
 151 #define RCC_BDCR_LSEDRV_SHIFT   4
 152 #define RCC_BDCR_LSECSSON       BIT(8)
 153 #define RCC_BDCR_RTCCKEN        BIT(20)
 154 #define RCC_BDCR_RTCSRC_MASK    GENMASK(17, 16)
 155 #define RCC_BDCR_RTCSRC_SHIFT   16
 156
 157 /* Fields of RCC_RDLSICR register */
 158 #define RCC_RDLSICR_LSION       BIT(0)
 159 #define RCC_RDLSICR_LSIRDY      BIT(1)
 160
 161 /* used for ALL PLLNCR registers */
 162 #define RCC_PLLNCR_PLLON        BIT(0)
 163 #define RCC_PLLNCR_PLLRDY       BIT(1)
 164 #define RCC_PLLNCR_DIVPEN       BIT(4)
 165 #define RCC_PLLNCR_DIVQEN       BIT(5)
 166 #define RCC_PLLNCR_DIVREN       BIT(6)
 167 #define RCC_PLLNCR_DIVEN_SHIFT  4
 168
 169 /* used for ALL PLLNCFGR1 registers */
 170 #define RCC_PLLNCFGR1_DIVM_SHIFT        16
 171 #define RCC_PLLNCFGR1_DIVM_MASK         GENMASK(21, 16)
 172 #define RCC_PLLNCFGR1_DIVN_SHIFT        0
 173 #define RCC_PLLNCFGR1_DIVN_MASK         GENMASK(8, 0)
 174 /* only for PLL3 and PLL4 */
 175 #define RCC_PLLNCFGR1_IFRGE_SHIFT       24
 176 #define RCC_PLLNCFGR1_IFRGE_MASK        GENMASK(25, 24)
 177
 178 /* used for ALL PLLNCFGR2 registers , using stm32mp1_div_id */
 179 #define RCC_PLLNCFGR2_SHIFT(div_id)     ((div_id) * 8)
 180 #define RCC_PLLNCFGR2_DIVX_MASK         GENMASK(6, 0)
 181 #define RCC_PLLNCFGR2_DIVP_SHIFT        RCC_PLLNCFGR2_SHIFT(_DIV_P)
 182 #define RCC_PLLNCFGR2_DIVP_MASK         GENMASK(6, 0)
 183 #define RCC_PLLNCFGR2_DIVQ_SHIFT        RCC_PLLNCFGR2_SHIFT(_DIV_Q)
 184 #define RCC_PLLNCFGR2_DIVQ_MASK         GENMASK(14, 8)
 185 #define RCC_PLLNCFGR2_DIVR_SHIFT        RCC_PLLNCFGR2_SHIFT(_DIV_R)
 186 #define RCC_PLLNCFGR2_DIVR_MASK         GENMASK(22, 16)
 187
 188 /* used for ALL PLLNFRACR registers */
 189 #define RCC_PLLNFRACR_FRACV_SHIFT       3
 190 #define RCC_PLLNFRACR_FRACV_MASK        GENMASK(15, 3)
 191 #define RCC_PLLNFRACR_FRACLE            BIT(16)
 192
 193 /* used for ALL PLLNCSGR registers */
 194 #define RCC_PLLNCSGR_INC_STEP_SHIFT     16
 195 #define RCC_PLLNCSGR_INC_STEP_MASK      GENMASK(30, 16)
 196 #define RCC_PLLNCSGR_MOD_PER_SHIFT      0
 197 #define RCC_PLLNCSGR_MOD_PER_MASK       GENMASK(12, 0)
 198 #define RCC_PLLNCSGR_SSCG_MODE_SHIFT    15
 199 #define RCC_PLLNCSGR_SSCG_MODE_MASK     BIT(15)
 200
 201 /* used for RCC_OCENSETR and RCC_OCENCLRR registers */
 202 #define RCC_OCENR_HSION                 BIT(0)
 203 #define RCC_OCENR_CSION                 BIT(4)
 204 #define RCC_OCENR_HSEON                 BIT(8)
 205 #define RCC_OCENR_HSEBYP                BIT(10)
 206 #define RCC_OCENR_HSECSSON              BIT(11)
 207
 208 /* Fields of RCC_OCRDYR register */
 209 #define RCC_OCRDYR_HSIRDY               BIT(0)
 210 #define RCC_OCRDYR_HSIDIVRDY            BIT(2)
 211 #define RCC_OCRDYR_CSIRDY               BIT(4)
 212 #define RCC_OCRDYR_HSERDY               BIT(8)
 213
 214 /* Fields of DDRITFCR register */
 215 #define RCC_DDRITFCR_DDRCKMOD_MASK      GENMASK(22, 20)
 216 #define RCC_DDRITFCR_DDRCKMOD_SHIFT     20
 217 #define RCC_DDRITFCR_DDRCKMOD_SSR       0
 218
 219 /* Fields of RCC_HSICFGR register */
 220 #define RCC_HSICFGR_HSIDIV_MASK         GENMASK(1, 0)
 221
 222 /* used for MCO related operations */
 223 #define RCC_MCOCFG_MCOON                BIT(12)
 224 #define RCC_MCOCFG_MCODIV_MASK          GENMASK(7, 4)
 225 #define RCC_MCOCFG_MCODIV_SHIFT         4
 226 #define RCC_MCOCFG_MCOSRC_MASK          GENMASK(2, 0)
 227
 228 enum stm32mp1_parent_id {
 229 /*
 230  * _HSI, _HSE, _CSI, _LSI, _LSE should not be moved
 231  * they are used as index in osc[] as entry point
 232  */
 233         _HSI,
 234         _HSE,
 235         _CSI,
 236         _LSI,
 237         _LSE,
 238         _I2S_CKIN,
 239         _USB_PHY_48,
 240         NB_OSC,
 241
 242 /* other parent source */
 243         _HSI_KER = NB_OSC,
 244         _HSE_KER,
 245         _HSE_KER_DIV2,
 246         _CSI_KER,
 247         _PLL1_P,
 248         _PLL1_Q,
 249         _PLL1_R,
 250         _PLL2_P,
 251         _PLL2_Q,
 252         _PLL2_R,
 253         _PLL3_P,
 254         _PLL3_Q,
 255         _PLL3_R,
 256         _PLL4_P,
 257         _PLL4_Q,
 258         _PLL4_R,
 259         _ACLK,
 260         _PCLK1,
 261         _PCLK2,
 262         _PCLK3,
 263         _PCLK4,
 264         _PCLK5,
 265         _HCLK6,
 266         _HCLK2,
 267         _CK_PER,
 268         _CK_MPU,
 269         _CK_MCU,
 270         _PARENT_NB,
 271         _UNKNOWN_ID = 0xff,
 272 };
 273
 274 enum stm32mp1_parent_sel {
 275         _I2C12_SEL,
 276         _I2C35_SEL,
 277         _I2C46_SEL,
 278         _UART6_SEL,
 279         _UART24_SEL,
 280         _UART35_SEL,
 281         _UART78_SEL,
 282         _SDMMC12_SEL,
 283         _SDMMC3_SEL,
 284         _ETH_SEL,
 285         _QSPI_SEL,
 286         _FMC_SEL,
 287         _USBPHY_SEL,
 288         _USBO_SEL,
 289         _STGEN_SEL,
 290         _PARENT_SEL_NB,
 291         _UNKNOWN_SEL = 0xff,
 292 };
 293
 294 enum stm32mp1_pll_id {
 295         _PLL1,
 296         _PLL2,
 297         _PLL3,
 298         _PLL4,
 299         _PLL_NB
 300 };
 301
 302 enum stm32mp1_div_id {
 303         _DIV_P,
 304         _DIV_Q,
 305         _DIV_R,
 306         _DIV_NB,
 307 };
 308
 309 enum stm32mp1_clksrc_id {
 310         CLKSRC_MPU,
 311         CLKSRC_AXI,
 312         CLKSRC_MCU,
 313         CLKSRC_PLL12,
 314         CLKSRC_PLL3,
 315         CLKSRC_PLL4,
 316         CLKSRC_RTC,
 317         CLKSRC_MCO1,
 318         CLKSRC_MCO2,
 319         CLKSRC_NB
 320 };
 321
 322 enum stm32mp1_clkdiv_id {
 323         CLKDIV_MPU,
 324         CLKDIV_AXI,
 325         CLKDIV_MCU,
 326         CLKDIV_APB1,
 327         CLKDIV_APB2,
 328         CLKDIV_APB3,
 329         CLKDIV_APB4,
 330         CLKDIV_APB5,
 331         CLKDIV_RTC,
 332         CLKDIV_MCO1,
 333         CLKDIV_MCO2,
 334         CLKDIV_NB
 335 };
 336
 337 enum stm32mp1_pllcfg {
 338         PLLCFG_M,
 339         PLLCFG_N,
 340         PLLCFG_P,
 341         PLLCFG_Q,
 342         PLLCFG_R,
 343         PLLCFG_O,
 344         PLLCFG_NB
 345 };
 346
 347 enum stm32mp1_pllcsg {
 348         PLLCSG_MOD_PER,
 349         PLLCSG_INC_STEP,
 350         PLLCSG_SSCG_MODE,
 351         PLLCSG_NB
 352 };
 353
 354 enum stm32mp1_plltype {
 355         PLL_800,
 356         PLL_1600,
 357         PLL_TYPE_NB
 358 };
 359
 360 struct stm32mp1_pll {
 361         u8 refclk_min;
 362         u8 refclk_max;
 363         u8 divn_max;
 364 };
 365
 366 struct stm32mp1_clk_gate {
 367         u16 offset;
 368         u8 bit;
 369         u8 index;
 370         u8 set_clr;
 371         u8 sel;
 372         u8 fixed;
 373 };
 374
 375 struct stm32mp1_clk_sel {
 376         u16 offset;
 377         u8 src;
 378         u8 msk;
 379         u8 nb_parent;
 380         const u8 *parent;
 381 };
 382
 383 #define REFCLK_SIZE 4
 384 struct stm32mp1_clk_pll {
 385         enum stm32mp1_plltype plltype;
 386         u16 rckxselr;
 387         u16 pllxcfgr1;
 388         u16 pllxcfgr2;
 389         u16 pllxfracr;
 390         u16 pllxcr;
 391         u16 pllxcsgr;
 392         u8 refclk[REFCLK_SIZE];
 393 };
 394
 395 struct stm32mp1_clk_data {
 396         const struct stm32mp1_clk_gate *gate;
 397         const struct stm32mp1_clk_sel *sel;
 398         const struct stm32mp1_clk_pll *pll;
 399         const int nb_gate;
 400 };
 401
 402 struct stm32mp1_clk_priv {
 403         fdt_addr_t base;
 404         const struct stm32mp1_clk_data *data;
 405         ulong osc[NB_OSC];
 406         struct udevice *osc_dev[NB_OSC];
 407 };
 408
 409 #define STM32MP1_CLK(off, b, idx, s)            \
 410         {                                       \
 411                 .offset = (off),                \
 412                 .bit = (b),                     \
 413                 .index = (idx),                 \
 414                 .set_clr = 0,                   \
 415                 .sel = (s),                     \
 416                 .fixed = _UNKNOWN_ID,           \
 417         }
 418
 419 #define STM32MP1_CLK_F(off, b, idx, f)          \
 420         {                                       \
 421                 .offset = (off),                \
 422                 .bit = (b),                     \
 423                 .index = (idx),                 \
 424                 .set_clr = 0,                   \
 425                 .sel = _UNKNOWN_SEL,            \
 426                 .fixed = (f),                   \
 427         }
 428
 429 #define STM32MP1_CLK_SET_CLR(off, b, idx, s)    \
 430         {                                       \
 431                 .offset = (off),                \
 432                 .bit = (b),                     \
 433                 .index = (idx),                 \
 434                 .set_clr = 1,                   \
 435                 .sel = (s),                     \
 436                 .fixed = _UNKNOWN_ID,           \
 437         }
 438
 439 #define STM32MP1_CLK_SET_CLR_F(off, b, idx, f)  \
 440         {                                       \
 441                 .offset = (off),                \
 442                 .bit = (b),                     \
 443                 .index = (idx),                 \
 444                 .set_clr = 1,                   \
 445                 .sel = _UNKNOWN_SEL,            \
 446                 .fixed = (f),                   \
 447         }
 448
 449 #define STM32MP1_CLK_PARENT(idx, off, s, m, p)   \
 450         [(idx)] = {                             \
 451                 .offset = (off),                \
 452                 .src = (s),                     \
 453                 .msk = (m),                     \
 454                 .parent = (p),                  \
 455                 .nb_parent = ARRAY_SIZE((p))    \
 456         }
 457
 458 #define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, off4, off5, off6,\
 459                         p1, p2, p3, p4) \
 460         [(idx)] = {                             \
 461                 .plltype = (type),                      \
 462                 .rckxselr = (off1),             \
 463                 .pllxcfgr1 = (off2),            \
 464                 .pllxcfgr2 = (off3),            \
 465                 .pllxfracr = (off4),            \
 466                 .pllxcr = (off5),               \
 467                 .pllxcsgr = (off6),             \
 468                 .refclk[0] = (p1),              \
 469                 .refclk[1] = (p2),              \
 470                 .refclk[2] = (p3),              \
 471                 .refclk[3] = (p4),              \
 472         }
 473
 474 static const u8 stm32mp1_clks[][2] = {
 475         {CK_PER, _CK_PER},
 476         {CK_MPU, _CK_MPU},
 477         {CK_AXI, _ACLK},
 478         {CK_MCU, _CK_MCU},
 479         {CK_HSE, _HSE},
 480         {CK_CSI, _CSI},
 481         {CK_LSI, _LSI},
 482         {CK_LSE, _LSE},
 483         {CK_HSI, _HSI},
 484         {CK_HSE_DIV2, _HSE_KER_DIV2},
 485 };
 486
 487 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
 488         STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL),
 489         STM32MP1_CLK(RCC_DDRITFCR, 1, DDRC1LP, _UNKNOWN_SEL),
 490         STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL),
 491         STM32MP1_CLK(RCC_DDRITFCR, 3, DDRC2LP, _UNKNOWN_SEL),
 492         STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
 493         STM32MP1_CLK(RCC_DDRITFCR, 5, DDRPHYCLP, _UNKNOWN_SEL),
 494         STM32MP1_CLK(RCC_DDRITFCR, 6, DDRCAPB, _UNKNOWN_SEL),
 495         STM32MP1_CLK(RCC_DDRITFCR, 7, DDRCAPBLP, _UNKNOWN_SEL),
 496         STM32MP1_CLK(RCC_DDRITFCR, 8, AXIDCG, _UNKNOWN_SEL),
 497         STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL),
 498         STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL),
 499
 500         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
 501         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
 502         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
 503         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL),
 504         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL),
 505         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL),
 506         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL),
 507         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL),
 508         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL),
 509         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
 510
 511         STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
 512
 513         STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3),
 514
 515         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
 516         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
 517         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
 518
 519         STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
 520         STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
 521
 522         STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
 523         STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
 524
 525         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
 526         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
 527         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
 528         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL),
 529         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL),
 530         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL),
 531         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL),
 532         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL),
 533         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL),
 534         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL),
 535         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
 536
 537         STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
 538
 539         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK, _UNKNOWN_SEL),
 540         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL),
 541         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL),
 542         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 10, ETHMAC_K, _ETH_SEL),
 543         STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK),
 544         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
 545         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
 546         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL),
 547         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL),
 548         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL),
 549
 550         STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
 551 };
 552
 553 static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
 554 static const u8 i2c35_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
 555 static const u8 i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER};
 556 static const u8 uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
 557                                         _HSE_KER};
 558 static const u8 uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 559                                          _HSE_KER};
 560 static const u8 uart35_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 561                                          _HSE_KER};
 562 static const u8 uart78_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 563                                          _HSE_KER};
 564 static const u8 sdmmc12_parents[] = {_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER};
 565 static const u8 sdmmc3_parents[] = {_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER};
 566 static const u8 eth_parents[] = {_PLL4_P, _PLL3_Q};
 567 static const u8 qspi_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
 568 static const u8 fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
 569 static const u8 usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2};
 570 static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48};
 571 static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER};
 572
 573 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
 574         STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents),
 575         STM32MP1_CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents),
 576         STM32MP1_CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents),
 577         STM32MP1_CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents),
 578         STM32MP1_CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7,
 579                             uart24_parents),
 580         STM32MP1_CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7,
 581                             uart35_parents),
 582         STM32MP1_CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7,
 583                             uart78_parents),
 584         STM32MP1_CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7,
 585                             sdmmc12_parents),
 586         STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7,
 587                             sdmmc3_parents),
 588         STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents),
 589         STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents),
 590         STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents),
 591         STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents),
 592         STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
 593         STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
 594 };
 595
 596 #ifdef STM32MP1_CLOCK_TREE_INIT
 597 /* define characteristic of PLL according type */
 598 #define DIVN_MIN        24
 599 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
 600         [PLL_800] = {
 601                 .refclk_min = 4,
 602                 .refclk_max = 16,
 603                 .divn_max = 99,
 604                 },
 605         [PLL_1600] = {
 606                 .refclk_min = 8,
 607                 .refclk_max = 16,
 608                 .divn_max = 199,
 609                 },
 610 };
 611 #endif /* STM32MP1_CLOCK_TREE_INIT */
 612
 613 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = {
 614         STM32MP1_CLK_PLL(_PLL1, PLL_1600,
 615                          RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2,
 616                          RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR,
 617                          _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
 618         STM32MP1_CLK_PLL(_PLL2, PLL_1600,
 619                          RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2,
 620                          RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR,
 621                          _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
 622         STM32MP1_CLK_PLL(_PLL3, PLL_800,
 623                          RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2,
 624                          RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR,
 625                          _HSI, _HSE, _CSI, _UNKNOWN_ID),
 626         STM32MP1_CLK_PLL(_PLL4, PLL_800,
 627                          RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2,
 628                          RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR,
 629                          _HSI, _HSE, _CSI, _I2S_CKIN),
 630 };
 631
 632 /* Prescaler table lookups for clock computation */
 633 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */
 634 static const u8 stm32mp1_mcu_div[16] = {
 635         0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9
 636 };
 637
 638 /* div = /1 /2 /4 /8 /16 : same divider for pmu and apbx*/
 639 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div
 640 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div
 641 static const u8 stm32mp1_mpu_apbx_div[8] = {
 642         0, 1, 2, 3, 4, 4, 4, 4
 643 };
 644
 645 /* div = /1 /2 /3 /4 */
 646 static const u8 stm32mp1_axi_div[8] = {
 647         1, 2, 3, 4, 4, 4, 4, 4
 648 };
 649
 650 #ifdef DEBUG
 651 static const char * const stm32mp1_clk_parent_name[_PARENT_NB] = {
 652         [_HSI] = "HSI",
 653         [_HSE] = "HSE",
 654         [_CSI] = "CSI",
 655         [_LSI] = "LSI",
 656         [_LSE] = "LSE",
 657         [_I2S_CKIN] = "I2S_CKIN",
 658         [_HSI_KER] = "HSI_KER",
 659         [_HSE_KER] = "HSE_KER",
 660         [_HSE_KER_DIV2] = "HSE_KER_DIV2",
 661         [_CSI_KER] = "CSI_KER",
 662         [_PLL1_P] = "PLL1_P",
 663         [_PLL1_Q] = "PLL1_Q",
 664         [_PLL1_R] = "PLL1_R",
 665         [_PLL2_P] = "PLL2_P",
 666         [_PLL2_Q] = "PLL2_Q",
 667         [_PLL2_R] = "PLL2_R",
 668         [_PLL3_P] = "PLL3_P",
 669         [_PLL3_Q] = "PLL3_Q",
 670         [_PLL3_R] = "PLL3_R",
 671         [_PLL4_P] = "PLL4_P",
 672         [_PLL4_Q] = "PLL4_Q",
 673         [_PLL4_R] = "PLL4_R",
 674         [_ACLK] = "ACLK",
 675         [_PCLK1] = "PCLK1",
 676         [_PCLK2] = "PCLK2",
 677         [_PCLK3] = "PCLK3",
 678         [_PCLK4] = "PCLK4",
 679         [_PCLK5] = "PCLK5",
 680         [_HCLK6] = "KCLK6",
 681         [_HCLK2] = "HCLK2",
 682         [_CK_PER] = "CK_PER",
 683         [_CK_MPU] = "CK_MPU",
 684         [_CK_MCU] = "CK_MCU",
 685         [_USB_PHY_48] = "USB_PHY_48"
 686 };
 687
 688 static const char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
 689         [_I2C12_SEL] = "I2C12",
 690         [_I2C35_SEL] = "I2C35",
 691         [_I2C46_SEL] = "I2C46",
 692         [_UART6_SEL] = "UART6",
 693         [_UART24_SEL] = "UART24",
 694         [_UART35_SEL] = "UART35",
 695         [_UART78_SEL] = "UART78",
 696         [_SDMMC12_SEL] = "SDMMC12",
 697         [_SDMMC3_SEL] = "SDMMC3",
 698         [_ETH_SEL] = "ETH",
 699         [_QSPI_SEL] = "QSPI",
 700         [_FMC_SEL] = "FMC",
 701         [_USBPHY_SEL] = "USBPHY",
 702         [_USBO_SEL] = "USBO",
 703         [_STGEN_SEL] = "STGEN"
 704 };
 705 #endif
 706
 707 static const struct stm32mp1_clk_data stm32mp1_data = {
 708         .gate = stm32mp1_clk_gate,
 709         .sel = stm32mp1_clk_sel,
 710         .pll = stm32mp1_clk_pll,
 711         .nb_gate = ARRAY_SIZE(stm32mp1_clk_gate),
 712 };
 713
 714 static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx)
 715 {
 716         if (idx >= NB_OSC) {
 717                 debug("%s: clk id %d not found\n", __func__, idx);
 718                 return 0;
 719         }
 720
 721         debug("%s: clk id %d = %x : %ld kHz\n", __func__, idx,
 722               (u32)priv->osc[idx], priv->osc[idx] / 1000);
 723
 724         return priv->osc[idx];
 725 }
 726
 727 static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id)
 728 {
 729         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 730         int i, nb_clks = priv->data->nb_gate;
 731
 732         for (i = 0; i < nb_clks; i++) {
 733                 if (gate[i].index == id)
 734                         break;
 735         }
 736
 737         if (i == nb_clks) {
 738                 printf("%s: clk id %d not found\n", __func__, (u32)id);
 739                 return -EINVAL;
 740         }
 741
 742         return i;
 743 }
 744
 745 static int stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv,
 746                                 int i)
 747 {
 748         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 749
 750         if (gate[i].sel > _PARENT_SEL_NB) {
 751                 printf("%s: parents for clk id %d not found\n",
 752                        __func__, i);
 753                 return -EINVAL;
 754         }
 755
 756         return gate[i].sel;
 757 }
 758
 759 static int stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv *priv,
 760                                          int i)
 761 {
 762         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 763
 764         if (gate[i].fixed == _UNKNOWN_ID)
 765                 return -ENOENT;
 766
 767         return gate[i].fixed;
 768 }
 769
 770 static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv,
 771                                    unsigned long id)
 772 {
 773         const struct stm32mp1_clk_sel *sel = priv->data->sel;
 774         int i;
 775         int s, p;
 776
 777         for (i = 0; i < ARRAY_SIZE(stm32mp1_clks); i++)
 778                 if (stm32mp1_clks[i][0] == id)
 779                         return stm32mp1_clks[i][1];
 780
 781         i = stm32mp1_clk_get_id(priv, id);
 782         if (i < 0)
 783                 return i;
 784
 785         p = stm32mp1_clk_get_fixed_parent(priv, i);
 786         if (p >= 0 && p < _PARENT_NB)
 787                 return p;
 788
 789         s = stm32mp1_clk_get_sel(priv, i);
 790         if (s < 0)
 791                 return s;
 792
 793         p = (readl(priv->base + sel[s].offset) >> sel[s].src) & sel[s].msk;
 794
 795         if (p < sel[s].nb_parent) {
 796 #ifdef DEBUG
 797                 debug("%s: %s clock is the parent %s of clk id %d\n", __func__,
 798                       stm32mp1_clk_parent_name[sel[s].parent[p]],
 799                       stm32mp1_clk_parent_sel_name[s],
 800                       (u32)id);
 801 #endif
 802                 return sel[s].parent[p];
 803         }
 804
 805         pr_err("%s: no parents defined for clk id %d\n",
 806                __func__, (u32)id);
 807
 808         return -EINVAL;
 809 }
 810
 811 static ulong  pll_get_fref_ck(struct stm32mp1_clk_priv *priv,
 812                               int pll_id)
 813 {
 814         const struct stm32mp1_clk_pll *pll = priv->data->pll;
 815         u32 selr;
 816         int src;
 817         ulong refclk;
 818
 819         /* Get current refclk */
 820         selr = readl(priv->base + pll[pll_id].rckxselr);
 821         src = selr & RCC_SELR_SRC_MASK;
 822
 823         refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]);
 824         debug("PLL%d : selr=%x refclk = %d kHz\n",
 825               pll_id, selr, (u32)(refclk / 1000));
 826
 827         return refclk;
 828 }
 829
 830 /*
 831  * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL
 832  * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1)
 833  * - PLL3 & PLL4 => return VCO     with Fpll_y_ck = FVCO / (DIVy + 1)
 834  * => in all the case Fpll_y_ck = pll_get_fvco() / (DIVy + 1)
 835  */
 836 static ulong pll_get_fvco(struct stm32mp1_clk_priv *priv,
 837                           int pll_id)
 838 {
 839         const struct stm32mp1_clk_pll *pll = priv->data->pll;
 840         int divm, divn;
 841         ulong refclk, fvco;
 842         u32 cfgr1, fracr;
 843
 844         cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1);
 845         fracr = readl(priv->base + pll[pll_id].pllxfracr);
 846
 847         divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
 848         divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
 849
 850         debug("PLL%d : cfgr1=%x fracr=%x DIVN=%d DIVM=%d\n",
 851               pll_id, cfgr1, fracr, divn, divm);
 852
 853         refclk = pll_get_fref_ck(priv, pll_id);
 854
 855         /* with FRACV :
 856          *   Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1)
 857          * without FRACV
 858          *   Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1)
 859          */
 860         if (fracr & RCC_PLLNFRACR_FRACLE) {
 861                 u32 fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK)
 862                             >> RCC_PLLNFRACR_FRACV_SHIFT;
 863                 fvco = (ulong)lldiv((unsigned long long)refclk *
 864                                      (((divn + 1) << 13) + fracv),
 865                                      ((unsigned long long)(divm + 1)) << 13);
 866         } else {
 867                 fvco = (ulong)(refclk * (divn + 1) / (divm + 1));
 868         }
 869         debug("PLL%d : %s = %ld\n", pll_id, __func__, fvco);
 870
 871         return fvco;
 872 }
 873
 874 static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
 875                                     int pll_id, int div_id)
 876 {
 877         const struct stm32mp1_clk_pll *pll = priv->data->pll;
 878         int divy;
 879         ulong dfout;
 880         u32 cfgr2;
 881
 882         debug("%s(%d, %d)\n", __func__, pll_id, div_id);
 883         if (div_id >= _DIV_NB)
 884                 return 0;
 885
 886         cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2);
 887         divy = (cfgr2 >> RCC_PLLNCFGR2_SHIFT(div_id)) & RCC_PLLNCFGR2_DIVX_MASK;
 888
 889         debug("PLL%d : cfgr2=%x DIVY=%d\n", pll_id, cfgr2, divy);
 890
 891         dfout = pll_get_fvco(priv, pll_id) / (divy + 1);
 892         debug("        => dfout = %d kHz\n", (u32)(dfout / 1000));
 893
 894         return dfout;
 895 }
 896
 897 static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
 898 {
 899         u32 reg;
 900         ulong clock = 0;
 901
 902         switch (p) {
 903         case _CK_MPU:
 904         /* MPU sub system */
 905                 reg = readl(priv->base + RCC_MPCKSELR);
 906                 switch (reg & RCC_SELR_SRC_MASK) {
 907                 case RCC_MPCKSELR_HSI:
 908                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
 909                         break;
 910                 case RCC_MPCKSELR_HSE:
 911                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
 912                         break;
 913                 case RCC_MPCKSELR_PLL:
 914                 case RCC_MPCKSELR_PLL_MPUDIV:
 915                         clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P);
 916                         if (p == RCC_MPCKSELR_PLL_MPUDIV) {
 917                                 reg = readl(priv->base + RCC_MPCKDIVR);
 918                                 clock /= stm32mp1_mpu_div[reg &
 919                                                           RCC_MPUDIV_MASK];
 920                         }
 921                         break;
 922                 }
 923                 break;
 924         /* AXI sub system */
 925         case _ACLK:
 926         case _HCLK2:
 927         case _HCLK6:
 928         case _PCLK4:
 929         case _PCLK5:
 930                 reg = readl(priv->base + RCC_ASSCKSELR);
 931                 switch (reg & RCC_SELR_SRC_MASK) {
 932                 case RCC_ASSCKSELR_HSI:
 933                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
 934                         break;
 935                 case RCC_ASSCKSELR_HSE:
 936                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
 937                         break;
 938                 case RCC_ASSCKSELR_PLL:
 939                         clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P);
 940                         break;
 941                 }
 942
 943                 /* System clock divider */
 944                 reg = readl(priv->base + RCC_AXIDIVR);
 945                 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK];
 946
 947                 switch (p) {
 948                 case _PCLK4:
 949                         reg = readl(priv->base + RCC_APB4DIVR);
 950                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
 951                         break;
 952                 case _PCLK5:
 953                         reg = readl(priv->base + RCC_APB5DIVR);
 954                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
 955                         break;
 956                 default:
 957                         break;
 958                 }
 959                 break;
 960         /* MCU sub system */
 961         case _CK_MCU:
 962         case _PCLK1:
 963         case _PCLK2:
 964         case _PCLK3:
 965                 reg = readl(priv->base + RCC_MSSCKSELR);
 966                 switch (reg & RCC_SELR_SRC_MASK) {
 967                 case RCC_MSSCKSELR_HSI:
 968                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
 969                         break;
 970                 case RCC_MSSCKSELR_HSE:
 971                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
 972                         break;
 973                 case RCC_MSSCKSELR_CSI:
 974                         clock = stm32mp1_clk_get_fixed(priv, _CSI);
 975                         break;
 976                 case RCC_MSSCKSELR_PLL:
 977                         clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_P);
 978                         break;
 979                 }
 980
 981                 /* MCU clock divider */
 982                 reg = readl(priv->base + RCC_MCUDIVR);
 983                 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK];
 984
 985                 switch (p) {
 986                 case _PCLK1:
 987                         reg = readl(priv->base + RCC_APB1DIVR);
 988                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
 989                         break;
 990                 case _PCLK2:
 991                         reg = readl(priv->base + RCC_APB2DIVR);
 992                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
 993                         break;
 994                 case _PCLK3:
 995                         reg = readl(priv->base + RCC_APB3DIVR);
 996                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
 997                         break;
 998                 case _CK_MCU:
 999                 default:
1000                         break;
1001                 }
1002                 break;
1003         case _CK_PER:
1004                 reg = readl(priv->base + RCC_CPERCKSELR);
1005                 switch (reg & RCC_SELR_SRC_MASK) {
1006                 case RCC_CPERCKSELR_HSI:
1007                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
1008                         break;
1009                 case RCC_CPERCKSELR_HSE:
1010                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
1011                         break;
1012                 case RCC_CPERCKSELR_CSI:
1013                         clock = stm32mp1_clk_get_fixed(priv, _CSI);
1014                         break;
1015                 }
1016                 break;
1017         case _HSI:
1018         case _HSI_KER:
1019                 clock = stm32mp1_clk_get_fixed(priv, _HSI);
1020                 break;
1021         case _CSI:
1022         case _CSI_KER:
1023                 clock = stm32mp1_clk_get_fixed(priv, _CSI);
1024                 break;
1025         case _HSE:
1026         case _HSE_KER:
1027         case _HSE_KER_DIV2:
1028                 clock = stm32mp1_clk_get_fixed(priv, _HSE);
1029                 if (p == _HSE_KER_DIV2)
1030                         clock >>= 1;
1031                 break;
1032         case _LSI:
1033                 clock = stm32mp1_clk_get_fixed(priv, _LSI);
1034                 break;
1035         case _LSE:
1036                 clock = stm32mp1_clk_get_fixed(priv, _LSE);
1037                 break;
1038         /* PLL */
1039         case _PLL1_P:
1040         case _PLL1_Q:
1041         case _PLL1_R:
1042                 clock = stm32mp1_read_pll_freq(priv, _PLL1, p - _PLL1_P);
1043                 break;
1044         case _PLL2_P:
1045         case _PLL2_Q:
1046         case _PLL2_R:
1047                 clock = stm32mp1_read_pll_freq(priv, _PLL2, p - _PLL2_P);
1048                 break;
1049         case _PLL3_P:
1050         case _PLL3_Q:
1051         case _PLL3_R:
1052                 clock = stm32mp1_read_pll_freq(priv, _PLL3, p - _PLL3_P);
1053                 break;
1054         case _PLL4_P:
1055         case _PLL4_Q:
1056         case _PLL4_R:
1057                 clock = stm32mp1_read_pll_freq(priv, _PLL4, p - _PLL4_P);
1058                 break;
1059         /* other */
1060         case _USB_PHY_48:
1061                 clock = stm32mp1_clk_get_fixed(priv, _USB_PHY_48);
1062                 break;
1063
1064         default:
1065                 break;
1066         }
1067
1068         debug("%s(%d) clock = %lx : %ld kHz\n",
1069               __func__, p, clock, clock / 1000);
1070
1071         return clock;
1072 }
1073
1074 static int stm32mp1_clk_enable(struct clk *clk)
1075 {
1076         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1077         const struct stm32mp1_clk_gate *gate = priv->data->gate;
1078         int i = stm32mp1_clk_get_id(priv, clk->id);
1079
1080         if (i < 0)
1081                 return i;
1082
1083         if (gate[i].set_clr)
1084                 writel(BIT(gate[i].bit), priv->base + gate[i].offset);
1085         else
1086                 setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1087
1088         debug("%s: id clock %d has been enabled\n", __func__, (u32)clk->id);
1089
1090         return 0;
1091 }
1092
1093 static int stm32mp1_clk_disable(struct clk *clk)
1094 {
1095         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1096         const struct stm32mp1_clk_gate *gate = priv->data->gate;
1097         int i = stm32mp1_clk_get_id(priv, clk->id);
1098
1099         if (i < 0)
1100                 return i;
1101
1102         if (gate[i].set_clr)
1103                 writel(BIT(gate[i].bit),
1104                        priv->base + gate[i].offset
1105                        + RCC_MP_ENCLRR_OFFSET);
1106         else
1107                 clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1108
1109         debug("%s: id clock %d has been disabled\n", __func__, (u32)clk->id);
1110
1111         return 0;
1112 }
1113
1114 static ulong stm32mp1_clk_get_rate(struct clk *clk)
1115 {
1116         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1117         int p = stm32mp1_clk_get_parent(priv, clk->id);
1118         ulong rate;
1119
1120         if (p < 0)
1121                 return 0;
1122
1123         rate = stm32mp1_clk_get(priv, p);
1124
1125 #ifdef DEBUG
1126         debug("%s: computed rate for id clock %d is %d (parent is %s)\n",
1127               __func__, (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]);
1128 #endif
1129         return rate;
1130 }
1131
1132 #ifdef STM32MP1_CLOCK_TREE_INIT
1133 static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset,
1134                                 u32 mask_on)
1135 {
1136         u32 address = rcc + offset;
1137
1138         if (enable)
1139                 setbits_le32(address, mask_on);
1140         else
1141                 clrbits_le32(address, mask_on);
1142 }
1143
1144 static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on)
1145 {
1146         if (enable)
1147                 setbits_le32(rcc + RCC_OCENSETR, mask_on);
1148         else
1149                 setbits_le32(rcc + RCC_OCENCLRR, mask_on);
1150 }
1151
1152 static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset,
1153                              u32 mask_rdy)
1154 {
1155         u32 mask_test = 0;
1156         u32 address = rcc + offset;
1157         u32 val;
1158         int ret;
1159
1160         if (enable)
1161                 mask_test = mask_rdy;
1162
1163         ret = readl_poll_timeout(address, val,
1164                                  (val & mask_rdy) == mask_test,
1165                                  TIMEOUT_1S);
1166
1167         if (ret)
1168                 pr_err("OSC %x @ %x timeout for enable=%d : 0x%x\n",
1169                        mask_rdy, address, enable, readl(address));
1170
1171         return ret;
1172 }
1173
1174 static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int lsedrv)
1175 {
1176         u32 value;
1177
1178         if (bypass)
1179                 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP);
1180
1181         /*
1182          * warning: not recommended to switch directly from "high drive"
1183          * to "medium low drive", and vice-versa.
1184          */
1185         value = (readl(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK)
1186                 >> RCC_BDCR_LSEDRV_SHIFT;
1187
1188         while (value != lsedrv) {
1189                 if (value > lsedrv)
1190                         value--;
1191                 else
1192                         value++;
1193
1194                 clrsetbits_le32(rcc + RCC_BDCR,
1195                                 RCC_BDCR_LSEDRV_MASK,
1196                                 value << RCC_BDCR_LSEDRV_SHIFT);
1197         }
1198
1199         stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON);
1200 }
1201
1202 static void stm32mp1_lse_wait(fdt_addr_t rcc)
1203 {
1204         stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY);
1205 }
1206
1207 static void stm32mp1_lsi_set(fdt_addr_t rcc, int enable)
1208 {
1209         stm32mp1_ls_osc_set(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSION);
1210         stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY);
1211 }
1212
1213 static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int css)
1214 {
1215         if (bypass)
1216                 setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_HSEBYP);
1217
1218         stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON);
1219         stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY);
1220
1221         if (css)
1222                 setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_HSECSSON);
1223 }
1224
1225 static void stm32mp1_csi_set(fdt_addr_t rcc, int enable)
1226 {
1227         stm32mp1_ls_osc_set(enable, rcc, RCC_OCENSETR, RCC_OCENR_CSION);
1228         stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY);
1229 }
1230
1231 static void stm32mp1_hsi_set(fdt_addr_t rcc, int enable)
1232 {
1233         stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_HSION);
1234         stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_HSIRDY);
1235 }
1236
1237 static int stm32mp1_set_hsidiv(fdt_addr_t rcc, u8 hsidiv)
1238 {
1239         u32 address = rcc + RCC_OCRDYR;
1240         u32 val;
1241         int ret;
1242
1243         clrsetbits_le32(rcc + RCC_HSICFGR,
1244                         RCC_HSICFGR_HSIDIV_MASK,
1245                         RCC_HSICFGR_HSIDIV_MASK & hsidiv);
1246
1247         ret = readl_poll_timeout(address, val,
1248                                  val & RCC_OCRDYR_HSIDIVRDY,
1249                                  TIMEOUT_200MS);
1250         if (ret)
1251                 pr_err("HSIDIV failed @ 0x%x: 0x%x\n",
1252                        address, readl(address));
1253
1254         return ret;
1255 }
1256
1257 static int stm32mp1_hsidiv(fdt_addr_t rcc, ulong hsifreq)
1258 {
1259         u8 hsidiv;
1260         u32 hsidivfreq = MAX_HSI_HZ;
1261
1262         for (hsidiv = 0; hsidiv < 4; hsidiv++,
1263              hsidivfreq = hsidivfreq / 2)
1264                 if (hsidivfreq == hsifreq)
1265                         break;
1266
1267         if (hsidiv == 4) {
1268                 pr_err("clk-hsi frequency invalid");
1269                 return -1;
1270         }
1271
1272         if (hsidiv > 0)
1273                 return stm32mp1_set_hsidiv(rcc, hsidiv);
1274
1275         return 0;
1276 }
1277
1278 static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id)
1279 {
1280         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1281
1282         writel(RCC_PLLNCR_PLLON, priv->base + pll[pll_id].pllxcr);
1283 }
1284
1285 static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output)
1286 {
1287         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1288         u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1289         u32 val;
1290         int ret;
1291
1292         ret = readl_poll_timeout(pllxcr, val, val & RCC_PLLNCR_PLLRDY,
1293                                  TIMEOUT_200MS);
1294
1295         if (ret) {
1296                 pr_err("PLL%d start failed @ 0x%x: 0x%x\n",
1297                        pll_id, pllxcr, readl(pllxcr));
1298                 return ret;
1299         }
1300
1301         /* start the requested output */
1302         setbits_le32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT);
1303
1304         return 0;
1305 }
1306
1307 static int pll_stop(struct stm32mp1_clk_priv *priv, int pll_id)
1308 {
1309         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1310         u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1311         u32 val;
1312
1313         /* stop all output */
1314         clrbits_le32(pllxcr,
1315                      RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN);
1316
1317         /* stop PLL */
1318         clrbits_le32(pllxcr, RCC_PLLNCR_PLLON);
1319
1320         /* wait PLL stopped */
1321         return readl_poll_timeout(pllxcr, val, (val & RCC_PLLNCR_PLLRDY) == 0,
1322                                   TIMEOUT_200MS);
1323 }
1324
1325 static void pll_config_output(struct stm32mp1_clk_priv *priv,
1326                               int pll_id, u32 *pllcfg)
1327 {
1328         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1329         fdt_addr_t rcc = priv->base;
1330         u32 value;
1331
1332         value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT)
1333                 & RCC_PLLNCFGR2_DIVP_MASK;
1334         value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT)
1335                  & RCC_PLLNCFGR2_DIVQ_MASK;
1336         value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT)
1337                  & RCC_PLLNCFGR2_DIVR_MASK;
1338         writel(value, rcc + pll[pll_id].pllxcfgr2);
1339 }
1340
1341 static int pll_config(struct stm32mp1_clk_priv *priv, int pll_id,
1342                       u32 *pllcfg, u32 fracv)
1343 {
1344         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1345         fdt_addr_t rcc = priv->base;
1346         enum stm32mp1_plltype type = pll[pll_id].plltype;
1347         int src;
1348         ulong refclk;
1349         u8 ifrge = 0;
1350         u32 value;
1351
1352         src = readl(priv->base + pll[pll_id].rckxselr) & RCC_SELR_SRC_MASK;
1353
1354         refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]) /
1355                  (pllcfg[PLLCFG_M] + 1);
1356
1357         if (refclk < (stm32mp1_pll[type].refclk_min * 1000000) ||
1358             refclk > (stm32mp1_pll[type].refclk_max * 1000000)) {
1359                 debug("invalid refclk = %x\n", (u32)refclk);
1360                 return -EINVAL;
1361         }
1362         if (type == PLL_800 && refclk >= 8000000)
1363                 ifrge = 1;
1364
1365         value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT)
1366                  & RCC_PLLNCFGR1_DIVN_MASK;
1367         value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT)
1368                  & RCC_PLLNCFGR1_DIVM_MASK;
1369         value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT)
1370                  & RCC_PLLNCFGR1_IFRGE_MASK;
1371         writel(value, rcc + pll[pll_id].pllxcfgr1);
1372
1373         /* fractional configuration: load sigma-delta modulator (SDM) */
1374
1375         /* Write into FRACV the new fractional value , and FRACLE to 0 */
1376         writel(fracv << RCC_PLLNFRACR_FRACV_SHIFT,
1377                rcc + pll[pll_id].pllxfracr);
1378
1379         /* Write FRACLE to 1 : FRACV value is loaded into the SDM */
1380         setbits_le32(rcc + pll[pll_id].pllxfracr,
1381                      RCC_PLLNFRACR_FRACLE);
1382
1383         pll_config_output(priv, pll_id, pllcfg);
1384
1385         return 0;
1386 }
1387
1388 static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg)
1389 {
1390         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1391         u32 pllxcsg;
1392
1393         pllxcsg = ((csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) &
1394                     RCC_PLLNCSGR_MOD_PER_MASK) |
1395                   ((csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) &
1396                     RCC_PLLNCSGR_INC_STEP_MASK) |
1397                   ((csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) &
1398                     RCC_PLLNCSGR_SSCG_MODE_MASK);
1399
1400         writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr);
1401 }
1402
1403 static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc)
1404 {
1405         u32 address = priv->base + (clksrc >> 4);
1406         u32 val;
1407         int ret;
1408
1409         clrsetbits_le32(address, RCC_SELR_SRC_MASK, clksrc & RCC_SELR_SRC_MASK);
1410         ret = readl_poll_timeout(address, val, val & RCC_SELR_SRCRDY,
1411                                  TIMEOUT_200MS);
1412         if (ret)
1413                 pr_err("CLKSRC %x start failed @ 0x%x: 0x%x\n",
1414                        clksrc, address, readl(address));
1415
1416         return ret;
1417 }
1418
1419 static void stgen_config(struct stm32mp1_clk_priv *priv)
1420 {
1421         int p;
1422         u32 stgenc, cntfid0;
1423         ulong rate;
1424
1425         stgenc = (u32)syscon_get_first_range(STM32MP_SYSCON_STGEN);
1426
1427         cntfid0 = readl(stgenc + STGENC_CNTFID0);
1428         p = stm32mp1_clk_get_parent(priv, STGEN_K);
1429         rate = stm32mp1_clk_get(priv, p);
1430
1431         if (cntfid0 != rate) {
1432                 pr_debug("System Generic Counter (STGEN) update\n");
1433                 clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1434                 writel(0x0, stgenc + STGENC_CNTCVL);
1435                 writel(0x0, stgenc + STGENC_CNTCVU);
1436                 writel(rate, stgenc + STGENC_CNTFID0);
1437                 setbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1438
1439                 __asm__ volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (rate));
1440
1441                 /* need to update gd->arch.timer_rate_hz with new frequency */
1442                 timer_init();
1443                 pr_debug("gd->arch.timer_rate_hz = %x\n",
1444                          (u32)gd->arch.timer_rate_hz);
1445                 pr_debug("Tick = %x\n", (u32)(get_ticks()));
1446         }
1447 }
1448
1449 static int set_clkdiv(unsigned int clkdiv, u32 address)
1450 {
1451         u32 val;
1452         int ret;
1453
1454         clrsetbits_le32(address, RCC_DIVR_DIV_MASK, clkdiv & RCC_DIVR_DIV_MASK);
1455         ret = readl_poll_timeout(address, val, val & RCC_DIVR_DIVRDY,
1456                                  TIMEOUT_200MS);
1457         if (ret)
1458                 pr_err("CLKDIV %x start failed @ 0x%x: 0x%x\n",
1459                        clkdiv, address, readl(address));
1460
1461         return ret;
1462 }
1463
1464 static void stm32mp1_mco_csg(struct stm32mp1_clk_priv *priv,
1465                              u32 clksrc, u32 clkdiv)
1466 {
1467         u32 address = priv->base + (clksrc >> 4);
1468
1469         /*
1470          * binding clksrc : bit15-4 offset
1471          *                  bit3:   disable
1472          *                  bit2-0: MCOSEL[2:0]
1473          */
1474         if (clksrc & 0x8) {
1475                 clrbits_le32(address, RCC_MCOCFG_MCOON);
1476         } else {
1477                 clrsetbits_le32(address,
1478                                 RCC_MCOCFG_MCOSRC_MASK,
1479                                 clksrc & RCC_MCOCFG_MCOSRC_MASK);
1480                 clrsetbits_le32(address,
1481                                 RCC_MCOCFG_MCODIV_MASK,
1482                                 clkdiv << RCC_MCOCFG_MCODIV_SHIFT);
1483                 setbits_le32(address, RCC_MCOCFG_MCOON);
1484         }
1485 }
1486
1487 static void set_rtcsrc(struct stm32mp1_clk_priv *priv,
1488                        unsigned int clksrc,
1489                        int lse_css)
1490 {
1491         u32 address = priv->base + RCC_BDCR;
1492
1493         if (readl(address) & RCC_BDCR_RTCCKEN)
1494                 goto skip_rtc;
1495
1496         if (clksrc == CLK_RTC_DISABLED)
1497                 goto skip_rtc;
1498
1499         clrsetbits_le32(address,
1500                         RCC_BDCR_RTCSRC_MASK,
1501                         clksrc << RCC_BDCR_RTCSRC_SHIFT);
1502
1503         setbits_le32(address, RCC_BDCR_RTCCKEN);
1504
1505 skip_rtc:
1506         if (lse_css)
1507                 setbits_le32(address, RCC_BDCR_LSECSSON);
1508 }
1509
1510 static void pkcs_config(struct stm32mp1_clk_priv *priv, u32 pkcs)
1511 {
1512         u32 address = priv->base + ((pkcs >> 4) & 0xFFF);
1513         u32 value = pkcs & 0xF;
1514         u32 mask = 0xF;
1515
1516         if (pkcs & BIT(31)) {
1517                 mask <<= 4;
1518                 value <<= 4;
1519         }
1520         clrsetbits_le32(address, mask, value);
1521 }
1522
1523 static int stm32mp1_clktree(struct udevice *dev)
1524 {
1525         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1526         fdt_addr_t rcc = priv->base;
1527         unsigned int clksrc[CLKSRC_NB];
1528         unsigned int clkdiv[CLKDIV_NB];
1529         unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
1530         ofnode plloff[_PLL_NB];
1531         int ret;
1532         int i, len;
1533         int lse_css = 0;
1534         const u32 *pkcs_cell;
1535
1536         /* check mandatory field */
1537         ret = dev_read_u32_array(dev, "st,clksrc", clksrc, CLKSRC_NB);
1538         if (ret < 0) {
1539                 debug("field st,clksrc invalid: error %d\n", ret);
1540                 return -FDT_ERR_NOTFOUND;
1541         }
1542
1543         ret = dev_read_u32_array(dev, "st,clkdiv", clkdiv, CLKDIV_NB);
1544         if (ret < 0) {
1545                 debug("field st,clkdiv invalid: error %d\n", ret);
1546                 return -FDT_ERR_NOTFOUND;
1547         }
1548
1549         /* check mandatory field in each pll */
1550         for (i = 0; i < _PLL_NB; i++) {
1551                 char name[12];
1552
1553                 sprintf(name, "st,pll@%d", i);
1554                 plloff[i] = dev_read_subnode(dev, name);
1555                 if (!ofnode_valid(plloff[i]))
1556                         continue;
1557                 ret = ofnode_read_u32_array(plloff[i], "cfg",
1558                                             pllcfg[i], PLLCFG_NB);
1559                 if (ret < 0) {
1560                         debug("field cfg invalid: error %d\n", ret);
1561                         return -FDT_ERR_NOTFOUND;
1562                 }
1563         }
1564
1565         debug("configuration MCO\n");
1566         stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]);
1567         stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]);
1568
1569         debug("switch ON osillator\n");
1570         /*
1571          * switch ON oscillator found in device-tree,
1572          * HSI already ON after bootrom
1573          */
1574         if (priv->osc[_LSI])
1575                 stm32mp1_lsi_set(rcc, 1);
1576
1577         if (priv->osc[_LSE]) {
1578                 int bypass;
1579                 int lsedrv;
1580                 struct udevice *dev = priv->osc_dev[_LSE];
1581
1582                 bypass = dev_read_bool(dev, "st,bypass");
1583                 lse_css = dev_read_bool(dev, "st,css");
1584                 lsedrv = dev_read_u32_default(dev, "st,drive",
1585                                               LSEDRV_MEDIUM_HIGH);
1586
1587                 stm32mp1_lse_enable(rcc, bypass, lsedrv);
1588         }
1589
1590         if (priv->osc[_HSE]) {
1591                 int bypass, css;
1592                 struct udevice *dev = priv->osc_dev[_HSE];
1593
1594                 bypass = dev_read_bool(dev, "st,bypass");
1595                 css = dev_read_bool(dev, "st,css");
1596
1597                 stm32mp1_hse_enable(rcc, bypass, css);
1598         }
1599         /* CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR)
1600          * => switch on CSI even if node is not present in device tree
1601          */
1602         stm32mp1_csi_set(rcc, 1);
1603
1604         /* come back to HSI */
1605         debug("come back to HSI\n");
1606         set_clksrc(priv, CLK_MPU_HSI);
1607         set_clksrc(priv, CLK_AXI_HSI);
1608         set_clksrc(priv, CLK_MCU_HSI);
1609
1610         debug("pll stop\n");
1611         for (i = 0; i < _PLL_NB; i++)
1612                 pll_stop(priv, i);
1613
1614         /* configure HSIDIV */
1615         debug("configure HSIDIV\n");
1616         if (priv->osc[_HSI]) {
1617                 stm32mp1_hsidiv(rcc, priv->osc[_HSI]);
1618                 stgen_config(priv);
1619         }
1620
1621         /* select DIV */
1622         debug("select DIV\n");
1623         /* no ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */
1624         writel(clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK, rcc + RCC_MPCKDIVR);
1625         set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR);
1626         set_clkdiv(clkdiv[CLKDIV_APB4], rcc + RCC_APB4DIVR);
1627         set_clkdiv(clkdiv[CLKDIV_APB5], rcc + RCC_APB5DIVR);
1628         set_clkdiv(clkdiv[CLKDIV_MCU], rcc + RCC_MCUDIVR);
1629         set_clkdiv(clkdiv[CLKDIV_APB1], rcc + RCC_APB1DIVR);
1630         set_clkdiv(clkdiv[CLKDIV_APB2], rcc + RCC_APB2DIVR);
1631         set_clkdiv(clkdiv[CLKDIV_APB3], rcc + RCC_APB3DIVR);
1632
1633         /* no ready bit for RTC */
1634         writel(clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK, rcc + RCC_RTCDIVR);
1635
1636         /* configure PLLs source */
1637         debug("configure PLLs source\n");
1638         set_clksrc(priv, clksrc[CLKSRC_PLL12]);
1639         set_clksrc(priv, clksrc[CLKSRC_PLL3]);
1640         set_clksrc(priv, clksrc[CLKSRC_PLL4]);
1641
1642         /* configure and start PLLs */
1643         debug("configure PLLs\n");
1644         for (i = 0; i < _PLL_NB; i++) {
1645                 u32 fracv;
1646                 u32 csg[PLLCSG_NB];
1647
1648                 debug("configure PLL %d @ %d\n", i,
1649                       ofnode_to_offset(plloff[i]));
1650                 if (!ofnode_valid(plloff[i]))
1651                         continue;
1652
1653                 fracv = ofnode_read_u32_default(plloff[i], "frac", 0);
1654                 pll_config(priv, i, pllcfg[i], fracv);
1655                 ret = ofnode_read_u32_array(plloff[i], "csg", csg, PLLCSG_NB);
1656                 if (!ret) {
1657                         pll_csg(priv, i, csg);
1658                 } else if (ret != -FDT_ERR_NOTFOUND) {
1659                         debug("invalid csg node for pll@%d res=%d\n", i, ret);
1660                         return ret;
1661                 }
1662                 pll_start(priv, i);
1663         }
1664
1665         /* wait and start PLLs ouptut when ready */
1666         for (i = 0; i < _PLL_NB; i++) {
1667                 if (!ofnode_valid(plloff[i]))
1668                         continue;
1669                 debug("output PLL %d\n", i);
1670                 pll_output(priv, i, pllcfg[i][PLLCFG_O]);
1671         }
1672
1673         /* wait LSE ready before to use it */
1674         if (priv->osc[_LSE])
1675                 stm32mp1_lse_wait(rcc);
1676
1677         /* configure with expected clock source */
1678         debug("CLKSRC\n");
1679         set_clksrc(priv, clksrc[CLKSRC_MPU]);
1680         set_clksrc(priv, clksrc[CLKSRC_AXI]);
1681         set_clksrc(priv, clksrc[CLKSRC_MCU]);
1682         set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css);
1683
1684         /* configure PKCK */
1685         debug("PKCK\n");
1686         pkcs_cell = dev_read_prop(dev, "st,pkcs", &len);
1687         if (pkcs_cell) {
1688                 bool ckper_disabled = false;
1689
1690                 for (i = 0; i < len / sizeof(u32); i++) {
1691                         u32 pkcs = (u32)fdt32_to_cpu(pkcs_cell[i]);
1692
1693                         if (pkcs == CLK_CKPER_DISABLED) {
1694                                 ckper_disabled = true;
1695                                 continue;
1696                         }
1697                         pkcs_config(priv, pkcs);
1698                 }
1699                 /* CKPER is source for some peripheral clock
1700                  * (FMC-NAND / QPSI-NOR) and switching source is allowed
1701                  * only if previous clock is still ON
1702                  * => deactivated CKPER only after switching clock
1703                  */
1704                 if (ckper_disabled)
1705                         pkcs_config(priv, CLK_CKPER_DISABLED);
1706         }
1707
1708         /* STGEN clock source can change with CLK_STGEN_XXX */
1709         stgen_config(priv);
1710
1711         debug("oscillator off\n");
1712         /* switch OFF HSI if not found in device-tree */
1713         if (!priv->osc[_HSI])
1714                 stm32mp1_hsi_set(rcc, 0);
1715
1716         /* Software Self-Refresh mode (SSR) during DDR initilialization */
1717         clrsetbits_le32(priv->base + RCC_DDRITFCR,
1718                         RCC_DDRITFCR_DDRCKMOD_MASK,
1719                         RCC_DDRITFCR_DDRCKMOD_SSR <<
1720                         RCC_DDRITFCR_DDRCKMOD_SHIFT);
1721
1722         return 0;
1723 }
1724 #endif /* STM32MP1_CLOCK_TREE_INIT */
1725
1726 static void stm32mp1_osc_clk_init(const char *name,
1727                                   struct stm32mp1_clk_priv *priv,
1728                                   int index)
1729 {
1730         struct clk clk;
1731         struct udevice *dev = NULL;
1732
1733         priv->osc[index] = 0;
1734         clk.id = 0;
1735         if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) {
1736                 if (clk_request(dev, &clk))
1737                         pr_err("%s request", name);
1738                 else
1739                         priv->osc[index] = clk_get_rate(&clk);
1740         }
1741         priv->osc_dev[index] = dev;
1742 }
1743
1744 static void stm32mp1_osc_init(struct udevice *dev)
1745 {
1746         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1747         int i;
1748         const char *name[NB_OSC] = {
1749                 [_LSI] = "clk-lsi",
1750                 [_LSE] = "clk-lse",
1751                 [_HSI] = "clk-hsi",
1752                 [_HSE] = "clk-hse",
1753                 [_CSI] = "clk-csi",
1754                 [_I2S_CKIN] = "i2s_ckin",
1755                 [_USB_PHY_48] = "ck_usbo_48m"};
1756
1757         for (i = 0; i < NB_OSC; i++) {
1758                 stm32mp1_osc_clk_init(name[i], priv, i);
1759                 debug("%d: %s => %x\n", i, name[i], (u32)priv->osc[i]);
1760         }
1761 }
1762
1763 static int stm32mp1_clk_probe(struct udevice *dev)
1764 {
1765         int result = 0;
1766         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1767
1768         priv->base = dev_read_addr(dev->parent);
1769         if (priv->base == FDT_ADDR_T_NONE)
1770                 return -EINVAL;
1771
1772         priv->data = (void *)&stm32mp1_data;
1773
1774         if (!priv->data->gate || !priv->data->sel ||
1775             !priv->data->pll)
1776                 return -EINVAL;
1777
1778         stm32mp1_osc_init(dev);
1779
1780 #ifdef STM32MP1_CLOCK_TREE_INIT
1781         /* clock tree init is done only one time, before relocation */
1782         if (!(gd->flags & GD_FLG_RELOC))
1783                 result = stm32mp1_clktree(dev);
1784 #endif
1785
1786         return result;
1787 }
1788
1789 static const struct clk_ops stm32mp1_clk_ops = {
1790         .enable = stm32mp1_clk_enable,
1791         .disable = stm32mp1_clk_disable,
1792         .get_rate = stm32mp1_clk_get_rate,
1793 };
1794
1795 U_BOOT_DRIVER(stm32mp1_clock) = {
1796         .name = "stm32mp1_clk",
1797         .id = UCLASS_CLK,
1798         .ops = &stm32mp1_clk_ops,
1799         .priv_auto_alloc_size = sizeof(struct stm32mp1_clk_priv),
1800         .probe = stm32mp1_clk_probe,
1801 };