drivers/clk/clk_stm32mp1.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   4  */
   5
   6 #include <common.h>
   7 #include <clk-uclass.h>
   8 #include <div64.h>
   9 #include <dm.h>
  10 #include <regmap.h>
  11 #include <spl.h>
  12 #include <syscon.h>
  13 #include <linux/io.h>
  14 #include <linux/iopoll.h>
  15 #include <dt-bindings/clock/stm32mp1-clks.h>
  16 #include <dt-bindings/clock/stm32mp1-clksrc.h>
  17
  18 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
  19 /* activate clock tree initialization in the driver */
  20 #define STM32MP1_CLOCK_TREE_INIT
  21 #endif
  22
  23 #define MAX_HSI_HZ              64000000
  24
  25 /* TIMEOUT */
  26 #define TIMEOUT_200MS           200000
  27 #define TIMEOUT_1S              1000000
  28
  29 /* STGEN registers */
  30 #define STGENC_CNTCR            0x00
  31 #define STGENC_CNTSR            0x04
  32 #define STGENC_CNTCVL           0x08
  33 #define STGENC_CNTCVU           0x0C
  34 #define STGENC_CNTFID0          0x20
  35
  36 #define STGENC_CNTCR_EN         BIT(0)
  37
  38 /* RCC registers */
  39 #define RCC_OCENSETR            0x0C
  40 #define RCC_OCENCLRR            0x10
  41 #define RCC_HSICFGR             0x18
  42 #define RCC_MPCKSELR            0x20
  43 #define RCC_ASSCKSELR           0x24
  44 #define RCC_RCK12SELR           0x28
  45 #define RCC_MPCKDIVR            0x2C
  46 #define RCC_AXIDIVR             0x30
  47 #define RCC_APB4DIVR            0x3C
  48 #define RCC_APB5DIVR            0x40
  49 #define RCC_RTCDIVR             0x44
  50 #define RCC_MSSCKSELR           0x48
  51 #define RCC_PLL1CR              0x80
  52 #define RCC_PLL1CFGR1           0x84
  53 #define RCC_PLL1CFGR2           0x88
  54 #define RCC_PLL1FRACR           0x8C
  55 #define RCC_PLL1CSGR            0x90
  56 #define RCC_PLL2CR              0x94
  57 #define RCC_PLL2CFGR1           0x98
  58 #define RCC_PLL2CFGR2           0x9C
  59 #define RCC_PLL2FRACR           0xA0
  60 #define RCC_PLL2CSGR            0xA4
  61 #define RCC_I2C46CKSELR         0xC0
  62 #define RCC_CPERCKSELR          0xD0
  63 #define RCC_STGENCKSELR         0xD4
  64 #define RCC_DDRITFCR            0xD8
  65 #define RCC_BDCR                0x140
  66 #define RCC_RDLSICR             0x144
  67 #define RCC_MP_APB4ENSETR       0x200
  68 #define RCC_MP_APB5ENSETR       0x208
  69 #define RCC_MP_AHB5ENSETR       0x210
  70 #define RCC_MP_AHB6ENSETR       0x218
  71 #define RCC_OCRDYR              0x808
  72 #define RCC_DBGCFGR             0x80C
  73 #define RCC_RCK3SELR            0x820
  74 #define RCC_RCK4SELR            0x824
  75 #define RCC_MCUDIVR             0x830
  76 #define RCC_APB1DIVR            0x834
  77 #define RCC_APB2DIVR            0x838
  78 #define RCC_APB3DIVR            0x83C
  79 #define RCC_PLL3CR              0x880
  80 #define RCC_PLL3CFGR1           0x884
  81 #define RCC_PLL3CFGR2           0x888
  82 #define RCC_PLL3FRACR           0x88C
  83 #define RCC_PLL3CSGR            0x890
  84 #define RCC_PLL4CR              0x894
  85 #define RCC_PLL4CFGR1           0x898
  86 #define RCC_PLL4CFGR2           0x89C
  87 #define RCC_PLL4FRACR           0x8A0
  88 #define RCC_PLL4CSGR            0x8A4
  89 #define RCC_I2C12CKSELR         0x8C0
  90 #define RCC_I2C35CKSELR         0x8C4
  91 #define RCC_UART6CKSELR         0x8E4
  92 #define RCC_UART24CKSELR        0x8E8
  93 #define RCC_UART35CKSELR        0x8EC
  94 #define RCC_UART78CKSELR        0x8F0
  95 #define RCC_SDMMC12CKSELR       0x8F4
  96 #define RCC_SDMMC3CKSELR        0x8F8
  97 #define RCC_ETHCKSELR           0x8FC
  98 #define RCC_QSPICKSELR          0x900
  99 #define RCC_FMCCKSELR           0x904
 100 #define RCC_USBCKSELR           0x91C
 101 #define RCC_DSICKSELR           0x924
 102 #define RCC_MP_APB1ENSETR       0xA00
 103 #define RCC_MP_APB2ENSETR       0XA08
 104 #define RCC_MP_APB3ENSETR       0xA10
 105 #define RCC_MP_AHB2ENSETR       0xA18
 106 #define RCC_MP_AHB4ENSETR       0xA28
 107
 108 /* used for most of SELR register */
 109 #define RCC_SELR_SRC_MASK       GENMASK(2, 0)
 110 #define RCC_SELR_SRCRDY         BIT(31)
 111
 112 /* Values of RCC_MPCKSELR register */
 113 #define RCC_MPCKSELR_HSI        0
 114 #define RCC_MPCKSELR_HSE        1
 115 #define RCC_MPCKSELR_PLL        2
 116 #define RCC_MPCKSELR_PLL_MPUDIV 3
 117
 118 /* Values of RCC_ASSCKSELR register */
 119 #define RCC_ASSCKSELR_HSI       0
 120 #define RCC_ASSCKSELR_HSE       1
 121 #define RCC_ASSCKSELR_PLL       2
 122
 123 /* Values of RCC_MSSCKSELR register */
 124 #define RCC_MSSCKSELR_HSI       0
 125 #define RCC_MSSCKSELR_HSE       1
 126 #define RCC_MSSCKSELR_CSI       2
 127 #define RCC_MSSCKSELR_PLL       3
 128
 129 /* Values of RCC_CPERCKSELR register */
 130 #define RCC_CPERCKSELR_HSI      0
 131 #define RCC_CPERCKSELR_CSI      1
 132 #define RCC_CPERCKSELR_HSE      2
 133
 134 /* used for most of DIVR register : max div for RTC */
 135 #define RCC_DIVR_DIV_MASK       GENMASK(5, 0)
 136 #define RCC_DIVR_DIVRDY         BIT(31)
 137
 138 /* Masks for specific DIVR registers */
 139 #define RCC_APBXDIV_MASK        GENMASK(2, 0)
 140 #define RCC_MPUDIV_MASK         GENMASK(2, 0)
 141 #define RCC_AXIDIV_MASK         GENMASK(2, 0)
 142 #define RCC_MCUDIV_MASK         GENMASK(3, 0)
 143
 144 /*  offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
 145 #define RCC_MP_ENCLRR_OFFSET    4
 146
 147 /* Fields of RCC_BDCR register */
 148 #define RCC_BDCR_LSEON          BIT(0)
 149 #define RCC_BDCR_LSEBYP         BIT(1)
 150 #define RCC_BDCR_LSERDY         BIT(2)
 151 #define RCC_BDCR_LSEDRV_MASK    GENMASK(5, 4)
 152 #define RCC_BDCR_LSEDRV_SHIFT   4
 153 #define RCC_BDCR_LSECSSON       BIT(8)
 154 #define RCC_BDCR_RTCCKEN        BIT(20)
 155 #define RCC_BDCR_RTCSRC_MASK    GENMASK(17, 16)
 156 #define RCC_BDCR_RTCSRC_SHIFT   16
 157
 158 /* Fields of RCC_RDLSICR register */
 159 #define RCC_RDLSICR_LSION       BIT(0)
 160 #define RCC_RDLSICR_LSIRDY      BIT(1)
 161
 162 /* used for ALL PLLNCR registers */
 163 #define RCC_PLLNCR_PLLON        BIT(0)
 164 #define RCC_PLLNCR_PLLRDY       BIT(1)
 165 #define RCC_PLLNCR_DIVPEN       BIT(4)
 166 #define RCC_PLLNCR_DIVQEN       BIT(5)
 167 #define RCC_PLLNCR_DIVREN       BIT(6)
 168 #define RCC_PLLNCR_DIVEN_SHIFT  4
 169
 170 /* used for ALL PLLNCFGR1 registers */
 171 #define RCC_PLLNCFGR1_DIVM_SHIFT        16
 172 #define RCC_PLLNCFGR1_DIVM_MASK         GENMASK(21, 16)
 173 #define RCC_PLLNCFGR1_DIVN_SHIFT        0
 174 #define RCC_PLLNCFGR1_DIVN_MASK         GENMASK(8, 0)
 175 /* only for PLL3 and PLL4 */
 176 #define RCC_PLLNCFGR1_IFRGE_SHIFT       24
 177 #define RCC_PLLNCFGR1_IFRGE_MASK        GENMASK(25, 24)
 178
 179 /* used for ALL PLLNCFGR2 registers , using stm32mp1_div_id */
 180 #define RCC_PLLNCFGR2_SHIFT(div_id)     ((div_id) * 8)
 181 #define RCC_PLLNCFGR2_DIVX_MASK         GENMASK(6, 0)
 182 #define RCC_PLLNCFGR2_DIVP_SHIFT        RCC_PLLNCFGR2_SHIFT(_DIV_P)
 183 #define RCC_PLLNCFGR2_DIVP_MASK         GENMASK(6, 0)
 184 #define RCC_PLLNCFGR2_DIVQ_SHIFT        RCC_PLLNCFGR2_SHIFT(_DIV_Q)
 185 #define RCC_PLLNCFGR2_DIVQ_MASK         GENMASK(14, 8)
 186 #define RCC_PLLNCFGR2_DIVR_SHIFT        RCC_PLLNCFGR2_SHIFT(_DIV_R)
 187 #define RCC_PLLNCFGR2_DIVR_MASK         GENMASK(22, 16)
 188
 189 /* used for ALL PLLNFRACR registers */
 190 #define RCC_PLLNFRACR_FRACV_SHIFT       3
 191 #define RCC_PLLNFRACR_FRACV_MASK        GENMASK(15, 3)
 192 #define RCC_PLLNFRACR_FRACLE            BIT(16)
 193
 194 /* used for ALL PLLNCSGR registers */
 195 #define RCC_PLLNCSGR_INC_STEP_SHIFT     16
 196 #define RCC_PLLNCSGR_INC_STEP_MASK      GENMASK(30, 16)
 197 #define RCC_PLLNCSGR_MOD_PER_SHIFT      0
 198 #define RCC_PLLNCSGR_MOD_PER_MASK       GENMASK(12, 0)
 199 #define RCC_PLLNCSGR_SSCG_MODE_SHIFT    15
 200 #define RCC_PLLNCSGR_SSCG_MODE_MASK     BIT(15)
 201
 202 /* used for RCC_OCENSETR and RCC_OCENCLRR registers */
 203 #define RCC_OCENR_HSION                 BIT(0)
 204 #define RCC_OCENR_CSION                 BIT(4)
 205 #define RCC_OCENR_HSEON                 BIT(8)
 206 #define RCC_OCENR_HSEBYP                BIT(10)
 207 #define RCC_OCENR_HSECSSON              BIT(11)
 208
 209 /* Fields of RCC_OCRDYR register */
 210 #define RCC_OCRDYR_HSIRDY               BIT(0)
 211 #define RCC_OCRDYR_HSIDIVRDY            BIT(2)
 212 #define RCC_OCRDYR_CSIRDY               BIT(4)
 213 #define RCC_OCRDYR_HSERDY               BIT(8)
 214
 215 /* Fields of DDRITFCR register */
 216 #define RCC_DDRITFCR_DDRCKMOD_MASK      GENMASK(22, 20)
 217 #define RCC_DDRITFCR_DDRCKMOD_SHIFT     20
 218 #define RCC_DDRITFCR_DDRCKMOD_SSR       0
 219
 220 /* Fields of RCC_HSICFGR register */
 221 #define RCC_HSICFGR_HSIDIV_MASK         GENMASK(1, 0)
 222
 223 /* used for MCO related operations */
 224 #define RCC_MCOCFG_MCOON                BIT(12)
 225 #define RCC_MCOCFG_MCODIV_MASK          GENMASK(7, 4)
 226 #define RCC_MCOCFG_MCODIV_SHIFT         4
 227 #define RCC_MCOCFG_MCOSRC_MASK          GENMASK(2, 0)
 228
 229 enum stm32mp1_parent_id {
 230 /*
 231  * _HSI, _HSE, _CSI, _LSI, _LSE should not be moved
 232  * they are used as index in osc[] as entry point
 233  */
 234         _HSI,
 235         _HSE,
 236         _CSI,
 237         _LSI,
 238         _LSE,
 239         _I2S_CKIN,
 240         _USB_PHY_48,
 241         NB_OSC,
 242
 243 /* other parent source */
 244         _HSI_KER = NB_OSC,
 245         _HSE_KER,
 246         _HSE_KER_DIV2,
 247         _CSI_KER,
 248         _PLL1_P,
 249         _PLL1_Q,
 250         _PLL1_R,
 251         _PLL2_P,
 252         _PLL2_Q,
 253         _PLL2_R,
 254         _PLL3_P,
 255         _PLL3_Q,
 256         _PLL3_R,
 257         _PLL4_P,
 258         _PLL4_Q,
 259         _PLL4_R,
 260         _ACLK,
 261         _PCLK1,
 262         _PCLK2,
 263         _PCLK3,
 264         _PCLK4,
 265         _PCLK5,
 266         _HCLK6,
 267         _HCLK2,
 268         _CK_PER,
 269         _CK_MPU,
 270         _CK_MCU,
 271         _DSI_PHY,
 272         _PARENT_NB,
 273         _UNKNOWN_ID = 0xff,
 274 };
 275
 276 enum stm32mp1_parent_sel {
 277         _I2C12_SEL,
 278         _I2C35_SEL,
 279         _I2C46_SEL,
 280         _UART6_SEL,
 281         _UART24_SEL,
 282         _UART35_SEL,
 283         _UART78_SEL,
 284         _SDMMC12_SEL,
 285         _SDMMC3_SEL,
 286         _ETH_SEL,
 287         _QSPI_SEL,
 288         _FMC_SEL,
 289         _USBPHY_SEL,
 290         _USBO_SEL,
 291         _STGEN_SEL,
 292         _DSI_SEL,
 293         _PARENT_SEL_NB,
 294         _UNKNOWN_SEL = 0xff,
 295 };
 296
 297 enum stm32mp1_pll_id {
 298         _PLL1,
 299         _PLL2,
 300         _PLL3,
 301         _PLL4,
 302         _PLL_NB
 303 };
 304
 305 enum stm32mp1_div_id {
 306         _DIV_P,
 307         _DIV_Q,
 308         _DIV_R,
 309         _DIV_NB,
 310 };
 311
 312 enum stm32mp1_clksrc_id {
 313         CLKSRC_MPU,
 314         CLKSRC_AXI,
 315         CLKSRC_MCU,
 316         CLKSRC_PLL12,
 317         CLKSRC_PLL3,
 318         CLKSRC_PLL4,
 319         CLKSRC_RTC,
 320         CLKSRC_MCO1,
 321         CLKSRC_MCO2,
 322         CLKSRC_NB
 323 };
 324
 325 enum stm32mp1_clkdiv_id {
 326         CLKDIV_MPU,
 327         CLKDIV_AXI,
 328         CLKDIV_MCU,
 329         CLKDIV_APB1,
 330         CLKDIV_APB2,
 331         CLKDIV_APB3,
 332         CLKDIV_APB4,
 333         CLKDIV_APB5,
 334         CLKDIV_RTC,
 335         CLKDIV_MCO1,
 336         CLKDIV_MCO2,
 337         CLKDIV_NB
 338 };
 339
 340 enum stm32mp1_pllcfg {
 341         PLLCFG_M,
 342         PLLCFG_N,
 343         PLLCFG_P,
 344         PLLCFG_Q,
 345         PLLCFG_R,
 346         PLLCFG_O,
 347         PLLCFG_NB
 348 };
 349
 350 enum stm32mp1_pllcsg {
 351         PLLCSG_MOD_PER,
 352         PLLCSG_INC_STEP,
 353         PLLCSG_SSCG_MODE,
 354         PLLCSG_NB
 355 };
 356
 357 enum stm32mp1_plltype {
 358         PLL_800,
 359         PLL_1600,
 360         PLL_TYPE_NB
 361 };
 362
 363 struct stm32mp1_pll {
 364         u8 refclk_min;
 365         u8 refclk_max;
 366         u8 divn_max;
 367 };
 368
 369 struct stm32mp1_clk_gate {
 370         u16 offset;
 371         u8 bit;
 372         u8 index;
 373         u8 set_clr;
 374         u8 sel;
 375         u8 fixed;
 376 };
 377
 378 struct stm32mp1_clk_sel {
 379         u16 offset;
 380         u8 src;
 381         u8 msk;
 382         u8 nb_parent;
 383         const u8 *parent;
 384 };
 385
 386 #define REFCLK_SIZE 4
 387 struct stm32mp1_clk_pll {
 388         enum stm32mp1_plltype plltype;
 389         u16 rckxselr;
 390         u16 pllxcfgr1;
 391         u16 pllxcfgr2;
 392         u16 pllxfracr;
 393         u16 pllxcr;
 394         u16 pllxcsgr;
 395         u8 refclk[REFCLK_SIZE];
 396 };
 397
 398 struct stm32mp1_clk_data {
 399         const struct stm32mp1_clk_gate *gate;
 400         const struct stm32mp1_clk_sel *sel;
 401         const struct stm32mp1_clk_pll *pll;
 402         const int nb_gate;
 403 };
 404
 405 struct stm32mp1_clk_priv {
 406         fdt_addr_t base;
 407         const struct stm32mp1_clk_data *data;
 408         ulong osc[NB_OSC];
 409         struct udevice *osc_dev[NB_OSC];
 410 };
 411
 412 #define STM32MP1_CLK(off, b, idx, s)            \
 413         {                                       \
 414                 .offset = (off),                \
 415                 .bit = (b),                     \
 416                 .index = (idx),                 \
 417                 .set_clr = 0,                   \
 418                 .sel = (s),                     \
 419                 .fixed = _UNKNOWN_ID,           \
 420         }
 421
 422 #define STM32MP1_CLK_F(off, b, idx, f)          \
 423         {                                       \
 424                 .offset = (off),                \
 425                 .bit = (b),                     \
 426                 .index = (idx),                 \
 427                 .set_clr = 0,                   \
 428                 .sel = _UNKNOWN_SEL,            \
 429                 .fixed = (f),                   \
 430         }
 431
 432 #define STM32MP1_CLK_SET_CLR(off, b, idx, s)    \
 433         {                                       \
 434                 .offset = (off),                \
 435                 .bit = (b),                     \
 436                 .index = (idx),                 \
 437                 .set_clr = 1,                   \
 438                 .sel = (s),                     \
 439                 .fixed = _UNKNOWN_ID,           \
 440         }
 441
 442 #define STM32MP1_CLK_SET_CLR_F(off, b, idx, f)  \
 443         {                                       \
 444                 .offset = (off),                \
 445                 .bit = (b),                     \
 446                 .index = (idx),                 \
 447                 .set_clr = 1,                   \
 448                 .sel = _UNKNOWN_SEL,            \
 449                 .fixed = (f),                   \
 450         }
 451
 452 #define STM32MP1_CLK_PARENT(idx, off, s, m, p)   \
 453         [(idx)] = {                             \
 454                 .offset = (off),                \
 455                 .src = (s),                     \
 456                 .msk = (m),                     \
 457                 .parent = (p),                  \
 458                 .nb_parent = ARRAY_SIZE((p))    \
 459         }
 460
 461 #define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, off4, off5, off6,\
 462                         p1, p2, p3, p4) \
 463         [(idx)] = {                             \
 464                 .plltype = (type),                      \
 465                 .rckxselr = (off1),             \
 466                 .pllxcfgr1 = (off2),            \
 467                 .pllxcfgr2 = (off3),            \
 468                 .pllxfracr = (off4),            \
 469                 .pllxcr = (off5),               \
 470                 .pllxcsgr = (off6),             \
 471                 .refclk[0] = (p1),              \
 472                 .refclk[1] = (p2),              \
 473                 .refclk[2] = (p3),              \
 474                 .refclk[3] = (p4),              \
 475         }
 476
 477 static const u8 stm32mp1_clks[][2] = {
 478         {CK_PER, _CK_PER},
 479         {CK_MPU, _CK_MPU},
 480         {CK_AXI, _ACLK},
 481         {CK_MCU, _CK_MCU},
 482         {CK_HSE, _HSE},
 483         {CK_CSI, _CSI},
 484         {CK_LSI, _LSI},
 485         {CK_LSE, _LSE},
 486         {CK_HSI, _HSI},
 487         {CK_HSE_DIV2, _HSE_KER_DIV2},
 488 };
 489
 490 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
 491         STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL),
 492         STM32MP1_CLK(RCC_DDRITFCR, 1, DDRC1LP, _UNKNOWN_SEL),
 493         STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL),
 494         STM32MP1_CLK(RCC_DDRITFCR, 3, DDRC2LP, _UNKNOWN_SEL),
 495         STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
 496         STM32MP1_CLK(RCC_DDRITFCR, 5, DDRPHYCLP, _UNKNOWN_SEL),
 497         STM32MP1_CLK(RCC_DDRITFCR, 6, DDRCAPB, _UNKNOWN_SEL),
 498         STM32MP1_CLK(RCC_DDRITFCR, 7, DDRCAPBLP, _UNKNOWN_SEL),
 499         STM32MP1_CLK(RCC_DDRITFCR, 8, AXIDCG, _UNKNOWN_SEL),
 500         STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL),
 501         STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL),
 502
 503         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
 504         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
 505         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
 506         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL),
 507         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL),
 508         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL),
 509         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL),
 510         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL),
 511         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL),
 512         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
 513
 514         STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
 515
 516         STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3),
 517
 518         STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 0, LTDC_PX, _PLL4_Q),
 519         STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 4, DSI_PX, _PLL4_Q),
 520         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 4, DSI_K, _DSI_SEL),
 521         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
 522         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
 523         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
 524
 525         STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
 526         STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
 527
 528         STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
 529         STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
 530
 531         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
 532         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
 533         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
 534         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL),
 535         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL),
 536         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL),
 537         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL),
 538         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL),
 539         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL),
 540         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL),
 541         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
 542
 543         STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
 544
 545         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK, _ETH_SEL),
 546         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL),
 547         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL),
 548         STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK),
 549         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
 550         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
 551         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL),
 552         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL),
 553         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL),
 554
 555         STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
 556 };
 557
 558 static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
 559 static const u8 i2c35_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
 560 static const u8 i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER};
 561 static const u8 uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
 562                                         _HSE_KER};
 563 static const u8 uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 564                                          _HSE_KER};
 565 static const u8 uart35_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 566                                          _HSE_KER};
 567 static const u8 uart78_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 568                                          _HSE_KER};
 569 static const u8 sdmmc12_parents[] = {_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER};
 570 static const u8 sdmmc3_parents[] = {_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER};
 571 static const u8 eth_parents[] = {_PLL4_P, _PLL3_Q};
 572 static const u8 qspi_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
 573 static const u8 fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
 574 static const u8 usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2};
 575 static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48};
 576 static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER};
 577 static const u8 dsi_parents[] = {_DSI_PHY, _PLL4_P};
 578
 579 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
 580         STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents),
 581         STM32MP1_CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents),
 582         STM32MP1_CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents),
 583         STM32MP1_CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents),
 584         STM32MP1_CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7,
 585                             uart24_parents),
 586         STM32MP1_CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7,
 587                             uart35_parents),
 588         STM32MP1_CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7,
 589                             uart78_parents),
 590         STM32MP1_CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7,
 591                             sdmmc12_parents),
 592         STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7,
 593                             sdmmc3_parents),
 594         STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents),
 595         STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents),
 596         STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents),
 597         STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents),
 598         STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
 599         STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
 600         STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents),
 601 };
 602
 603 #ifdef STM32MP1_CLOCK_TREE_INIT
 604 /* define characteristic of PLL according type */
 605 #define DIVN_MIN        24
 606 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
 607         [PLL_800] = {
 608                 .refclk_min = 4,
 609                 .refclk_max = 16,
 610                 .divn_max = 99,
 611                 },
 612         [PLL_1600] = {
 613                 .refclk_min = 8,
 614                 .refclk_max = 16,
 615                 .divn_max = 199,
 616                 },
 617 };
 618 #endif /* STM32MP1_CLOCK_TREE_INIT */
 619
 620 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = {
 621         STM32MP1_CLK_PLL(_PLL1, PLL_1600,
 622                          RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2,
 623                          RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR,
 624                          _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
 625         STM32MP1_CLK_PLL(_PLL2, PLL_1600,
 626                          RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2,
 627                          RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR,
 628                          _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
 629         STM32MP1_CLK_PLL(_PLL3, PLL_800,
 630                          RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2,
 631                          RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR,
 632                          _HSI, _HSE, _CSI, _UNKNOWN_ID),
 633         STM32MP1_CLK_PLL(_PLL4, PLL_800,
 634                          RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2,
 635                          RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR,
 636                          _HSI, _HSE, _CSI, _I2S_CKIN),
 637 };
 638
 639 /* Prescaler table lookups for clock computation */
 640 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */
 641 static const u8 stm32mp1_mcu_div[16] = {
 642         0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9
 643 };
 644
 645 /* div = /1 /2 /4 /8 /16 : same divider for pmu and apbx*/
 646 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div
 647 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div
 648 static const u8 stm32mp1_mpu_apbx_div[8] = {
 649         0, 1, 2, 3, 4, 4, 4, 4
 650 };
 651
 652 /* div = /1 /2 /3 /4 */
 653 static const u8 stm32mp1_axi_div[8] = {
 654         1, 2, 3, 4, 4, 4, 4, 4
 655 };
 656
 657 #ifdef DEBUG
 658 static const char * const stm32mp1_clk_parent_name[_PARENT_NB] = {
 659         [_HSI] = "HSI",
 660         [_HSE] = "HSE",
 661         [_CSI] = "CSI",
 662         [_LSI] = "LSI",
 663         [_LSE] = "LSE",
 664         [_I2S_CKIN] = "I2S_CKIN",
 665         [_HSI_KER] = "HSI_KER",
 666         [_HSE_KER] = "HSE_KER",
 667         [_HSE_KER_DIV2] = "HSE_KER_DIV2",
 668         [_CSI_KER] = "CSI_KER",
 669         [_PLL1_P] = "PLL1_P",
 670         [_PLL1_Q] = "PLL1_Q",
 671         [_PLL1_R] = "PLL1_R",
 672         [_PLL2_P] = "PLL2_P",
 673         [_PLL2_Q] = "PLL2_Q",
 674         [_PLL2_R] = "PLL2_R",
 675         [_PLL3_P] = "PLL3_P",
 676         [_PLL3_Q] = "PLL3_Q",
 677         [_PLL3_R] = "PLL3_R",
 678         [_PLL4_P] = "PLL4_P",
 679         [_PLL4_Q] = "PLL4_Q",
 680         [_PLL4_R] = "PLL4_R",
 681         [_ACLK] = "ACLK",
 682         [_PCLK1] = "PCLK1",
 683         [_PCLK2] = "PCLK2",
 684         [_PCLK3] = "PCLK3",
 685         [_PCLK4] = "PCLK4",
 686         [_PCLK5] = "PCLK5",
 687         [_HCLK6] = "KCLK6",
 688         [_HCLK2] = "HCLK2",
 689         [_CK_PER] = "CK_PER",
 690         [_CK_MPU] = "CK_MPU",
 691         [_CK_MCU] = "CK_MCU",
 692         [_USB_PHY_48] = "USB_PHY_48",
 693         [_DSI_PHY] = "DSI_PHY_PLL",
 694 };
 695
 696 static const char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
 697         [_I2C12_SEL] = "I2C12",
 698         [_I2C35_SEL] = "I2C35",
 699         [_I2C46_SEL] = "I2C46",
 700         [_UART6_SEL] = "UART6",
 701         [_UART24_SEL] = "UART24",
 702         [_UART35_SEL] = "UART35",
 703         [_UART78_SEL] = "UART78",
 704         [_SDMMC12_SEL] = "SDMMC12",
 705         [_SDMMC3_SEL] = "SDMMC3",
 706         [_ETH_SEL] = "ETH",
 707         [_QSPI_SEL] = "QSPI",
 708         [_FMC_SEL] = "FMC",
 709         [_USBPHY_SEL] = "USBPHY",
 710         [_USBO_SEL] = "USBO",
 711         [_STGEN_SEL] = "STGEN",
 712         [_DSI_SEL] = "DSI",
 713 };
 714 #endif
 715
 716 static const struct stm32mp1_clk_data stm32mp1_data = {
 717         .gate = stm32mp1_clk_gate,
 718         .sel = stm32mp1_clk_sel,
 719         .pll = stm32mp1_clk_pll,
 720         .nb_gate = ARRAY_SIZE(stm32mp1_clk_gate),
 721 };
 722
 723 static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx)
 724 {
 725         if (idx >= NB_OSC) {
 726                 debug("%s: clk id %d not found\n", __func__, idx);
 727                 return 0;
 728         }
 729
 730         debug("%s: clk id %d = %x : %ld kHz\n", __func__, idx,
 731               (u32)priv->osc[idx], priv->osc[idx] / 1000);
 732
 733         return priv->osc[idx];
 734 }
 735
 736 static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id)
 737 {
 738         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 739         int i, nb_clks = priv->data->nb_gate;
 740
 741         for (i = 0; i < nb_clks; i++) {
 742                 if (gate[i].index == id)
 743                         break;
 744         }
 745
 746         if (i == nb_clks) {
 747                 printf("%s: clk id %d not found\n", __func__, (u32)id);
 748                 return -EINVAL;
 749         }
 750
 751         return i;
 752 }
 753
 754 static int stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv,
 755                                 int i)
 756 {
 757         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 758
 759         if (gate[i].sel > _PARENT_SEL_NB) {
 760                 printf("%s: parents for clk id %d not found\n",
 761                        __func__, i);
 762                 return -EINVAL;
 763         }
 764
 765         return gate[i].sel;
 766 }
 767
 768 static int stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv *priv,
 769                                          int i)
 770 {
 771         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 772
 773         if (gate[i].fixed == _UNKNOWN_ID)
 774                 return -ENOENT;
 775
 776         return gate[i].fixed;
 777 }
 778
 779 static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv,
 780                                    unsigned long id)
 781 {
 782         const struct stm32mp1_clk_sel *sel = priv->data->sel;
 783         int i;
 784         int s, p;
 785
 786         for (i = 0; i < ARRAY_SIZE(stm32mp1_clks); i++)
 787                 if (stm32mp1_clks[i][0] == id)
 788                         return stm32mp1_clks[i][1];
 789
 790         i = stm32mp1_clk_get_id(priv, id);
 791         if (i < 0)
 792                 return i;
 793
 794         p = stm32mp1_clk_get_fixed_parent(priv, i);
 795         if (p >= 0 && p < _PARENT_NB)
 796                 return p;
 797
 798         s = stm32mp1_clk_get_sel(priv, i);
 799         if (s < 0)
 800                 return s;
 801
 802         p = (readl(priv->base + sel[s].offset) >> sel[s].src) & sel[s].msk;
 803
 804         if (p < sel[s].nb_parent) {
 805 #ifdef DEBUG
 806                 debug("%s: %s clock is the parent %s of clk id %d\n", __func__,
 807                       stm32mp1_clk_parent_name[sel[s].parent[p]],
 808                       stm32mp1_clk_parent_sel_name[s],
 809                       (u32)id);
 810 #endif
 811                 return sel[s].parent[p];
 812         }
 813
 814         pr_err("%s: no parents defined for clk id %d\n",
 815                __func__, (u32)id);
 816
 817         return -EINVAL;
 818 }
 819
 820 static ulong  pll_get_fref_ck(struct stm32mp1_clk_priv *priv,
 821                               int pll_id)
 822 {
 823         const struct stm32mp1_clk_pll *pll = priv->data->pll;
 824         u32 selr;
 825         int src;
 826         ulong refclk;
 827
 828         /* Get current refclk */
 829         selr = readl(priv->base + pll[pll_id].rckxselr);
 830         src = selr & RCC_SELR_SRC_MASK;
 831
 832         refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]);
 833         debug("PLL%d : selr=%x refclk = %d kHz\n",
 834               pll_id, selr, (u32)(refclk / 1000));
 835
 836         return refclk;
 837 }
 838
 839 /*
 840  * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL
 841  * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1)
 842  * - PLL3 & PLL4 => return VCO     with Fpll_y_ck = FVCO / (DIVy + 1)
 843  * => in all the case Fpll_y_ck = pll_get_fvco() / (DIVy + 1)
 844  */
 845 static ulong pll_get_fvco(struct stm32mp1_clk_priv *priv,
 846                           int pll_id)
 847 {
 848         const struct stm32mp1_clk_pll *pll = priv->data->pll;
 849         int divm, divn;
 850         ulong refclk, fvco;
 851         u32 cfgr1, fracr;
 852
 853         cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1);
 854         fracr = readl(priv->base + pll[pll_id].pllxfracr);
 855
 856         divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
 857         divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
 858
 859         debug("PLL%d : cfgr1=%x fracr=%x DIVN=%d DIVM=%d\n",
 860               pll_id, cfgr1, fracr, divn, divm);
 861
 862         refclk = pll_get_fref_ck(priv, pll_id);
 863
 864         /* with FRACV :
 865          *   Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1)
 866          * without FRACV
 867          *   Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1)
 868          */
 869         if (fracr & RCC_PLLNFRACR_FRACLE) {
 870                 u32 fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK)
 871                             >> RCC_PLLNFRACR_FRACV_SHIFT;
 872                 fvco = (ulong)lldiv((unsigned long long)refclk *
 873                                      (((divn + 1) << 13) + fracv),
 874                                      ((unsigned long long)(divm + 1)) << 13);
 875         } else {
 876                 fvco = (ulong)(refclk * (divn + 1) / (divm + 1));
 877         }
 878         debug("PLL%d : %s = %ld\n", pll_id, __func__, fvco);
 879
 880         return fvco;
 881 }
 882
 883 static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
 884                                     int pll_id, int div_id)
 885 {
 886         const struct stm32mp1_clk_pll *pll = priv->data->pll;
 887         int divy;
 888         ulong dfout;
 889         u32 cfgr2;
 890
 891         debug("%s(%d, %d)\n", __func__, pll_id, div_id);
 892         if (div_id >= _DIV_NB)
 893                 return 0;
 894
 895         cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2);
 896         divy = (cfgr2 >> RCC_PLLNCFGR2_SHIFT(div_id)) & RCC_PLLNCFGR2_DIVX_MASK;
 897
 898         debug("PLL%d : cfgr2=%x DIVY=%d\n", pll_id, cfgr2, divy);
 899
 900         dfout = pll_get_fvco(priv, pll_id) / (divy + 1);
 901         debug("        => dfout = %d kHz\n", (u32)(dfout / 1000));
 902
 903         return dfout;
 904 }
 905
 906 static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
 907 {
 908         u32 reg;
 909         ulong clock = 0;
 910
 911         switch (p) {
 912         case _CK_MPU:
 913         /* MPU sub system */
 914                 reg = readl(priv->base + RCC_MPCKSELR);
 915                 switch (reg & RCC_SELR_SRC_MASK) {
 916                 case RCC_MPCKSELR_HSI:
 917                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
 918                         break;
 919                 case RCC_MPCKSELR_HSE:
 920                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
 921                         break;
 922                 case RCC_MPCKSELR_PLL:
 923                 case RCC_MPCKSELR_PLL_MPUDIV:
 924                         clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P);
 925                         if (p == RCC_MPCKSELR_PLL_MPUDIV) {
 926                                 reg = readl(priv->base + RCC_MPCKDIVR);
 927                                 clock /= stm32mp1_mpu_div[reg &
 928                                                           RCC_MPUDIV_MASK];
 929                         }
 930                         break;
 931                 }
 932                 break;
 933         /* AXI sub system */
 934         case _ACLK:
 935         case _HCLK2:
 936         case _HCLK6:
 937         case _PCLK4:
 938         case _PCLK5:
 939                 reg = readl(priv->base + RCC_ASSCKSELR);
 940                 switch (reg & RCC_SELR_SRC_MASK) {
 941                 case RCC_ASSCKSELR_HSI:
 942                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
 943                         break;
 944                 case RCC_ASSCKSELR_HSE:
 945                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
 946                         break;
 947                 case RCC_ASSCKSELR_PLL:
 948                         clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P);
 949                         break;
 950                 }
 951
 952                 /* System clock divider */
 953                 reg = readl(priv->base + RCC_AXIDIVR);
 954                 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK];
 955
 956                 switch (p) {
 957                 case _PCLK4:
 958                         reg = readl(priv->base + RCC_APB4DIVR);
 959                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
 960                         break;
 961                 case _PCLK5:
 962                         reg = readl(priv->base + RCC_APB5DIVR);
 963                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
 964                         break;
 965                 default:
 966                         break;
 967                 }
 968                 break;
 969         /* MCU sub system */
 970         case _CK_MCU:
 971         case _PCLK1:
 972         case _PCLK2:
 973         case _PCLK3:
 974                 reg = readl(priv->base + RCC_MSSCKSELR);
 975                 switch (reg & RCC_SELR_SRC_MASK) {
 976                 case RCC_MSSCKSELR_HSI:
 977                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
 978                         break;
 979                 case RCC_MSSCKSELR_HSE:
 980                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
 981                         break;
 982                 case RCC_MSSCKSELR_CSI:
 983                         clock = stm32mp1_clk_get_fixed(priv, _CSI);
 984                         break;
 985                 case RCC_MSSCKSELR_PLL:
 986                         clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_P);
 987                         break;
 988                 }
 989
 990                 /* MCU clock divider */
 991                 reg = readl(priv->base + RCC_MCUDIVR);
 992                 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK];
 993
 994                 switch (p) {
 995                 case _PCLK1:
 996                         reg = readl(priv->base + RCC_APB1DIVR);
 997                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
 998                         break;
 999                 case _PCLK2:
1000                         reg = readl(priv->base + RCC_APB2DIVR);
1001                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1002                         break;
1003                 case _PCLK3:
1004                         reg = readl(priv->base + RCC_APB3DIVR);
1005                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1006                         break;
1007                 case _CK_MCU:
1008                 default:
1009                         break;
1010                 }
1011                 break;
1012         case _CK_PER:
1013                 reg = readl(priv->base + RCC_CPERCKSELR);
1014                 switch (reg & RCC_SELR_SRC_MASK) {
1015                 case RCC_CPERCKSELR_HSI:
1016                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
1017                         break;
1018                 case RCC_CPERCKSELR_HSE:
1019                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
1020                         break;
1021                 case RCC_CPERCKSELR_CSI:
1022                         clock = stm32mp1_clk_get_fixed(priv, _CSI);
1023                         break;
1024                 }
1025                 break;
1026         case _HSI:
1027         case _HSI_KER:
1028                 clock = stm32mp1_clk_get_fixed(priv, _HSI);
1029                 break;
1030         case _CSI:
1031         case _CSI_KER:
1032                 clock = stm32mp1_clk_get_fixed(priv, _CSI);
1033                 break;
1034         case _HSE:
1035         case _HSE_KER:
1036         case _HSE_KER_DIV2:
1037                 clock = stm32mp1_clk_get_fixed(priv, _HSE);
1038                 if (p == _HSE_KER_DIV2)
1039                         clock >>= 1;
1040                 break;
1041         case _LSI:
1042                 clock = stm32mp1_clk_get_fixed(priv, _LSI);
1043                 break;
1044         case _LSE:
1045                 clock = stm32mp1_clk_get_fixed(priv, _LSE);
1046                 break;
1047         /* PLL */
1048         case _PLL1_P:
1049         case _PLL1_Q:
1050         case _PLL1_R:
1051                 clock = stm32mp1_read_pll_freq(priv, _PLL1, p - _PLL1_P);
1052                 break;
1053         case _PLL2_P:
1054         case _PLL2_Q:
1055         case _PLL2_R:
1056                 clock = stm32mp1_read_pll_freq(priv, _PLL2, p - _PLL2_P);
1057                 break;
1058         case _PLL3_P:
1059         case _PLL3_Q:
1060         case _PLL3_R:
1061                 clock = stm32mp1_read_pll_freq(priv, _PLL3, p - _PLL3_P);
1062                 break;
1063         case _PLL4_P:
1064         case _PLL4_Q:
1065         case _PLL4_R:
1066                 clock = stm32mp1_read_pll_freq(priv, _PLL4, p - _PLL4_P);
1067                 break;
1068         /* other */
1069         case _USB_PHY_48:
1070                 clock = stm32mp1_clk_get_fixed(priv, _USB_PHY_48);
1071                 break;
1072         case _DSI_PHY:
1073         {
1074                 struct clk clk;
1075                 struct udevice *dev = NULL;
1076
1077                 if (!uclass_get_device_by_name(UCLASS_CLK, "ck_dsi_phy",
1078                                                &dev)) {
1079                         if (clk_request(dev, &clk)) {
1080                                 pr_err("ck_dsi_phy request");
1081                         } else {
1082                                 clk.id = 0;
1083                                 clock = clk_get_rate(&clk);
1084                         }
1085                 }
1086                 break;
1087         }
1088         default:
1089                 break;
1090         }
1091
1092         debug("%s(%d) clock = %lx : %ld kHz\n",
1093               __func__, p, clock, clock / 1000);
1094
1095         return clock;
1096 }
1097
1098 static int stm32mp1_clk_enable(struct clk *clk)
1099 {
1100         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1101         const struct stm32mp1_clk_gate *gate = priv->data->gate;
1102         int i = stm32mp1_clk_get_id(priv, clk->id);
1103
1104         if (i < 0)
1105                 return i;
1106
1107         if (gate[i].set_clr)
1108                 writel(BIT(gate[i].bit), priv->base + gate[i].offset);
1109         else
1110                 setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1111
1112         debug("%s: id clock %d has been enabled\n", __func__, (u32)clk->id);
1113
1114         return 0;
1115 }
1116
1117 static int stm32mp1_clk_disable(struct clk *clk)
1118 {
1119         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1120         const struct stm32mp1_clk_gate *gate = priv->data->gate;
1121         int i = stm32mp1_clk_get_id(priv, clk->id);
1122
1123         if (i < 0)
1124                 return i;
1125
1126         if (gate[i].set_clr)
1127                 writel(BIT(gate[i].bit),
1128                        priv->base + gate[i].offset
1129                        + RCC_MP_ENCLRR_OFFSET);
1130         else
1131                 clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1132
1133         debug("%s: id clock %d has been disabled\n", __func__, (u32)clk->id);
1134
1135         return 0;
1136 }
1137
1138 static ulong stm32mp1_clk_get_rate(struct clk *clk)
1139 {
1140         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1141         int p = stm32mp1_clk_get_parent(priv, clk->id);
1142         ulong rate;
1143
1144         if (p < 0)
1145                 return 0;
1146
1147         rate = stm32mp1_clk_get(priv, p);
1148
1149 #ifdef DEBUG
1150         debug("%s: computed rate for id clock %d is %d (parent is %s)\n",
1151               __func__, (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]);
1152 #endif
1153         return rate;
1154 }
1155
1156 #ifdef STM32MP1_CLOCK_TREE_INIT
1157 static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset,
1158                                 u32 mask_on)
1159 {
1160         u32 address = rcc + offset;
1161
1162         if (enable)
1163                 setbits_le32(address, mask_on);
1164         else
1165                 clrbits_le32(address, mask_on);
1166 }
1167
1168 static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on)
1169 {
1170         if (enable)
1171                 setbits_le32(rcc + RCC_OCENSETR, mask_on);
1172         else
1173                 setbits_le32(rcc + RCC_OCENCLRR, mask_on);
1174 }
1175
1176 static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset,
1177                              u32 mask_rdy)
1178 {
1179         u32 mask_test = 0;
1180         u32 address = rcc + offset;
1181         u32 val;
1182         int ret;
1183
1184         if (enable)
1185                 mask_test = mask_rdy;
1186
1187         ret = readl_poll_timeout(address, val,
1188                                  (val & mask_rdy) == mask_test,
1189                                  TIMEOUT_1S);
1190
1191         if (ret)
1192                 pr_err("OSC %x @ %x timeout for enable=%d : 0x%x\n",
1193                        mask_rdy, address, enable, readl(address));
1194
1195         return ret;
1196 }
1197
1198 static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int lsedrv)
1199 {
1200         u32 value;
1201
1202         if (bypass)
1203                 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP);
1204
1205         /*
1206          * warning: not recommended to switch directly from "high drive"
1207          * to "medium low drive", and vice-versa.
1208          */
1209         value = (readl(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK)
1210                 >> RCC_BDCR_LSEDRV_SHIFT;
1211
1212         while (value != lsedrv) {
1213                 if (value > lsedrv)
1214                         value--;
1215                 else
1216                         value++;
1217
1218                 clrsetbits_le32(rcc + RCC_BDCR,
1219                                 RCC_BDCR_LSEDRV_MASK,
1220                                 value << RCC_BDCR_LSEDRV_SHIFT);
1221         }
1222
1223         stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON);
1224 }
1225
1226 static void stm32mp1_lse_wait(fdt_addr_t rcc)
1227 {
1228         stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY);
1229 }
1230
1231 static void stm32mp1_lsi_set(fdt_addr_t rcc, int enable)
1232 {
1233         stm32mp1_ls_osc_set(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSION);
1234         stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY);
1235 }
1236
1237 static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int css)
1238 {
1239         if (bypass)
1240                 setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_HSEBYP);
1241
1242         stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON);
1243         stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY);
1244
1245         if (css)
1246                 setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_HSECSSON);
1247 }
1248
1249 static void stm32mp1_csi_set(fdt_addr_t rcc, int enable)
1250 {
1251         stm32mp1_ls_osc_set(enable, rcc, RCC_OCENSETR, RCC_OCENR_CSION);
1252         stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY);
1253 }
1254
1255 static void stm32mp1_hsi_set(fdt_addr_t rcc, int enable)
1256 {
1257         stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_HSION);
1258         stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_HSIRDY);
1259 }
1260
1261 static int stm32mp1_set_hsidiv(fdt_addr_t rcc, u8 hsidiv)
1262 {
1263         u32 address = rcc + RCC_OCRDYR;
1264         u32 val;
1265         int ret;
1266
1267         clrsetbits_le32(rcc + RCC_HSICFGR,
1268                         RCC_HSICFGR_HSIDIV_MASK,
1269                         RCC_HSICFGR_HSIDIV_MASK & hsidiv);
1270
1271         ret = readl_poll_timeout(address, val,
1272                                  val & RCC_OCRDYR_HSIDIVRDY,
1273                                  TIMEOUT_200MS);
1274         if (ret)
1275                 pr_err("HSIDIV failed @ 0x%x: 0x%x\n",
1276                        address, readl(address));
1277
1278         return ret;
1279 }
1280
1281 static int stm32mp1_hsidiv(fdt_addr_t rcc, ulong hsifreq)
1282 {
1283         u8 hsidiv;
1284         u32 hsidivfreq = MAX_HSI_HZ;
1285
1286         for (hsidiv = 0; hsidiv < 4; hsidiv++,
1287              hsidivfreq = hsidivfreq / 2)
1288                 if (hsidivfreq == hsifreq)
1289                         break;
1290
1291         if (hsidiv == 4) {
1292                 pr_err("clk-hsi frequency invalid");
1293                 return -1;
1294         }
1295
1296         if (hsidiv > 0)
1297                 return stm32mp1_set_hsidiv(rcc, hsidiv);
1298
1299         return 0;
1300 }
1301
1302 static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id)
1303 {
1304         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1305
1306         writel(RCC_PLLNCR_PLLON, priv->base + pll[pll_id].pllxcr);
1307 }
1308
1309 static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output)
1310 {
1311         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1312         u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1313         u32 val;
1314         int ret;
1315
1316         ret = readl_poll_timeout(pllxcr, val, val & RCC_PLLNCR_PLLRDY,
1317                                  TIMEOUT_200MS);
1318
1319         if (ret) {
1320                 pr_err("PLL%d start failed @ 0x%x: 0x%x\n",
1321                        pll_id, pllxcr, readl(pllxcr));
1322                 return ret;
1323         }
1324
1325         /* start the requested output */
1326         setbits_le32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT);
1327
1328         return 0;
1329 }
1330
1331 static int pll_stop(struct stm32mp1_clk_priv *priv, int pll_id)
1332 {
1333         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1334         u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1335         u32 val;
1336
1337         /* stop all output */
1338         clrbits_le32(pllxcr,
1339                      RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN);
1340
1341         /* stop PLL */
1342         clrbits_le32(pllxcr, RCC_PLLNCR_PLLON);
1343
1344         /* wait PLL stopped */
1345         return readl_poll_timeout(pllxcr, val, (val & RCC_PLLNCR_PLLRDY) == 0,
1346                                   TIMEOUT_200MS);
1347 }
1348
1349 static void pll_config_output(struct stm32mp1_clk_priv *priv,
1350                               int pll_id, u32 *pllcfg)
1351 {
1352         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1353         fdt_addr_t rcc = priv->base;
1354         u32 value;
1355
1356         value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT)
1357                 & RCC_PLLNCFGR2_DIVP_MASK;
1358         value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT)
1359                  & RCC_PLLNCFGR2_DIVQ_MASK;
1360         value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT)
1361                  & RCC_PLLNCFGR2_DIVR_MASK;
1362         writel(value, rcc + pll[pll_id].pllxcfgr2);
1363 }
1364
1365 static int pll_config(struct stm32mp1_clk_priv *priv, int pll_id,
1366                       u32 *pllcfg, u32 fracv)
1367 {
1368         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1369         fdt_addr_t rcc = priv->base;
1370         enum stm32mp1_plltype type = pll[pll_id].plltype;
1371         int src;
1372         ulong refclk;
1373         u8 ifrge = 0;
1374         u32 value;
1375
1376         src = readl(priv->base + pll[pll_id].rckxselr) & RCC_SELR_SRC_MASK;
1377
1378         refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]) /
1379                  (pllcfg[PLLCFG_M] + 1);
1380
1381         if (refclk < (stm32mp1_pll[type].refclk_min * 1000000) ||
1382             refclk > (stm32mp1_pll[type].refclk_max * 1000000)) {
1383                 debug("invalid refclk = %x\n", (u32)refclk);
1384                 return -EINVAL;
1385         }
1386         if (type == PLL_800 && refclk >= 8000000)
1387                 ifrge = 1;
1388
1389         value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT)
1390                  & RCC_PLLNCFGR1_DIVN_MASK;
1391         value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT)
1392                  & RCC_PLLNCFGR1_DIVM_MASK;
1393         value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT)
1394                  & RCC_PLLNCFGR1_IFRGE_MASK;
1395         writel(value, rcc + pll[pll_id].pllxcfgr1);
1396
1397         /* fractional configuration: load sigma-delta modulator (SDM) */
1398
1399         /* Write into FRACV the new fractional value , and FRACLE to 0 */
1400         writel(fracv << RCC_PLLNFRACR_FRACV_SHIFT,
1401                rcc + pll[pll_id].pllxfracr);
1402
1403         /* Write FRACLE to 1 : FRACV value is loaded into the SDM */
1404         setbits_le32(rcc + pll[pll_id].pllxfracr,
1405                      RCC_PLLNFRACR_FRACLE);
1406
1407         pll_config_output(priv, pll_id, pllcfg);
1408
1409         return 0;
1410 }
1411
1412 static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg)
1413 {
1414         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1415         u32 pllxcsg;
1416
1417         pllxcsg = ((csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) &
1418                     RCC_PLLNCSGR_MOD_PER_MASK) |
1419                   ((csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) &
1420                     RCC_PLLNCSGR_INC_STEP_MASK) |
1421                   ((csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) &
1422                     RCC_PLLNCSGR_SSCG_MODE_MASK);
1423
1424         writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr);
1425 }
1426
1427 static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc)
1428 {
1429         u32 address = priv->base + (clksrc >> 4);
1430         u32 val;
1431         int ret;
1432
1433         clrsetbits_le32(address, RCC_SELR_SRC_MASK, clksrc & RCC_SELR_SRC_MASK);
1434         ret = readl_poll_timeout(address, val, val & RCC_SELR_SRCRDY,
1435                                  TIMEOUT_200MS);
1436         if (ret)
1437                 pr_err("CLKSRC %x start failed @ 0x%x: 0x%x\n",
1438                        clksrc, address, readl(address));
1439
1440         return ret;
1441 }
1442
1443 static void stgen_config(struct stm32mp1_clk_priv *priv)
1444 {
1445         int p;
1446         u32 stgenc, cntfid0;
1447         ulong rate;
1448
1449         stgenc = (u32)syscon_get_first_range(STM32MP_SYSCON_STGEN);
1450
1451         cntfid0 = readl(stgenc + STGENC_CNTFID0);
1452         p = stm32mp1_clk_get_parent(priv, STGEN_K);
1453         rate = stm32mp1_clk_get(priv, p);
1454
1455         if (cntfid0 != rate) {
1456                 pr_debug("System Generic Counter (STGEN) update\n");
1457                 clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1458                 writel(0x0, stgenc + STGENC_CNTCVL);
1459                 writel(0x0, stgenc + STGENC_CNTCVU);
1460                 writel(rate, stgenc + STGENC_CNTFID0);
1461                 setbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1462
1463                 __asm__ volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (rate));
1464
1465                 /* need to update gd->arch.timer_rate_hz with new frequency */
1466                 timer_init();
1467                 pr_debug("gd->arch.timer_rate_hz = %x\n",
1468                          (u32)gd->arch.timer_rate_hz);
1469                 pr_debug("Tick = %x\n", (u32)(get_ticks()));
1470         }
1471 }
1472
1473 static int set_clkdiv(unsigned int clkdiv, u32 address)
1474 {
1475         u32 val;
1476         int ret;
1477
1478         clrsetbits_le32(address, RCC_DIVR_DIV_MASK, clkdiv & RCC_DIVR_DIV_MASK);
1479         ret = readl_poll_timeout(address, val, val & RCC_DIVR_DIVRDY,
1480                                  TIMEOUT_200MS);
1481         if (ret)
1482                 pr_err("CLKDIV %x start failed @ 0x%x: 0x%x\n",
1483                        clkdiv, address, readl(address));
1484
1485         return ret;
1486 }
1487
1488 static void stm32mp1_mco_csg(struct stm32mp1_clk_priv *priv,
1489                              u32 clksrc, u32 clkdiv)
1490 {
1491         u32 address = priv->base + (clksrc >> 4);
1492
1493         /*
1494          * binding clksrc : bit15-4 offset
1495          *                  bit3:   disable
1496          *                  bit2-0: MCOSEL[2:0]
1497          */
1498         if (clksrc & 0x8) {
1499                 clrbits_le32(address, RCC_MCOCFG_MCOON);
1500         } else {
1501                 clrsetbits_le32(address,
1502                                 RCC_MCOCFG_MCOSRC_MASK,
1503                                 clksrc & RCC_MCOCFG_MCOSRC_MASK);
1504                 clrsetbits_le32(address,
1505                                 RCC_MCOCFG_MCODIV_MASK,
1506                                 clkdiv << RCC_MCOCFG_MCODIV_SHIFT);
1507                 setbits_le32(address, RCC_MCOCFG_MCOON);
1508         }
1509 }
1510
1511 static void set_rtcsrc(struct stm32mp1_clk_priv *priv,
1512                        unsigned int clksrc,
1513                        int lse_css)
1514 {
1515         u32 address = priv->base + RCC_BDCR;
1516
1517         if (readl(address) & RCC_BDCR_RTCCKEN)
1518                 goto skip_rtc;
1519
1520         if (clksrc == CLK_RTC_DISABLED)
1521                 goto skip_rtc;
1522
1523         clrsetbits_le32(address,
1524                         RCC_BDCR_RTCSRC_MASK,
1525                         clksrc << RCC_BDCR_RTCSRC_SHIFT);
1526
1527         setbits_le32(address, RCC_BDCR_RTCCKEN);
1528
1529 skip_rtc:
1530         if (lse_css)
1531                 setbits_le32(address, RCC_BDCR_LSECSSON);
1532 }
1533
1534 static void pkcs_config(struct stm32mp1_clk_priv *priv, u32 pkcs)
1535 {
1536         u32 address = priv->base + ((pkcs >> 4) & 0xFFF);
1537         u32 value = pkcs & 0xF;
1538         u32 mask = 0xF;
1539
1540         if (pkcs & BIT(31)) {
1541                 mask <<= 4;
1542                 value <<= 4;
1543         }
1544         clrsetbits_le32(address, mask, value);
1545 }
1546
1547 static int stm32mp1_clktree(struct udevice *dev)
1548 {
1549         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1550         fdt_addr_t rcc = priv->base;
1551         unsigned int clksrc[CLKSRC_NB];
1552         unsigned int clkdiv[CLKDIV_NB];
1553         unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
1554         ofnode plloff[_PLL_NB];
1555         int ret;
1556         int i, len;
1557         int lse_css = 0;
1558         const u32 *pkcs_cell;
1559
1560         /* check mandatory field */
1561         ret = dev_read_u32_array(dev, "st,clksrc", clksrc, CLKSRC_NB);
1562         if (ret < 0) {
1563                 debug("field st,clksrc invalid: error %d\n", ret);
1564                 return -FDT_ERR_NOTFOUND;
1565         }
1566
1567         ret = dev_read_u32_array(dev, "st,clkdiv", clkdiv, CLKDIV_NB);
1568         if (ret < 0) {
1569                 debug("field st,clkdiv invalid: error %d\n", ret);
1570                 return -FDT_ERR_NOTFOUND;
1571         }
1572
1573         /* check mandatory field in each pll */
1574         for (i = 0; i < _PLL_NB; i++) {
1575                 char name[12];
1576
1577                 sprintf(name, "st,pll@%d", i);
1578                 plloff[i] = dev_read_subnode(dev, name);
1579                 if (!ofnode_valid(plloff[i]))
1580                         continue;
1581                 ret = ofnode_read_u32_array(plloff[i], "cfg",
1582                                             pllcfg[i], PLLCFG_NB);
1583                 if (ret < 0) {
1584                         debug("field cfg invalid: error %d\n", ret);
1585                         return -FDT_ERR_NOTFOUND;
1586                 }
1587         }
1588
1589         debug("configuration MCO\n");
1590         stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]);
1591         stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]);
1592
1593         debug("switch ON osillator\n");
1594         /*
1595          * switch ON oscillator found in device-tree,
1596          * HSI already ON after bootrom
1597          */
1598         if (priv->osc[_LSI])
1599                 stm32mp1_lsi_set(rcc, 1);
1600
1601         if (priv->osc[_LSE]) {
1602                 int bypass;
1603                 int lsedrv;
1604                 struct udevice *dev = priv->osc_dev[_LSE];
1605
1606                 bypass = dev_read_bool(dev, "st,bypass");
1607                 lse_css = dev_read_bool(dev, "st,css");
1608                 lsedrv = dev_read_u32_default(dev, "st,drive",
1609                                               LSEDRV_MEDIUM_HIGH);
1610
1611                 stm32mp1_lse_enable(rcc, bypass, lsedrv);
1612         }
1613
1614         if (priv->osc[_HSE]) {
1615                 int bypass, css;
1616                 struct udevice *dev = priv->osc_dev[_HSE];
1617
1618                 bypass = dev_read_bool(dev, "st,bypass");
1619                 css = dev_read_bool(dev, "st,css");
1620
1621                 stm32mp1_hse_enable(rcc, bypass, css);
1622         }
1623         /* CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR)
1624          * => switch on CSI even if node is not present in device tree
1625          */
1626         stm32mp1_csi_set(rcc, 1);
1627
1628         /* come back to HSI */
1629         debug("come back to HSI\n");
1630         set_clksrc(priv, CLK_MPU_HSI);
1631         set_clksrc(priv, CLK_AXI_HSI);
1632         set_clksrc(priv, CLK_MCU_HSI);
1633
1634         debug("pll stop\n");
1635         for (i = 0; i < _PLL_NB; i++)
1636                 pll_stop(priv, i);
1637
1638         /* configure HSIDIV */
1639         debug("configure HSIDIV\n");
1640         if (priv->osc[_HSI]) {
1641                 stm32mp1_hsidiv(rcc, priv->osc[_HSI]);
1642                 stgen_config(priv);
1643         }
1644
1645         /* select DIV */
1646         debug("select DIV\n");
1647         /* no ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */
1648         writel(clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK, rcc + RCC_MPCKDIVR);
1649         set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR);
1650         set_clkdiv(clkdiv[CLKDIV_APB4], rcc + RCC_APB4DIVR);
1651         set_clkdiv(clkdiv[CLKDIV_APB5], rcc + RCC_APB5DIVR);
1652         set_clkdiv(clkdiv[CLKDIV_MCU], rcc + RCC_MCUDIVR);
1653         set_clkdiv(clkdiv[CLKDIV_APB1], rcc + RCC_APB1DIVR);
1654         set_clkdiv(clkdiv[CLKDIV_APB2], rcc + RCC_APB2DIVR);
1655         set_clkdiv(clkdiv[CLKDIV_APB3], rcc + RCC_APB3DIVR);
1656
1657         /* no ready bit for RTC */
1658         writel(clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK, rcc + RCC_RTCDIVR);
1659
1660         /* configure PLLs source */
1661         debug("configure PLLs source\n");
1662         set_clksrc(priv, clksrc[CLKSRC_PLL12]);
1663         set_clksrc(priv, clksrc[CLKSRC_PLL3]);
1664         set_clksrc(priv, clksrc[CLKSRC_PLL4]);
1665
1666         /* configure and start PLLs */
1667         debug("configure PLLs\n");
1668         for (i = 0; i < _PLL_NB; i++) {
1669                 u32 fracv;
1670                 u32 csg[PLLCSG_NB];
1671
1672                 debug("configure PLL %d @ %d\n", i,
1673                       ofnode_to_offset(plloff[i]));
1674                 if (!ofnode_valid(plloff[i]))
1675                         continue;
1676
1677                 fracv = ofnode_read_u32_default(plloff[i], "frac", 0);
1678                 pll_config(priv, i, pllcfg[i], fracv);
1679                 ret = ofnode_read_u32_array(plloff[i], "csg", csg, PLLCSG_NB);
1680                 if (!ret) {
1681                         pll_csg(priv, i, csg);
1682                 } else if (ret != -FDT_ERR_NOTFOUND) {
1683                         debug("invalid csg node for pll@%d res=%d\n", i, ret);
1684                         return ret;
1685                 }
1686                 pll_start(priv, i);
1687         }
1688
1689         /* wait and start PLLs ouptut when ready */
1690         for (i = 0; i < _PLL_NB; i++) {
1691                 if (!ofnode_valid(plloff[i]))
1692                         continue;
1693                 debug("output PLL %d\n", i);
1694                 pll_output(priv, i, pllcfg[i][PLLCFG_O]);
1695         }
1696
1697         /* wait LSE ready before to use it */
1698         if (priv->osc[_LSE])
1699                 stm32mp1_lse_wait(rcc);
1700
1701         /* configure with expected clock source */
1702         debug("CLKSRC\n");
1703         set_clksrc(priv, clksrc[CLKSRC_MPU]);
1704         set_clksrc(priv, clksrc[CLKSRC_AXI]);
1705         set_clksrc(priv, clksrc[CLKSRC_MCU]);
1706         set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css);
1707
1708         /* configure PKCK */
1709         debug("PKCK\n");
1710         pkcs_cell = dev_read_prop(dev, "st,pkcs", &len);
1711         if (pkcs_cell) {
1712                 bool ckper_disabled = false;
1713
1714                 for (i = 0; i < len / sizeof(u32); i++) {
1715                         u32 pkcs = (u32)fdt32_to_cpu(pkcs_cell[i]);
1716
1717                         if (pkcs == CLK_CKPER_DISABLED) {
1718                                 ckper_disabled = true;
1719                                 continue;
1720                         }
1721                         pkcs_config(priv, pkcs);
1722                 }
1723                 /* CKPER is source for some peripheral clock
1724                  * (FMC-NAND / QPSI-NOR) and switching source is allowed
1725                  * only if previous clock is still ON
1726                  * => deactivated CKPER only after switching clock
1727                  */
1728                 if (ckper_disabled)
1729                         pkcs_config(priv, CLK_CKPER_DISABLED);
1730         }
1731
1732         /* STGEN clock source can change with CLK_STGEN_XXX */
1733         stgen_config(priv);
1734
1735         debug("oscillator off\n");
1736         /* switch OFF HSI if not found in device-tree */
1737         if (!priv->osc[_HSI])
1738                 stm32mp1_hsi_set(rcc, 0);
1739
1740         /* Software Self-Refresh mode (SSR) during DDR initilialization */
1741         clrsetbits_le32(priv->base + RCC_DDRITFCR,
1742                         RCC_DDRITFCR_DDRCKMOD_MASK,
1743                         RCC_DDRITFCR_DDRCKMOD_SSR <<
1744                         RCC_DDRITFCR_DDRCKMOD_SHIFT);
1745
1746         return 0;
1747 }
1748 #endif /* STM32MP1_CLOCK_TREE_INIT */
1749
1750 static int pll_set_output_rate(struct udevice *dev,
1751                                int pll_id,
1752                                int div_id,
1753                                unsigned long clk_rate)
1754 {
1755         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1756         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1757         u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1758         int div;
1759         ulong fvco;
1760
1761         if (div_id > _DIV_NB)
1762                 return -EINVAL;
1763
1764         fvco = pll_get_fvco(priv, pll_id);
1765
1766         if (fvco <= clk_rate)
1767                 div = 1;
1768         else
1769                 div = DIV_ROUND_UP(fvco, clk_rate);
1770
1771         if (div > 128)
1772                 div = 128;
1773
1774         debug("fvco = %ld, clk_rate = %ld, div=%d\n", fvco, clk_rate, div);
1775         /* stop the requested output */
1776         clrbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
1777         /* change divider */
1778         clrsetbits_le32(priv->base + pll[pll_id].pllxcfgr2,
1779                         RCC_PLLNCFGR2_DIVX_MASK << RCC_PLLNCFGR2_SHIFT(div_id),
1780                         (div - 1) << RCC_PLLNCFGR2_SHIFT(div_id));
1781         /* start the requested output */
1782         setbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
1783
1784         return 0;
1785 }
1786
1787 static ulong stm32mp1_clk_set_rate(struct clk *clk, unsigned long clk_rate)
1788 {
1789         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1790         int p;
1791
1792         switch (clk->id) {
1793         case LTDC_PX:
1794         case DSI_PX:
1795                 break;
1796         default:
1797                 pr_err("not supported");
1798                 return -EINVAL;
1799         }
1800
1801         p = stm32mp1_clk_get_parent(priv, clk->id);
1802         if (p < 0)
1803                 return -EINVAL;
1804
1805         switch (p) {
1806         case _PLL4_Q:
1807                 /* for LTDC_PX and DSI_PX case */
1808                 return pll_set_output_rate(clk->dev, _PLL4, _DIV_Q, clk_rate);
1809         }
1810
1811         return -EINVAL;
1812 }
1813
1814 static void stm32mp1_osc_clk_init(const char *name,
1815                                   struct stm32mp1_clk_priv *priv,
1816                                   int index)
1817 {
1818         struct clk clk;
1819         struct udevice *dev = NULL;
1820
1821         priv->osc[index] = 0;
1822         clk.id = 0;
1823         if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) {
1824                 if (clk_request(dev, &clk))
1825                         pr_err("%s request", name);
1826                 else
1827                         priv->osc[index] = clk_get_rate(&clk);
1828         }
1829         priv->osc_dev[index] = dev;
1830 }
1831
1832 static void stm32mp1_osc_init(struct udevice *dev)
1833 {
1834         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1835         int i;
1836         const char *name[NB_OSC] = {
1837                 [_LSI] = "clk-lsi",
1838                 [_LSE] = "clk-lse",
1839                 [_HSI] = "clk-hsi",
1840                 [_HSE] = "clk-hse",
1841                 [_CSI] = "clk-csi",
1842                 [_I2S_CKIN] = "i2s_ckin",
1843                 [_USB_PHY_48] = "ck_usbo_48m"};
1844
1845         for (i = 0; i < NB_OSC; i++) {
1846                 stm32mp1_osc_clk_init(name[i], priv, i);
1847                 debug("%d: %s => %x\n", i, name[i], (u32)priv->osc[i]);
1848         }
1849 }
1850
1851 static int stm32mp1_clk_probe(struct udevice *dev)
1852 {
1853         int result = 0;
1854         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1855
1856         priv->base = dev_read_addr(dev->parent);
1857         if (priv->base == FDT_ADDR_T_NONE)
1858                 return -EINVAL;
1859
1860         priv->data = (void *)&stm32mp1_data;
1861
1862         if (!priv->data->gate || !priv->data->sel ||
1863             !priv->data->pll)
1864                 return -EINVAL;
1865
1866         stm32mp1_osc_init(dev);
1867
1868 #ifdef STM32MP1_CLOCK_TREE_INIT
1869         /* clock tree init is done only one time, before relocation */
1870         if (!(gd->flags & GD_FLG_RELOC))
1871                 result = stm32mp1_clktree(dev);
1872 #endif
1873
1874         return result;
1875 }
1876
1877 static const struct clk_ops stm32mp1_clk_ops = {
1878         .enable = stm32mp1_clk_enable,
1879         .disable = stm32mp1_clk_disable,
1880         .get_rate = stm32mp1_clk_get_rate,
1881         .set_rate = stm32mp1_clk_set_rate,
1882 };
1883
1884 U_BOOT_DRIVER(stm32mp1_clock) = {
1885         .name = "stm32mp1_clk",
1886         .id = UCLASS_CLK,
1887         .ops = &stm32mp1_clk_ops,
1888         .priv_auto_alloc_size = sizeof(struct stm32mp1_clk_priv),
1889         .probe = stm32mp1_clk_probe,
1890 };