drivers/clk/clk_stm32mp1.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   4  */
   5
   6 #include <common.h>
   7 #include <clk-uclass.h>
   8 #include <div64.h>
   9 #include <dm.h>
  10 #include <regmap.h>
  11 #include <spl.h>
  12 #include <syscon.h>
  13 #include <linux/io.h>
  14 #include <linux/iopoll.h>
  15 #include <dt-bindings/clock/stm32mp1-clks.h>
  16 #include <dt-bindings/clock/stm32mp1-clksrc.h>
  17
  18 #ifndef CONFIG_STM32MP1_TRUSTED
  19 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
  20 /* activate clock tree initialization in the driver */
  21 #define STM32MP1_CLOCK_TREE_INIT
  22 #endif
  23 #endif
  24
  25 #define MAX_HSI_HZ              64000000
  26
  27 /* TIMEOUT */
  28 #define TIMEOUT_200MS           200000
  29 #define TIMEOUT_1S              1000000
  30
  31 /* STGEN registers */
  32 #define STGENC_CNTCR            0x00
  33 #define STGENC_CNTSR            0x04
  34 #define STGENC_CNTCVL           0x08
  35 #define STGENC_CNTCVU           0x0C
  36 #define STGENC_CNTFID0          0x20
  37
  38 #define STGENC_CNTCR_EN         BIT(0)
  39
  40 /* RCC registers */
  41 #define RCC_OCENSETR            0x0C
  42 #define RCC_OCENCLRR            0x10
  43 #define RCC_HSICFGR             0x18
  44 #define RCC_MPCKSELR            0x20
  45 #define RCC_ASSCKSELR           0x24
  46 #define RCC_RCK12SELR           0x28
  47 #define RCC_MPCKDIVR            0x2C
  48 #define RCC_AXIDIVR             0x30
  49 #define RCC_APB4DIVR            0x3C
  50 #define RCC_APB5DIVR            0x40
  51 #define RCC_RTCDIVR             0x44
  52 #define RCC_MSSCKSELR           0x48
  53 #define RCC_PLL1CR              0x80
  54 #define RCC_PLL1CFGR1           0x84
  55 #define RCC_PLL1CFGR2           0x88
  56 #define RCC_PLL1FRACR           0x8C
  57 #define RCC_PLL1CSGR            0x90
  58 #define RCC_PLL2CR              0x94
  59 #define RCC_PLL2CFGR1           0x98
  60 #define RCC_PLL2CFGR2           0x9C
  61 #define RCC_PLL2FRACR           0xA0
  62 #define RCC_PLL2CSGR            0xA4
  63 #define RCC_I2C46CKSELR         0xC0
  64 #define RCC_CPERCKSELR          0xD0
  65 #define RCC_STGENCKSELR         0xD4
  66 #define RCC_DDRITFCR            0xD8
  67 #define RCC_BDCR                0x140
  68 #define RCC_RDLSICR             0x144
  69 #define RCC_MP_APB4ENSETR       0x200
  70 #define RCC_MP_APB5ENSETR       0x208
  71 #define RCC_MP_AHB5ENSETR       0x210
  72 #define RCC_MP_AHB6ENSETR       0x218
  73 #define RCC_OCRDYR              0x808
  74 #define RCC_DBGCFGR             0x80C
  75 #define RCC_RCK3SELR            0x820
  76 #define RCC_RCK4SELR            0x824
  77 #define RCC_MCUDIVR             0x830
  78 #define RCC_APB1DIVR            0x834
  79 #define RCC_APB2DIVR            0x838
  80 #define RCC_APB3DIVR            0x83C
  81 #define RCC_PLL3CR              0x880
  82 #define RCC_PLL3CFGR1           0x884
  83 #define RCC_PLL3CFGR2           0x888
  84 #define RCC_PLL3FRACR           0x88C
  85 #define RCC_PLL3CSGR            0x890
  86 #define RCC_PLL4CR              0x894
  87 #define RCC_PLL4CFGR1           0x898
  88 #define RCC_PLL4CFGR2           0x89C
  89 #define RCC_PLL4FRACR           0x8A0
  90 #define RCC_PLL4CSGR            0x8A4
  91 #define RCC_I2C12CKSELR         0x8C0
  92 #define RCC_I2C35CKSELR         0x8C4
  93 #define RCC_SPI2S1CKSELR        0x8D8
  94 #define RCC_UART6CKSELR         0x8E4
  95 #define RCC_UART24CKSELR        0x8E8
  96 #define RCC_UART35CKSELR        0x8EC
  97 #define RCC_UART78CKSELR        0x8F0
  98 #define RCC_SDMMC12CKSELR       0x8F4
  99 #define RCC_SDMMC3CKSELR        0x8F8
 100 #define RCC_ETHCKSELR           0x8FC
 101 #define RCC_QSPICKSELR          0x900
 102 #define RCC_FMCCKSELR           0x904
 103 #define RCC_USBCKSELR           0x91C
 104 #define RCC_DSICKSELR           0x924
 105 #define RCC_ADCCKSELR           0x928
 106 #define RCC_MP_APB1ENSETR       0xA00
 107 #define RCC_MP_APB2ENSETR       0XA08
 108 #define RCC_MP_APB3ENSETR       0xA10
 109 #define RCC_MP_AHB2ENSETR       0xA18
 110 #define RCC_MP_AHB3ENSETR       0xA20
 111 #define RCC_MP_AHB4ENSETR       0xA28
 112
 113 /* used for most of SELR register */
 114 #define RCC_SELR_SRC_MASK       GENMASK(2, 0)
 115 #define RCC_SELR_SRCRDY         BIT(31)
 116
 117 /* Values of RCC_MPCKSELR register */
 118 #define RCC_MPCKSELR_HSI        0
 119 #define RCC_MPCKSELR_HSE        1
 120 #define RCC_MPCKSELR_PLL        2
 121 #define RCC_MPCKSELR_PLL_MPUDIV 3
 122
 123 /* Values of RCC_ASSCKSELR register */
 124 #define RCC_ASSCKSELR_HSI       0
 125 #define RCC_ASSCKSELR_HSE       1
 126 #define RCC_ASSCKSELR_PLL       2
 127
 128 /* Values of RCC_MSSCKSELR register */
 129 #define RCC_MSSCKSELR_HSI       0
 130 #define RCC_MSSCKSELR_HSE       1
 131 #define RCC_MSSCKSELR_CSI       2
 132 #define RCC_MSSCKSELR_PLL       3
 133
 134 /* Values of RCC_CPERCKSELR register */
 135 #define RCC_CPERCKSELR_HSI      0
 136 #define RCC_CPERCKSELR_CSI      1
 137 #define RCC_CPERCKSELR_HSE      2
 138
 139 /* used for most of DIVR register : max div for RTC */
 140 #define RCC_DIVR_DIV_MASK       GENMASK(5, 0)
 141 #define RCC_DIVR_DIVRDY         BIT(31)
 142
 143 /* Masks for specific DIVR registers */
 144 #define RCC_APBXDIV_MASK        GENMASK(2, 0)
 145 #define RCC_MPUDIV_MASK         GENMASK(2, 0)
 146 #define RCC_AXIDIV_MASK         GENMASK(2, 0)
 147 #define RCC_MCUDIV_MASK         GENMASK(3, 0)
 148
 149 /*  offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
 150 #define RCC_MP_ENCLRR_OFFSET    4
 151
 152 /* Fields of RCC_BDCR register */
 153 #define RCC_BDCR_LSEON          BIT(0)
 154 #define RCC_BDCR_LSEBYP         BIT(1)
 155 #define RCC_BDCR_LSERDY         BIT(2)
 156 #define RCC_BDCR_DIGBYP         BIT(3)
 157 #define RCC_BDCR_LSEDRV_MASK    GENMASK(5, 4)
 158 #define RCC_BDCR_LSEDRV_SHIFT   4
 159 #define RCC_BDCR_LSECSSON       BIT(8)
 160 #define RCC_BDCR_RTCCKEN        BIT(20)
 161 #define RCC_BDCR_RTCSRC_MASK    GENMASK(17, 16)
 162 #define RCC_BDCR_RTCSRC_SHIFT   16
 163
 164 /* Fields of RCC_RDLSICR register */
 165 #define RCC_RDLSICR_LSION       BIT(0)
 166 #define RCC_RDLSICR_LSIRDY      BIT(1)
 167
 168 /* used for ALL PLLNCR registers */
 169 #define RCC_PLLNCR_PLLON        BIT(0)
 170 #define RCC_PLLNCR_PLLRDY       BIT(1)
 171 #define RCC_PLLNCR_SSCG_CTRL    BIT(2)
 172 #define RCC_PLLNCR_DIVPEN       BIT(4)
 173 #define RCC_PLLNCR_DIVQEN       BIT(5)
 174 #define RCC_PLLNCR_DIVREN       BIT(6)
 175 #define RCC_PLLNCR_DIVEN_SHIFT  4
 176
 177 /* used for ALL PLLNCFGR1 registers */
 178 #define RCC_PLLNCFGR1_DIVM_SHIFT        16
 179 #define RCC_PLLNCFGR1_DIVM_MASK         GENMASK(21, 16)
 180 #define RCC_PLLNCFGR1_DIVN_SHIFT        0
 181 #define RCC_PLLNCFGR1_DIVN_MASK         GENMASK(8, 0)
 182 /* only for PLL3 and PLL4 */
 183 #define RCC_PLLNCFGR1_IFRGE_SHIFT       24
 184 #define RCC_PLLNCFGR1_IFRGE_MASK        GENMASK(25, 24)
 185
 186 /* used for ALL PLLNCFGR2 registers , using stm32mp1_div_id */
 187 #define RCC_PLLNCFGR2_SHIFT(div_id)     ((div_id) * 8)
 188 #define RCC_PLLNCFGR2_DIVX_MASK         GENMASK(6, 0)
 189 #define RCC_PLLNCFGR2_DIVP_SHIFT        RCC_PLLNCFGR2_SHIFT(_DIV_P)
 190 #define RCC_PLLNCFGR2_DIVP_MASK         GENMASK(6, 0)
 191 #define RCC_PLLNCFGR2_DIVQ_SHIFT        RCC_PLLNCFGR2_SHIFT(_DIV_Q)
 192 #define RCC_PLLNCFGR2_DIVQ_MASK         GENMASK(14, 8)
 193 #define RCC_PLLNCFGR2_DIVR_SHIFT        RCC_PLLNCFGR2_SHIFT(_DIV_R)
 194 #define RCC_PLLNCFGR2_DIVR_MASK         GENMASK(22, 16)
 195
 196 /* used for ALL PLLNFRACR registers */
 197 #define RCC_PLLNFRACR_FRACV_SHIFT       3
 198 #define RCC_PLLNFRACR_FRACV_MASK        GENMASK(15, 3)
 199 #define RCC_PLLNFRACR_FRACLE            BIT(16)
 200
 201 /* used for ALL PLLNCSGR registers */
 202 #define RCC_PLLNCSGR_INC_STEP_SHIFT     16
 203 #define RCC_PLLNCSGR_INC_STEP_MASK      GENMASK(30, 16)
 204 #define RCC_PLLNCSGR_MOD_PER_SHIFT      0
 205 #define RCC_PLLNCSGR_MOD_PER_MASK       GENMASK(12, 0)
 206 #define RCC_PLLNCSGR_SSCG_MODE_SHIFT    15
 207 #define RCC_PLLNCSGR_SSCG_MODE_MASK     BIT(15)
 208
 209 /* used for RCC_OCENSETR and RCC_OCENCLRR registers */
 210 #define RCC_OCENR_HSION                 BIT(0)
 211 #define RCC_OCENR_CSION                 BIT(4)
 212 #define RCC_OCENR_DIGBYP                BIT(7)
 213 #define RCC_OCENR_HSEON                 BIT(8)
 214 #define RCC_OCENR_HSEBYP                BIT(10)
 215 #define RCC_OCENR_HSECSSON              BIT(11)
 216
 217 /* Fields of RCC_OCRDYR register */
 218 #define RCC_OCRDYR_HSIRDY               BIT(0)
 219 #define RCC_OCRDYR_HSIDIVRDY            BIT(2)
 220 #define RCC_OCRDYR_CSIRDY               BIT(4)
 221 #define RCC_OCRDYR_HSERDY               BIT(8)
 222
 223 /* Fields of DDRITFCR register */
 224 #define RCC_DDRITFCR_DDRCKMOD_MASK      GENMASK(22, 20)
 225 #define RCC_DDRITFCR_DDRCKMOD_SHIFT     20
 226 #define RCC_DDRITFCR_DDRCKMOD_SSR       0
 227
 228 /* Fields of RCC_HSICFGR register */
 229 #define RCC_HSICFGR_HSIDIV_MASK         GENMASK(1, 0)
 230
 231 /* used for MCO related operations */
 232 #define RCC_MCOCFG_MCOON                BIT(12)
 233 #define RCC_MCOCFG_MCODIV_MASK          GENMASK(7, 4)
 234 #define RCC_MCOCFG_MCODIV_SHIFT         4
 235 #define RCC_MCOCFG_MCOSRC_MASK          GENMASK(2, 0)
 236
 237 enum stm32mp1_parent_id {
 238 /*
 239  * _HSI, _HSE, _CSI, _LSI, _LSE should not be moved
 240  * they are used as index in osc[] as entry point
 241  */
 242         _HSI,
 243         _HSE,
 244         _CSI,
 245         _LSI,
 246         _LSE,
 247         _I2S_CKIN,
 248         NB_OSC,
 249
 250 /* other parent source */
 251         _HSI_KER = NB_OSC,
 252         _HSE_KER,
 253         _HSE_KER_DIV2,
 254         _CSI_KER,
 255         _PLL1_P,
 256         _PLL1_Q,
 257         _PLL1_R,
 258         _PLL2_P,
 259         _PLL2_Q,
 260         _PLL2_R,
 261         _PLL3_P,
 262         _PLL3_Q,
 263         _PLL3_R,
 264         _PLL4_P,
 265         _PLL4_Q,
 266         _PLL4_R,
 267         _ACLK,
 268         _PCLK1,
 269         _PCLK2,
 270         _PCLK3,
 271         _PCLK4,
 272         _PCLK5,
 273         _HCLK6,
 274         _HCLK2,
 275         _CK_PER,
 276         _CK_MPU,
 277         _CK_MCU,
 278         _DSI_PHY,
 279         _USB_PHY_48,
 280         _PARENT_NB,
 281         _UNKNOWN_ID = 0xff,
 282 };
 283
 284 enum stm32mp1_parent_sel {
 285         _I2C12_SEL,
 286         _I2C35_SEL,
 287         _I2C46_SEL,
 288         _UART6_SEL,
 289         _UART24_SEL,
 290         _UART35_SEL,
 291         _UART78_SEL,
 292         _SDMMC12_SEL,
 293         _SDMMC3_SEL,
 294         _ETH_SEL,
 295         _QSPI_SEL,
 296         _FMC_SEL,
 297         _USBPHY_SEL,
 298         _USBO_SEL,
 299         _STGEN_SEL,
 300         _DSI_SEL,
 301         _ADC12_SEL,
 302         _SPI1_SEL,
 303         _RTC_SEL,
 304         _PARENT_SEL_NB,
 305         _UNKNOWN_SEL = 0xff,
 306 };
 307
 308 enum stm32mp1_pll_id {
 309         _PLL1,
 310         _PLL2,
 311         _PLL3,
 312         _PLL4,
 313         _PLL_NB
 314 };
 315
 316 enum stm32mp1_div_id {
 317         _DIV_P,
 318         _DIV_Q,
 319         _DIV_R,
 320         _DIV_NB,
 321 };
 322
 323 enum stm32mp1_clksrc_id {
 324         CLKSRC_MPU,
 325         CLKSRC_AXI,
 326         CLKSRC_MCU,
 327         CLKSRC_PLL12,
 328         CLKSRC_PLL3,
 329         CLKSRC_PLL4,
 330         CLKSRC_RTC,
 331         CLKSRC_MCO1,
 332         CLKSRC_MCO2,
 333         CLKSRC_NB
 334 };
 335
 336 enum stm32mp1_clkdiv_id {
 337         CLKDIV_MPU,
 338         CLKDIV_AXI,
 339         CLKDIV_MCU,
 340         CLKDIV_APB1,
 341         CLKDIV_APB2,
 342         CLKDIV_APB3,
 343         CLKDIV_APB4,
 344         CLKDIV_APB5,
 345         CLKDIV_RTC,
 346         CLKDIV_MCO1,
 347         CLKDIV_MCO2,
 348         CLKDIV_NB
 349 };
 350
 351 enum stm32mp1_pllcfg {
 352         PLLCFG_M,
 353         PLLCFG_N,
 354         PLLCFG_P,
 355         PLLCFG_Q,
 356         PLLCFG_R,
 357         PLLCFG_O,
 358         PLLCFG_NB
 359 };
 360
 361 enum stm32mp1_pllcsg {
 362         PLLCSG_MOD_PER,
 363         PLLCSG_INC_STEP,
 364         PLLCSG_SSCG_MODE,
 365         PLLCSG_NB
 366 };
 367
 368 enum stm32mp1_plltype {
 369         PLL_800,
 370         PLL_1600,
 371         PLL_TYPE_NB
 372 };
 373
 374 struct stm32mp1_pll {
 375         u8 refclk_min;
 376         u8 refclk_max;
 377         u8 divn_max;
 378 };
 379
 380 struct stm32mp1_clk_gate {
 381         u16 offset;
 382         u8 bit;
 383         u8 index;
 384         u8 set_clr;
 385         u8 sel;
 386         u8 fixed;
 387 };
 388
 389 struct stm32mp1_clk_sel {
 390         u16 offset;
 391         u8 src;
 392         u8 msk;
 393         u8 nb_parent;
 394         const u8 *parent;
 395 };
 396
 397 #define REFCLK_SIZE 4
 398 struct stm32mp1_clk_pll {
 399         enum stm32mp1_plltype plltype;
 400         u16 rckxselr;
 401         u16 pllxcfgr1;
 402         u16 pllxcfgr2;
 403         u16 pllxfracr;
 404         u16 pllxcr;
 405         u16 pllxcsgr;
 406         u8 refclk[REFCLK_SIZE];
 407 };
 408
 409 struct stm32mp1_clk_data {
 410         const struct stm32mp1_clk_gate *gate;
 411         const struct stm32mp1_clk_sel *sel;
 412         const struct stm32mp1_clk_pll *pll;
 413         const int nb_gate;
 414 };
 415
 416 struct stm32mp1_clk_priv {
 417         fdt_addr_t base;
 418         const struct stm32mp1_clk_data *data;
 419         ulong osc[NB_OSC];
 420         struct udevice *osc_dev[NB_OSC];
 421 };
 422
 423 #define STM32MP1_CLK(off, b, idx, s)            \
 424         {                                       \
 425                 .offset = (off),                \
 426                 .bit = (b),                     \
 427                 .index = (idx),                 \
 428                 .set_clr = 0,                   \
 429                 .sel = (s),                     \
 430                 .fixed = _UNKNOWN_ID,           \
 431         }
 432
 433 #define STM32MP1_CLK_F(off, b, idx, f)          \
 434         {                                       \
 435                 .offset = (off),                \
 436                 .bit = (b),                     \
 437                 .index = (idx),                 \
 438                 .set_clr = 0,                   \
 439                 .sel = _UNKNOWN_SEL,            \
 440                 .fixed = (f),                   \
 441         }
 442
 443 #define STM32MP1_CLK_SET_CLR(off, b, idx, s)    \
 444         {                                       \
 445                 .offset = (off),                \
 446                 .bit = (b),                     \
 447                 .index = (idx),                 \
 448                 .set_clr = 1,                   \
 449                 .sel = (s),                     \
 450                 .fixed = _UNKNOWN_ID,           \
 451         }
 452
 453 #define STM32MP1_CLK_SET_CLR_F(off, b, idx, f)  \
 454         {                                       \
 455                 .offset = (off),                \
 456                 .bit = (b),                     \
 457                 .index = (idx),                 \
 458                 .set_clr = 1,                   \
 459                 .sel = _UNKNOWN_SEL,            \
 460                 .fixed = (f),                   \
 461         }
 462
 463 #define STM32MP1_CLK_PARENT(idx, off, s, m, p)   \
 464         [(idx)] = {                             \
 465                 .offset = (off),                \
 466                 .src = (s),                     \
 467                 .msk = (m),                     \
 468                 .parent = (p),                  \
 469                 .nb_parent = ARRAY_SIZE((p))    \
 470         }
 471
 472 #define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, off4, off5, off6,\
 473                         p1, p2, p3, p4) \
 474         [(idx)] = {                             \
 475                 .plltype = (type),                      \
 476                 .rckxselr = (off1),             \
 477                 .pllxcfgr1 = (off2),            \
 478                 .pllxcfgr2 = (off3),            \
 479                 .pllxfracr = (off4),            \
 480                 .pllxcr = (off5),               \
 481                 .pllxcsgr = (off6),             \
 482                 .refclk[0] = (p1),              \
 483                 .refclk[1] = (p2),              \
 484                 .refclk[2] = (p3),              \
 485                 .refclk[3] = (p4),              \
 486         }
 487
 488 static const u8 stm32mp1_clks[][2] = {
 489         {CK_PER, _CK_PER},
 490         {CK_MPU, _CK_MPU},
 491         {CK_AXI, _ACLK},
 492         {CK_MCU, _CK_MCU},
 493         {CK_HSE, _HSE},
 494         {CK_CSI, _CSI},
 495         {CK_LSI, _LSI},
 496         {CK_LSE, _LSE},
 497         {CK_HSI, _HSI},
 498         {CK_HSE_DIV2, _HSE_KER_DIV2},
 499 };
 500
 501 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
 502         STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL),
 503         STM32MP1_CLK(RCC_DDRITFCR, 1, DDRC1LP, _UNKNOWN_SEL),
 504         STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL),
 505         STM32MP1_CLK(RCC_DDRITFCR, 3, DDRC2LP, _UNKNOWN_SEL),
 506         STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
 507         STM32MP1_CLK(RCC_DDRITFCR, 5, DDRPHYCLP, _UNKNOWN_SEL),
 508         STM32MP1_CLK(RCC_DDRITFCR, 6, DDRCAPB, _UNKNOWN_SEL),
 509         STM32MP1_CLK(RCC_DDRITFCR, 7, DDRCAPBLP, _UNKNOWN_SEL),
 510         STM32MP1_CLK(RCC_DDRITFCR, 8, AXIDCG, _UNKNOWN_SEL),
 511         STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL),
 512         STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL),
 513
 514         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
 515         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
 516         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
 517         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL),
 518         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL),
 519         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL),
 520         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL),
 521         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL),
 522         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL),
 523         STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
 524
 525         STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 8, SPI1_K, _SPI1_SEL),
 526         STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
 527
 528         STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3),
 529
 530         STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 0, LTDC_PX, _PLL4_Q),
 531         STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 4, DSI_PX, _PLL4_Q),
 532         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 4, DSI_K, _DSI_SEL),
 533         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
 534         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
 535         STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
 536
 537         STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
 538         STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5),
 539         STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
 540
 541         STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB2ENSETR, 5, ADC12, _HCLK2),
 542         STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 5, ADC12_K, _ADC12_SEL),
 543         STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
 544         STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
 545
 546         STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 11, HSEM, _UNKNOWN_SEL),
 547         STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 12, IPCC, _UNKNOWN_SEL),
 548
 549         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
 550         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
 551         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
 552         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL),
 553         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL),
 554         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL),
 555         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL),
 556         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL),
 557         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL),
 558         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL),
 559         STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
 560
 561         STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
 562
 563         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK_K, _ETH_SEL),
 564         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL),
 565         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL),
 566         STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK),
 567         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
 568         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
 569         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL),
 570         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL),
 571         STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL),
 572
 573         STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
 574
 575         STM32MP1_CLK(RCC_BDCR, 20, RTC, _RTC_SEL),
 576 };
 577
 578 static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
 579 static const u8 i2c35_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
 580 static const u8 i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER};
 581 static const u8 uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
 582                                         _HSE_KER};
 583 static const u8 uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 584                                          _HSE_KER};
 585 static const u8 uart35_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 586                                          _HSE_KER};
 587 static const u8 uart78_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
 588                                          _HSE_KER};
 589 static const u8 sdmmc12_parents[] = {_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER};
 590 static const u8 sdmmc3_parents[] = {_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER};
 591 static const u8 eth_parents[] = {_PLL4_P, _PLL3_Q};
 592 static const u8 qspi_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
 593 static const u8 fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
 594 static const u8 usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2};
 595 static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48};
 596 static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER};
 597 static const u8 dsi_parents[] = {_DSI_PHY, _PLL4_P};
 598 static const u8 adc_parents[] = {_PLL4_R, _CK_PER, _PLL3_Q};
 599 static const u8 spi_parents[] = {_PLL4_P, _PLL3_Q, _I2S_CKIN, _CK_PER,
 600                                  _PLL3_R};
 601 static const u8 rtc_parents[] = {_UNKNOWN_ID, _LSE, _LSI, _HSE};
 602
 603 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
 604         STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents),
 605         STM32MP1_CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents),
 606         STM32MP1_CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents),
 607         STM32MP1_CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents),
 608         STM32MP1_CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7,
 609                             uart24_parents),
 610         STM32MP1_CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7,
 611                             uart35_parents),
 612         STM32MP1_CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7,
 613                             uart78_parents),
 614         STM32MP1_CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7,
 615                             sdmmc12_parents),
 616         STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7,
 617                             sdmmc3_parents),
 618         STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents),
 619         STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents),
 620         STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents),
 621         STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents),
 622         STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
 623         STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
 624         STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents),
 625         STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x1, adc_parents),
 626         STM32MP1_CLK_PARENT(_SPI1_SEL, RCC_SPI2S1CKSELR, 0, 0x7, spi_parents),
 627         STM32MP1_CLK_PARENT(_RTC_SEL, RCC_BDCR, RCC_BDCR_RTCSRC_SHIFT,
 628                             (RCC_BDCR_RTCSRC_MASK >> RCC_BDCR_RTCSRC_SHIFT),
 629                             rtc_parents),
 630 };
 631
 632 #ifdef STM32MP1_CLOCK_TREE_INIT
 633 /* define characteristic of PLL according type */
 634 #define DIVN_MIN        24
 635 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
 636         [PLL_800] = {
 637                 .refclk_min = 4,
 638                 .refclk_max = 16,
 639                 .divn_max = 99,
 640                 },
 641         [PLL_1600] = {
 642                 .refclk_min = 8,
 643                 .refclk_max = 16,
 644                 .divn_max = 199,
 645                 },
 646 };
 647 #endif /* STM32MP1_CLOCK_TREE_INIT */
 648
 649 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = {
 650         STM32MP1_CLK_PLL(_PLL1, PLL_1600,
 651                          RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2,
 652                          RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR,
 653                          _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
 654         STM32MP1_CLK_PLL(_PLL2, PLL_1600,
 655                          RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2,
 656                          RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR,
 657                          _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
 658         STM32MP1_CLK_PLL(_PLL3, PLL_800,
 659                          RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2,
 660                          RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR,
 661                          _HSI, _HSE, _CSI, _UNKNOWN_ID),
 662         STM32MP1_CLK_PLL(_PLL4, PLL_800,
 663                          RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2,
 664                          RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR,
 665                          _HSI, _HSE, _CSI, _I2S_CKIN),
 666 };
 667
 668 /* Prescaler table lookups for clock computation */
 669 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */
 670 static const u8 stm32mp1_mcu_div[16] = {
 671         0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9
 672 };
 673
 674 /* div = /1 /2 /4 /8 /16 : same divider for pmu and apbx*/
 675 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div
 676 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div
 677 static const u8 stm32mp1_mpu_apbx_div[8] = {
 678         0, 1, 2, 3, 4, 4, 4, 4
 679 };
 680
 681 /* div = /1 /2 /3 /4 */
 682 static const u8 stm32mp1_axi_div[8] = {
 683         1, 2, 3, 4, 4, 4, 4, 4
 684 };
 685
 686 static const __maybe_unused
 687 char * const stm32mp1_clk_parent_name[_PARENT_NB] = {
 688         [_HSI] = "HSI",
 689         [_HSE] = "HSE",
 690         [_CSI] = "CSI",
 691         [_LSI] = "LSI",
 692         [_LSE] = "LSE",
 693         [_I2S_CKIN] = "I2S_CKIN",
 694         [_HSI_KER] = "HSI_KER",
 695         [_HSE_KER] = "HSE_KER",
 696         [_HSE_KER_DIV2] = "HSE_KER_DIV2",
 697         [_CSI_KER] = "CSI_KER",
 698         [_PLL1_P] = "PLL1_P",
 699         [_PLL1_Q] = "PLL1_Q",
 700         [_PLL1_R] = "PLL1_R",
 701         [_PLL2_P] = "PLL2_P",
 702         [_PLL2_Q] = "PLL2_Q",
 703         [_PLL2_R] = "PLL2_R",
 704         [_PLL3_P] = "PLL3_P",
 705         [_PLL3_Q] = "PLL3_Q",
 706         [_PLL3_R] = "PLL3_R",
 707         [_PLL4_P] = "PLL4_P",
 708         [_PLL4_Q] = "PLL4_Q",
 709         [_PLL4_R] = "PLL4_R",
 710         [_ACLK] = "ACLK",
 711         [_PCLK1] = "PCLK1",
 712         [_PCLK2] = "PCLK2",
 713         [_PCLK3] = "PCLK3",
 714         [_PCLK4] = "PCLK4",
 715         [_PCLK5] = "PCLK5",
 716         [_HCLK6] = "KCLK6",
 717         [_HCLK2] = "HCLK2",
 718         [_CK_PER] = "CK_PER",
 719         [_CK_MPU] = "CK_MPU",
 720         [_CK_MCU] = "CK_MCU",
 721         [_USB_PHY_48] = "USB_PHY_48",
 722         [_DSI_PHY] = "DSI_PHY_PLL",
 723 };
 724
 725 static const __maybe_unused
 726 char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
 727         [_I2C12_SEL] = "I2C12",
 728         [_I2C35_SEL] = "I2C35",
 729         [_I2C46_SEL] = "I2C46",
 730         [_UART6_SEL] = "UART6",
 731         [_UART24_SEL] = "UART24",
 732         [_UART35_SEL] = "UART35",
 733         [_UART78_SEL] = "UART78",
 734         [_SDMMC12_SEL] = "SDMMC12",
 735         [_SDMMC3_SEL] = "SDMMC3",
 736         [_ETH_SEL] = "ETH",
 737         [_QSPI_SEL] = "QSPI",
 738         [_FMC_SEL] = "FMC",
 739         [_USBPHY_SEL] = "USBPHY",
 740         [_USBO_SEL] = "USBO",
 741         [_STGEN_SEL] = "STGEN",
 742         [_DSI_SEL] = "DSI",
 743         [_ADC12_SEL] = "ADC12",
 744         [_SPI1_SEL] = "SPI1",
 745         [_RTC_SEL] = "RTC",
 746 };
 747
 748 static const struct stm32mp1_clk_data stm32mp1_data = {
 749         .gate = stm32mp1_clk_gate,
 750         .sel = stm32mp1_clk_sel,
 751         .pll = stm32mp1_clk_pll,
 752         .nb_gate = ARRAY_SIZE(stm32mp1_clk_gate),
 753 };
 754
 755 static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx)
 756 {
 757         if (idx >= NB_OSC) {
 758                 debug("%s: clk id %d not found\n", __func__, idx);
 759                 return 0;
 760         }
 761
 762         return priv->osc[idx];
 763 }
 764
 765 static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id)
 766 {
 767         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 768         int i, nb_clks = priv->data->nb_gate;
 769
 770         for (i = 0; i < nb_clks; i++) {
 771                 if (gate[i].index == id)
 772                         break;
 773         }
 774
 775         if (i == nb_clks) {
 776                 printf("%s: clk id %d not found\n", __func__, (u32)id);
 777                 return -EINVAL;
 778         }
 779
 780         return i;
 781 }
 782
 783 static int stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv,
 784                                 int i)
 785 {
 786         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 787
 788         if (gate[i].sel > _PARENT_SEL_NB) {
 789                 printf("%s: parents for clk id %d not found\n",
 790                        __func__, i);
 791                 return -EINVAL;
 792         }
 793
 794         return gate[i].sel;
 795 }
 796
 797 static int stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv *priv,
 798                                          int i)
 799 {
 800         const struct stm32mp1_clk_gate *gate = priv->data->gate;
 801
 802         if (gate[i].fixed == _UNKNOWN_ID)
 803                 return -ENOENT;
 804
 805         return gate[i].fixed;
 806 }
 807
 808 static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv,
 809                                    unsigned long id)
 810 {
 811         const struct stm32mp1_clk_sel *sel = priv->data->sel;
 812         int i;
 813         int s, p;
 814         unsigned int idx;
 815
 816         for (idx = 0; idx < ARRAY_SIZE(stm32mp1_clks); idx++)
 817                 if (stm32mp1_clks[idx][0] == id)
 818                         return stm32mp1_clks[idx][1];
 819
 820         i = stm32mp1_clk_get_id(priv, id);
 821         if (i < 0)
 822                 return i;
 823
 824         p = stm32mp1_clk_get_fixed_parent(priv, i);
 825         if (p >= 0 && p < _PARENT_NB)
 826                 return p;
 827
 828         s = stm32mp1_clk_get_sel(priv, i);
 829         if (s < 0)
 830                 return s;
 831
 832         p = (readl(priv->base + sel[s].offset) >> sel[s].src) & sel[s].msk;
 833
 834         if (p < sel[s].nb_parent) {
 835 #ifdef DEBUG
 836                 debug("%s: %s clock is the parent %s of clk id %d\n", __func__,
 837                       stm32mp1_clk_parent_name[sel[s].parent[p]],
 838                       stm32mp1_clk_parent_sel_name[s],
 839                       (u32)id);
 840 #endif
 841                 return sel[s].parent[p];
 842         }
 843
 844         pr_err("%s: no parents defined for clk id %d\n",
 845                __func__, (u32)id);
 846
 847         return -EINVAL;
 848 }
 849
 850 static ulong  pll_get_fref_ck(struct stm32mp1_clk_priv *priv,
 851                               int pll_id)
 852 {
 853         const struct stm32mp1_clk_pll *pll = priv->data->pll;
 854         u32 selr;
 855         int src;
 856         ulong refclk;
 857
 858         /* Get current refclk */
 859         selr = readl(priv->base + pll[pll_id].rckxselr);
 860         src = selr & RCC_SELR_SRC_MASK;
 861
 862         refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]);
 863
 864         return refclk;
 865 }
 866
 867 /*
 868  * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL
 869  * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1)
 870  * - PLL3 & PLL4 => return VCO     with Fpll_y_ck = FVCO / (DIVy + 1)
 871  * => in all the case Fpll_y_ck = pll_get_fvco() / (DIVy + 1)
 872  */
 873 static ulong pll_get_fvco(struct stm32mp1_clk_priv *priv,
 874                           int pll_id)
 875 {
 876         const struct stm32mp1_clk_pll *pll = priv->data->pll;
 877         int divm, divn;
 878         ulong refclk, fvco;
 879         u32 cfgr1, fracr;
 880
 881         cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1);
 882         fracr = readl(priv->base + pll[pll_id].pllxfracr);
 883
 884         divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
 885         divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
 886
 887         refclk = pll_get_fref_ck(priv, pll_id);
 888
 889         /* with FRACV :
 890          *   Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1)
 891          * without FRACV
 892          *   Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1)
 893          */
 894         if (fracr & RCC_PLLNFRACR_FRACLE) {
 895                 u32 fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK)
 896                             >> RCC_PLLNFRACR_FRACV_SHIFT;
 897                 fvco = (ulong)lldiv((unsigned long long)refclk *
 898                                      (((divn + 1) << 13) + fracv),
 899                                      ((unsigned long long)(divm + 1)) << 13);
 900         } else {
 901                 fvco = (ulong)(refclk * (divn + 1) / (divm + 1));
 902         }
 903
 904         return fvco;
 905 }
 906
 907 static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
 908                                     int pll_id, int div_id)
 909 {
 910         const struct stm32mp1_clk_pll *pll = priv->data->pll;
 911         int divy;
 912         ulong dfout;
 913         u32 cfgr2;
 914
 915         if (div_id >= _DIV_NB)
 916                 return 0;
 917
 918         cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2);
 919         divy = (cfgr2 >> RCC_PLLNCFGR2_SHIFT(div_id)) & RCC_PLLNCFGR2_DIVX_MASK;
 920
 921         dfout = pll_get_fvco(priv, pll_id) / (divy + 1);
 922
 923         return dfout;
 924 }
 925
 926 static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
 927 {
 928         u32 reg;
 929         ulong clock = 0;
 930
 931         switch (p) {
 932         case _CK_MPU:
 933         /* MPU sub system */
 934                 reg = readl(priv->base + RCC_MPCKSELR);
 935                 switch (reg & RCC_SELR_SRC_MASK) {
 936                 case RCC_MPCKSELR_HSI:
 937                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
 938                         break;
 939                 case RCC_MPCKSELR_HSE:
 940                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
 941                         break;
 942                 case RCC_MPCKSELR_PLL:
 943                 case RCC_MPCKSELR_PLL_MPUDIV:
 944                         clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P);
 945                         if (p == RCC_MPCKSELR_PLL_MPUDIV) {
 946                                 reg = readl(priv->base + RCC_MPCKDIVR);
 947                                 clock /= stm32mp1_mpu_div[reg &
 948                                                           RCC_MPUDIV_MASK];
 949                         }
 950                         break;
 951                 }
 952                 break;
 953         /* AXI sub system */
 954         case _ACLK:
 955         case _HCLK2:
 956         case _HCLK6:
 957         case _PCLK4:
 958         case _PCLK5:
 959                 reg = readl(priv->base + RCC_ASSCKSELR);
 960                 switch (reg & RCC_SELR_SRC_MASK) {
 961                 case RCC_ASSCKSELR_HSI:
 962                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
 963                         break;
 964                 case RCC_ASSCKSELR_HSE:
 965                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
 966                         break;
 967                 case RCC_ASSCKSELR_PLL:
 968                         clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P);
 969                         break;
 970                 }
 971
 972                 /* System clock divider */
 973                 reg = readl(priv->base + RCC_AXIDIVR);
 974                 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK];
 975
 976                 switch (p) {
 977                 case _PCLK4:
 978                         reg = readl(priv->base + RCC_APB4DIVR);
 979                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
 980                         break;
 981                 case _PCLK5:
 982                         reg = readl(priv->base + RCC_APB5DIVR);
 983                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
 984                         break;
 985                 default:
 986                         break;
 987                 }
 988                 break;
 989         /* MCU sub system */
 990         case _CK_MCU:
 991         case _PCLK1:
 992         case _PCLK2:
 993         case _PCLK3:
 994                 reg = readl(priv->base + RCC_MSSCKSELR);
 995                 switch (reg & RCC_SELR_SRC_MASK) {
 996                 case RCC_MSSCKSELR_HSI:
 997                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
 998                         break;
 999                 case RCC_MSSCKSELR_HSE:
1000                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
1001                         break;
1002                 case RCC_MSSCKSELR_CSI:
1003                         clock = stm32mp1_clk_get_fixed(priv, _CSI);
1004                         break;
1005                 case RCC_MSSCKSELR_PLL:
1006                         clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_P);
1007                         break;
1008                 }
1009
1010                 /* MCU clock divider */
1011                 reg = readl(priv->base + RCC_MCUDIVR);
1012                 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK];
1013
1014                 switch (p) {
1015                 case _PCLK1:
1016                         reg = readl(priv->base + RCC_APB1DIVR);
1017                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1018                         break;
1019                 case _PCLK2:
1020                         reg = readl(priv->base + RCC_APB2DIVR);
1021                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1022                         break;
1023                 case _PCLK3:
1024                         reg = readl(priv->base + RCC_APB3DIVR);
1025                         clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1026                         break;
1027                 case _CK_MCU:
1028                 default:
1029                         break;
1030                 }
1031                 break;
1032         case _CK_PER:
1033                 reg = readl(priv->base + RCC_CPERCKSELR);
1034                 switch (reg & RCC_SELR_SRC_MASK) {
1035                 case RCC_CPERCKSELR_HSI:
1036                         clock = stm32mp1_clk_get_fixed(priv, _HSI);
1037                         break;
1038                 case RCC_CPERCKSELR_HSE:
1039                         clock = stm32mp1_clk_get_fixed(priv, _HSE);
1040                         break;
1041                 case RCC_CPERCKSELR_CSI:
1042                         clock = stm32mp1_clk_get_fixed(priv, _CSI);
1043                         break;
1044                 }
1045                 break;
1046         case _HSI:
1047         case _HSI_KER:
1048                 clock = stm32mp1_clk_get_fixed(priv, _HSI);
1049                 break;
1050         case _CSI:
1051         case _CSI_KER:
1052                 clock = stm32mp1_clk_get_fixed(priv, _CSI);
1053                 break;
1054         case _HSE:
1055         case _HSE_KER:
1056         case _HSE_KER_DIV2:
1057                 clock = stm32mp1_clk_get_fixed(priv, _HSE);
1058                 if (p == _HSE_KER_DIV2)
1059                         clock >>= 1;
1060                 break;
1061         case _LSI:
1062                 clock = stm32mp1_clk_get_fixed(priv, _LSI);
1063                 break;
1064         case _LSE:
1065                 clock = stm32mp1_clk_get_fixed(priv, _LSE);
1066                 break;
1067         /* PLL */
1068         case _PLL1_P:
1069         case _PLL1_Q:
1070         case _PLL1_R:
1071                 clock = stm32mp1_read_pll_freq(priv, _PLL1, p - _PLL1_P);
1072                 break;
1073         case _PLL2_P:
1074         case _PLL2_Q:
1075         case _PLL2_R:
1076                 clock = stm32mp1_read_pll_freq(priv, _PLL2, p - _PLL2_P);
1077                 break;
1078         case _PLL3_P:
1079         case _PLL3_Q:
1080         case _PLL3_R:
1081                 clock = stm32mp1_read_pll_freq(priv, _PLL3, p - _PLL3_P);
1082                 break;
1083         case _PLL4_P:
1084         case _PLL4_Q:
1085         case _PLL4_R:
1086                 clock = stm32mp1_read_pll_freq(priv, _PLL4, p - _PLL4_P);
1087                 break;
1088         /* other */
1089         case _USB_PHY_48:
1090                 clock = 48000000;
1091                 break;
1092         case _DSI_PHY:
1093         {
1094                 struct clk clk;
1095                 struct udevice *dev = NULL;
1096
1097                 if (!uclass_get_device_by_name(UCLASS_CLK, "ck_dsi_phy",
1098                                                &dev)) {
1099                         if (clk_request(dev, &clk)) {
1100                                 pr_err("ck_dsi_phy request");
1101                         } else {
1102                                 clk.id = 0;
1103                                 clock = clk_get_rate(&clk);
1104                         }
1105                 }
1106                 break;
1107         }
1108         default:
1109                 break;
1110         }
1111
1112         debug("%s(%d) clock = %lx : %ld kHz\n",
1113               __func__, p, clock, clock / 1000);
1114
1115         return clock;
1116 }
1117
1118 static int stm32mp1_clk_enable(struct clk *clk)
1119 {
1120         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1121         const struct stm32mp1_clk_gate *gate = priv->data->gate;
1122         int i = stm32mp1_clk_get_id(priv, clk->id);
1123
1124         if (i < 0)
1125                 return i;
1126
1127         if (gate[i].set_clr)
1128                 writel(BIT(gate[i].bit), priv->base + gate[i].offset);
1129         else
1130                 setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1131
1132         debug("%s: id clock %d has been enabled\n", __func__, (u32)clk->id);
1133
1134         return 0;
1135 }
1136
1137 static int stm32mp1_clk_disable(struct clk *clk)
1138 {
1139         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1140         const struct stm32mp1_clk_gate *gate = priv->data->gate;
1141         int i = stm32mp1_clk_get_id(priv, clk->id);
1142
1143         if (i < 0)
1144                 return i;
1145
1146         if (gate[i].set_clr)
1147                 writel(BIT(gate[i].bit),
1148                        priv->base + gate[i].offset
1149                        + RCC_MP_ENCLRR_OFFSET);
1150         else
1151                 clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1152
1153         debug("%s: id clock %d has been disabled\n", __func__, (u32)clk->id);
1154
1155         return 0;
1156 }
1157
1158 static ulong stm32mp1_clk_get_rate(struct clk *clk)
1159 {
1160         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1161         int p = stm32mp1_clk_get_parent(priv, clk->id);
1162         ulong rate;
1163
1164         if (p < 0)
1165                 return 0;
1166
1167         rate = stm32mp1_clk_get(priv, p);
1168
1169 #ifdef DEBUG
1170         debug("%s: computed rate for id clock %d is %d (parent is %s)\n",
1171               __func__, (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]);
1172 #endif
1173         return rate;
1174 }
1175
1176 #ifdef STM32MP1_CLOCK_TREE_INIT
1177 static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset,
1178                                 u32 mask_on)
1179 {
1180         u32 address = rcc + offset;
1181
1182         if (enable)
1183                 setbits_le32(address, mask_on);
1184         else
1185                 clrbits_le32(address, mask_on);
1186 }
1187
1188 static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on)
1189 {
1190         writel(mask_on, rcc + (enable ? RCC_OCENSETR : RCC_OCENCLRR));
1191 }
1192
1193 static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset,
1194                              u32 mask_rdy)
1195 {
1196         u32 mask_test = 0;
1197         u32 address = rcc + offset;
1198         u32 val;
1199         int ret;
1200
1201         if (enable)
1202                 mask_test = mask_rdy;
1203
1204         ret = readl_poll_timeout(address, val,
1205                                  (val & mask_rdy) == mask_test,
1206                                  TIMEOUT_1S);
1207
1208         if (ret)
1209                 pr_err("OSC %x @ %x timeout for enable=%d : 0x%x\n",
1210                        mask_rdy, address, enable, readl(address));
1211
1212         return ret;
1213 }
1214
1215 static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int digbyp,
1216                                 int lsedrv)
1217 {
1218         u32 value;
1219
1220         if (digbyp)
1221                 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_DIGBYP);
1222
1223         if (bypass || digbyp)
1224                 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP);
1225
1226         /*
1227          * warning: not recommended to switch directly from "high drive"
1228          * to "medium low drive", and vice-versa.
1229          */
1230         value = (readl(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK)
1231                 >> RCC_BDCR_LSEDRV_SHIFT;
1232
1233         while (value != lsedrv) {
1234                 if (value > lsedrv)
1235                         value--;
1236                 else
1237                         value++;
1238
1239                 clrsetbits_le32(rcc + RCC_BDCR,
1240                                 RCC_BDCR_LSEDRV_MASK,
1241                                 value << RCC_BDCR_LSEDRV_SHIFT);
1242         }
1243
1244         stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON);
1245 }
1246
1247 static void stm32mp1_lse_wait(fdt_addr_t rcc)
1248 {
1249         stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY);
1250 }
1251
1252 static void stm32mp1_lsi_set(fdt_addr_t rcc, int enable)
1253 {
1254         stm32mp1_ls_osc_set(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSION);
1255         stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY);
1256 }
1257
1258 static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int digbyp, int css)
1259 {
1260         if (digbyp)
1261                 writel(RCC_OCENR_DIGBYP, rcc + RCC_OCENSETR);
1262         if (bypass || digbyp)
1263                 writel(RCC_OCENR_HSEBYP, rcc + RCC_OCENSETR);
1264
1265         stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON);
1266         stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY);
1267
1268         if (css)
1269                 writel(RCC_OCENR_HSECSSON, rcc + RCC_OCENSETR);
1270 }
1271
1272 static void stm32mp1_csi_set(fdt_addr_t rcc, int enable)
1273 {
1274         stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_CSION);
1275         stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY);
1276 }
1277
1278 static void stm32mp1_hsi_set(fdt_addr_t rcc, int enable)
1279 {
1280         stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_HSION);
1281         stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_HSIRDY);
1282 }
1283
1284 static int stm32mp1_set_hsidiv(fdt_addr_t rcc, u8 hsidiv)
1285 {
1286         u32 address = rcc + RCC_OCRDYR;
1287         u32 val;
1288         int ret;
1289
1290         clrsetbits_le32(rcc + RCC_HSICFGR,
1291                         RCC_HSICFGR_HSIDIV_MASK,
1292                         RCC_HSICFGR_HSIDIV_MASK & hsidiv);
1293
1294         ret = readl_poll_timeout(address, val,
1295                                  val & RCC_OCRDYR_HSIDIVRDY,
1296                                  TIMEOUT_200MS);
1297         if (ret)
1298                 pr_err("HSIDIV failed @ 0x%x: 0x%x\n",
1299                        address, readl(address));
1300
1301         return ret;
1302 }
1303
1304 static int stm32mp1_hsidiv(fdt_addr_t rcc, ulong hsifreq)
1305 {
1306         u8 hsidiv;
1307         u32 hsidivfreq = MAX_HSI_HZ;
1308
1309         for (hsidiv = 0; hsidiv < 4; hsidiv++,
1310              hsidivfreq = hsidivfreq / 2)
1311                 if (hsidivfreq == hsifreq)
1312                         break;
1313
1314         if (hsidiv == 4) {
1315                 pr_err("clk-hsi frequency invalid");
1316                 return -1;
1317         }
1318
1319         if (hsidiv > 0)
1320                 return stm32mp1_set_hsidiv(rcc, hsidiv);
1321
1322         return 0;
1323 }
1324
1325 static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id)
1326 {
1327         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1328
1329         clrsetbits_le32(priv->base + pll[pll_id].pllxcr,
1330                         RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN |
1331                         RCC_PLLNCR_DIVREN,
1332                         RCC_PLLNCR_PLLON);
1333 }
1334
1335 static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output)
1336 {
1337         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1338         u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1339         u32 val;
1340         int ret;
1341
1342         ret = readl_poll_timeout(pllxcr, val, val & RCC_PLLNCR_PLLRDY,
1343                                  TIMEOUT_200MS);
1344
1345         if (ret) {
1346                 pr_err("PLL%d start failed @ 0x%x: 0x%x\n",
1347                        pll_id, pllxcr, readl(pllxcr));
1348                 return ret;
1349         }
1350
1351         /* start the requested output */
1352         setbits_le32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT);
1353
1354         return 0;
1355 }
1356
1357 static int pll_stop(struct stm32mp1_clk_priv *priv, int pll_id)
1358 {
1359         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1360         u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1361         u32 val;
1362
1363         /* stop all output */
1364         clrbits_le32(pllxcr,
1365                      RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN);
1366
1367         /* stop PLL */
1368         clrbits_le32(pllxcr, RCC_PLLNCR_PLLON);
1369
1370         /* wait PLL stopped */
1371         return readl_poll_timeout(pllxcr, val, (val & RCC_PLLNCR_PLLRDY) == 0,
1372                                   TIMEOUT_200MS);
1373 }
1374
1375 static void pll_config_output(struct stm32mp1_clk_priv *priv,
1376                               int pll_id, u32 *pllcfg)
1377 {
1378         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1379         fdt_addr_t rcc = priv->base;
1380         u32 value;
1381
1382         value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT)
1383                 & RCC_PLLNCFGR2_DIVP_MASK;
1384         value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT)
1385                  & RCC_PLLNCFGR2_DIVQ_MASK;
1386         value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT)
1387                  & RCC_PLLNCFGR2_DIVR_MASK;
1388         writel(value, rcc + pll[pll_id].pllxcfgr2);
1389 }
1390
1391 static int pll_config(struct stm32mp1_clk_priv *priv, int pll_id,
1392                       u32 *pllcfg, u32 fracv)
1393 {
1394         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1395         fdt_addr_t rcc = priv->base;
1396         enum stm32mp1_plltype type = pll[pll_id].plltype;
1397         int src;
1398         ulong refclk;
1399         u8 ifrge = 0;
1400         u32 value;
1401
1402         src = readl(priv->base + pll[pll_id].rckxselr) & RCC_SELR_SRC_MASK;
1403
1404         refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]) /
1405                  (pllcfg[PLLCFG_M] + 1);
1406
1407         if (refclk < (stm32mp1_pll[type].refclk_min * 1000000) ||
1408             refclk > (stm32mp1_pll[type].refclk_max * 1000000)) {
1409                 debug("invalid refclk = %x\n", (u32)refclk);
1410                 return -EINVAL;
1411         }
1412         if (type == PLL_800 && refclk >= 8000000)
1413                 ifrge = 1;
1414
1415         value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT)
1416                  & RCC_PLLNCFGR1_DIVN_MASK;
1417         value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT)
1418                  & RCC_PLLNCFGR1_DIVM_MASK;
1419         value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT)
1420                  & RCC_PLLNCFGR1_IFRGE_MASK;
1421         writel(value, rcc + pll[pll_id].pllxcfgr1);
1422
1423         /* fractional configuration: load sigma-delta modulator (SDM) */
1424
1425         /* Write into FRACV the new fractional value , and FRACLE to 0 */
1426         writel(fracv << RCC_PLLNFRACR_FRACV_SHIFT,
1427                rcc + pll[pll_id].pllxfracr);
1428
1429         /* Write FRACLE to 1 : FRACV value is loaded into the SDM */
1430         setbits_le32(rcc + pll[pll_id].pllxfracr,
1431                      RCC_PLLNFRACR_FRACLE);
1432
1433         pll_config_output(priv, pll_id, pllcfg);
1434
1435         return 0;
1436 }
1437
1438 static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg)
1439 {
1440         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1441         u32 pllxcsg;
1442
1443         pllxcsg = ((csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) &
1444                     RCC_PLLNCSGR_MOD_PER_MASK) |
1445                   ((csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) &
1446                     RCC_PLLNCSGR_INC_STEP_MASK) |
1447                   ((csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) &
1448                     RCC_PLLNCSGR_SSCG_MODE_MASK);
1449
1450         writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr);
1451
1452         setbits_le32(priv->base + pll[pll_id].pllxcr, RCC_PLLNCR_SSCG_CTRL);
1453 }
1454
1455 static  __maybe_unused int pll_set_rate(struct udevice *dev,
1456                                         int pll_id,
1457                                         int div_id,
1458                                         unsigned long clk_rate)
1459 {
1460         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1461         unsigned int pllcfg[PLLCFG_NB];
1462         ofnode plloff;
1463         char name[12];
1464         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1465         enum stm32mp1_plltype type = pll[pll_id].plltype;
1466         int divm, divn, divy;
1467         int ret;
1468         ulong fck_ref;
1469         u32 fracv;
1470         u64 value;
1471
1472         if (div_id > _DIV_NB)
1473                 return -EINVAL;
1474
1475         sprintf(name, "st,pll@%d", pll_id);
1476         plloff = dev_read_subnode(dev, name);
1477         if (!ofnode_valid(plloff))
1478                 return -FDT_ERR_NOTFOUND;
1479
1480         ret = ofnode_read_u32_array(plloff, "cfg",
1481                                     pllcfg, PLLCFG_NB);
1482         if (ret < 0)
1483                 return -FDT_ERR_NOTFOUND;
1484
1485         fck_ref = pll_get_fref_ck(priv, pll_id);
1486
1487         divm = pllcfg[PLLCFG_M];
1488         /* select output divider = 0: for _DIV_P, 1:_DIV_Q 2:_DIV_R */
1489         divy = pllcfg[PLLCFG_P + div_id];
1490
1491         /* For: PLL1 & PLL2 => VCO is * 2 but ck_pll_y is also / 2
1492          * So same final result than PLL2 et 4
1493          * with FRACV
1494          * Fck_pll_y = Fck_ref * ((DIVN + 1) + FRACV / 2^13)
1495          *             / (DIVy + 1) * (DIVM + 1)
1496          * value = (DIVN + 1) * 2^13 + FRACV / 2^13
1497          *       = Fck_pll_y (DIVy + 1) * (DIVM + 1) * 2^13 / Fck_ref
1498          */
1499         value = ((u64)clk_rate * (divy + 1) * (divm + 1)) << 13;
1500         value = lldiv(value, fck_ref);
1501
1502         divn = (value >> 13) - 1;
1503         if (divn < DIVN_MIN ||
1504             divn > stm32mp1_pll[type].divn_max) {
1505                 pr_err("divn invalid = %d", divn);
1506                 return -EINVAL;
1507         }
1508         fracv = value - ((divn + 1) << 13);
1509         pllcfg[PLLCFG_N] = divn;
1510
1511         /* reconfigure PLL */
1512         pll_stop(priv, pll_id);
1513         pll_config(priv, pll_id, pllcfg, fracv);
1514         pll_start(priv, pll_id);
1515         pll_output(priv, pll_id, pllcfg[PLLCFG_O]);
1516
1517         return 0;
1518 }
1519
1520 static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc)
1521 {
1522         u32 address = priv->base + (clksrc >> 4);
1523         u32 val;
1524         int ret;
1525
1526         clrsetbits_le32(address, RCC_SELR_SRC_MASK, clksrc & RCC_SELR_SRC_MASK);
1527         ret = readl_poll_timeout(address, val, val & RCC_SELR_SRCRDY,
1528                                  TIMEOUT_200MS);
1529         if (ret)
1530                 pr_err("CLKSRC %x start failed @ 0x%x: 0x%x\n",
1531                        clksrc, address, readl(address));
1532
1533         return ret;
1534 }
1535
1536 static void stgen_config(struct stm32mp1_clk_priv *priv)
1537 {
1538         int p;
1539         u32 stgenc, cntfid0;
1540         ulong rate;
1541
1542         stgenc = STM32_STGEN_BASE;
1543         cntfid0 = readl(stgenc + STGENC_CNTFID0);
1544         p = stm32mp1_clk_get_parent(priv, STGEN_K);
1545         rate = stm32mp1_clk_get(priv, p);
1546
1547         if (cntfid0 != rate) {
1548                 u64 counter;
1549
1550                 pr_debug("System Generic Counter (STGEN) update\n");
1551                 clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1552                 counter = (u64)readl(stgenc + STGENC_CNTCVL);
1553                 counter |= ((u64)(readl(stgenc + STGENC_CNTCVU))) << 32;
1554                 counter = lldiv(counter * (u64)rate, cntfid0);
1555                 writel((u32)counter, stgenc + STGENC_CNTCVL);
1556                 writel((u32)(counter >> 32), stgenc + STGENC_CNTCVU);
1557                 writel(rate, stgenc + STGENC_CNTFID0);
1558                 setbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1559
1560                 __asm__ volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (rate));
1561
1562                 /* need to update gd->arch.timer_rate_hz with new frequency */
1563                 timer_init();
1564         }
1565 }
1566
1567 static int set_clkdiv(unsigned int clkdiv, u32 address)
1568 {
1569         u32 val;
1570         int ret;
1571
1572         clrsetbits_le32(address, RCC_DIVR_DIV_MASK, clkdiv & RCC_DIVR_DIV_MASK);
1573         ret = readl_poll_timeout(address, val, val & RCC_DIVR_DIVRDY,
1574                                  TIMEOUT_200MS);
1575         if (ret)
1576                 pr_err("CLKDIV %x start failed @ 0x%x: 0x%x\n",
1577                        clkdiv, address, readl(address));
1578
1579         return ret;
1580 }
1581
1582 static void stm32mp1_mco_csg(struct stm32mp1_clk_priv *priv,
1583                              u32 clksrc, u32 clkdiv)
1584 {
1585         u32 address = priv->base + (clksrc >> 4);
1586
1587         /*
1588          * binding clksrc : bit15-4 offset
1589          *                  bit3:   disable
1590          *                  bit2-0: MCOSEL[2:0]
1591          */
1592         if (clksrc & 0x8) {
1593                 clrbits_le32(address, RCC_MCOCFG_MCOON);
1594         } else {
1595                 clrsetbits_le32(address,
1596                                 RCC_MCOCFG_MCOSRC_MASK,
1597                                 clksrc & RCC_MCOCFG_MCOSRC_MASK);
1598                 clrsetbits_le32(address,
1599                                 RCC_MCOCFG_MCODIV_MASK,
1600                                 clkdiv << RCC_MCOCFG_MCODIV_SHIFT);
1601                 setbits_le32(address, RCC_MCOCFG_MCOON);
1602         }
1603 }
1604
1605 static void set_rtcsrc(struct stm32mp1_clk_priv *priv,
1606                        unsigned int clksrc,
1607                        int lse_css)
1608 {
1609         u32 address = priv->base + RCC_BDCR;
1610
1611         if (readl(address) & RCC_BDCR_RTCCKEN)
1612                 goto skip_rtc;
1613
1614         if (clksrc == CLK_RTC_DISABLED)
1615                 goto skip_rtc;
1616
1617         clrsetbits_le32(address,
1618                         RCC_BDCR_RTCSRC_MASK,
1619                         clksrc << RCC_BDCR_RTCSRC_SHIFT);
1620
1621         setbits_le32(address, RCC_BDCR_RTCCKEN);
1622
1623 skip_rtc:
1624         if (lse_css)
1625                 setbits_le32(address, RCC_BDCR_LSECSSON);
1626 }
1627
1628 static void pkcs_config(struct stm32mp1_clk_priv *priv, u32 pkcs)
1629 {
1630         u32 address = priv->base + ((pkcs >> 4) & 0xFFF);
1631         u32 value = pkcs & 0xF;
1632         u32 mask = 0xF;
1633
1634         if (pkcs & BIT(31)) {
1635                 mask <<= 4;
1636                 value <<= 4;
1637         }
1638         clrsetbits_le32(address, mask, value);
1639 }
1640
1641 static int stm32mp1_clktree(struct udevice *dev)
1642 {
1643         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1644         fdt_addr_t rcc = priv->base;
1645         unsigned int clksrc[CLKSRC_NB];
1646         unsigned int clkdiv[CLKDIV_NB];
1647         unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
1648         ofnode plloff[_PLL_NB];
1649         int ret;
1650         int i, len;
1651         int lse_css = 0;
1652         const u32 *pkcs_cell;
1653
1654         /* check mandatory field */
1655         ret = dev_read_u32_array(dev, "st,clksrc", clksrc, CLKSRC_NB);
1656         if (ret < 0) {
1657                 debug("field st,clksrc invalid: error %d\n", ret);
1658                 return -FDT_ERR_NOTFOUND;
1659         }
1660
1661         ret = dev_read_u32_array(dev, "st,clkdiv", clkdiv, CLKDIV_NB);
1662         if (ret < 0) {
1663                 debug("field st,clkdiv invalid: error %d\n", ret);
1664                 return -FDT_ERR_NOTFOUND;
1665         }
1666
1667         /* check mandatory field in each pll */
1668         for (i = 0; i < _PLL_NB; i++) {
1669                 char name[12];
1670
1671                 sprintf(name, "st,pll@%d", i);
1672                 plloff[i] = dev_read_subnode(dev, name);
1673                 if (!ofnode_valid(plloff[i]))
1674                         continue;
1675                 ret = ofnode_read_u32_array(plloff[i], "cfg",
1676                                             pllcfg[i], PLLCFG_NB);
1677                 if (ret < 0) {
1678                         debug("field cfg invalid: error %d\n", ret);
1679                         return -FDT_ERR_NOTFOUND;
1680                 }
1681         }
1682
1683         debug("configuration MCO\n");
1684         stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]);
1685         stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]);
1686
1687         debug("switch ON osillator\n");
1688         /*
1689          * switch ON oscillator found in device-tree,
1690          * HSI already ON after bootrom
1691          */
1692         if (priv->osc[_LSI])
1693                 stm32mp1_lsi_set(rcc, 1);
1694
1695         if (priv->osc[_LSE]) {
1696                 int bypass, digbyp, lsedrv;
1697                 struct udevice *dev = priv->osc_dev[_LSE];
1698
1699                 bypass = dev_read_bool(dev, "st,bypass");
1700                 digbyp = dev_read_bool(dev, "st,digbypass");
1701                 lse_css = dev_read_bool(dev, "st,css");
1702                 lsedrv = dev_read_u32_default(dev, "st,drive",
1703                                               LSEDRV_MEDIUM_HIGH);
1704
1705                 stm32mp1_lse_enable(rcc, bypass, digbyp, lsedrv);
1706         }
1707
1708         if (priv->osc[_HSE]) {
1709                 int bypass, digbyp, css;
1710                 struct udevice *dev = priv->osc_dev[_HSE];
1711
1712                 bypass = dev_read_bool(dev, "st,bypass");
1713                 digbyp = dev_read_bool(dev, "st,digbypass");
1714                 css = dev_read_bool(dev, "st,css");
1715
1716                 stm32mp1_hse_enable(rcc, bypass, digbyp, css);
1717         }
1718         /* CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR)
1719          * => switch on CSI even if node is not present in device tree
1720          */
1721         stm32mp1_csi_set(rcc, 1);
1722
1723         /* come back to HSI */
1724         debug("come back to HSI\n");
1725         set_clksrc(priv, CLK_MPU_HSI);
1726         set_clksrc(priv, CLK_AXI_HSI);
1727         set_clksrc(priv, CLK_MCU_HSI);
1728
1729         debug("pll stop\n");
1730         for (i = 0; i < _PLL_NB; i++)
1731                 pll_stop(priv, i);
1732
1733         /* configure HSIDIV */
1734         debug("configure HSIDIV\n");
1735         if (priv->osc[_HSI]) {
1736                 stm32mp1_hsidiv(rcc, priv->osc[_HSI]);
1737                 stgen_config(priv);
1738         }
1739
1740         /* select DIV */
1741         debug("select DIV\n");
1742         /* no ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */
1743         writel(clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK, rcc + RCC_MPCKDIVR);
1744         set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR);
1745         set_clkdiv(clkdiv[CLKDIV_APB4], rcc + RCC_APB4DIVR);
1746         set_clkdiv(clkdiv[CLKDIV_APB5], rcc + RCC_APB5DIVR);
1747         set_clkdiv(clkdiv[CLKDIV_MCU], rcc + RCC_MCUDIVR);
1748         set_clkdiv(clkdiv[CLKDIV_APB1], rcc + RCC_APB1DIVR);
1749         set_clkdiv(clkdiv[CLKDIV_APB2], rcc + RCC_APB2DIVR);
1750         set_clkdiv(clkdiv[CLKDIV_APB3], rcc + RCC_APB3DIVR);
1751
1752         /* no ready bit for RTC */
1753         writel(clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK, rcc + RCC_RTCDIVR);
1754
1755         /* configure PLLs source */
1756         debug("configure PLLs source\n");
1757         set_clksrc(priv, clksrc[CLKSRC_PLL12]);
1758         set_clksrc(priv, clksrc[CLKSRC_PLL3]);
1759         set_clksrc(priv, clksrc[CLKSRC_PLL4]);
1760
1761         /* configure and start PLLs */
1762         debug("configure PLLs\n");
1763         for (i = 0; i < _PLL_NB; i++) {
1764                 u32 fracv;
1765                 u32 csg[PLLCSG_NB];
1766
1767                 debug("configure PLL %d @ %d\n", i,
1768                       ofnode_to_offset(plloff[i]));
1769                 if (!ofnode_valid(plloff[i]))
1770                         continue;
1771
1772                 fracv = ofnode_read_u32_default(plloff[i], "frac", 0);
1773                 pll_config(priv, i, pllcfg[i], fracv);
1774                 ret = ofnode_read_u32_array(plloff[i], "csg", csg, PLLCSG_NB);
1775                 if (!ret) {
1776                         pll_csg(priv, i, csg);
1777                 } else if (ret != -FDT_ERR_NOTFOUND) {
1778                         debug("invalid csg node for pll@%d res=%d\n", i, ret);
1779                         return ret;
1780                 }
1781                 pll_start(priv, i);
1782         }
1783
1784         /* wait and start PLLs ouptut when ready */
1785         for (i = 0; i < _PLL_NB; i++) {
1786                 if (!ofnode_valid(plloff[i]))
1787                         continue;
1788                 debug("output PLL %d\n", i);
1789                 pll_output(priv, i, pllcfg[i][PLLCFG_O]);
1790         }
1791
1792         /* wait LSE ready before to use it */
1793         if (priv->osc[_LSE])
1794                 stm32mp1_lse_wait(rcc);
1795
1796         /* configure with expected clock source */
1797         debug("CLKSRC\n");
1798         set_clksrc(priv, clksrc[CLKSRC_MPU]);
1799         set_clksrc(priv, clksrc[CLKSRC_AXI]);
1800         set_clksrc(priv, clksrc[CLKSRC_MCU]);
1801         set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css);
1802
1803         /* configure PKCK */
1804         debug("PKCK\n");
1805         pkcs_cell = dev_read_prop(dev, "st,pkcs", &len);
1806         if (pkcs_cell) {
1807                 bool ckper_disabled = false;
1808
1809                 for (i = 0; i < len / sizeof(u32); i++) {
1810                         u32 pkcs = (u32)fdt32_to_cpu(pkcs_cell[i]);
1811
1812                         if (pkcs == CLK_CKPER_DISABLED) {
1813                                 ckper_disabled = true;
1814                                 continue;
1815                         }
1816                         pkcs_config(priv, pkcs);
1817                 }
1818                 /* CKPER is source for some peripheral clock
1819                  * (FMC-NAND / QPSI-NOR) and switching source is allowed
1820                  * only if previous clock is still ON
1821                  * => deactivated CKPER only after switching clock
1822                  */
1823                 if (ckper_disabled)
1824                         pkcs_config(priv, CLK_CKPER_DISABLED);
1825         }
1826
1827         /* STGEN clock source can change with CLK_STGEN_XXX */
1828         stgen_config(priv);
1829
1830         debug("oscillator off\n");
1831         /* switch OFF HSI if not found in device-tree */
1832         if (!priv->osc[_HSI])
1833                 stm32mp1_hsi_set(rcc, 0);
1834
1835         /* Software Self-Refresh mode (SSR) during DDR initilialization */
1836         clrsetbits_le32(priv->base + RCC_DDRITFCR,
1837                         RCC_DDRITFCR_DDRCKMOD_MASK,
1838                         RCC_DDRITFCR_DDRCKMOD_SSR <<
1839                         RCC_DDRITFCR_DDRCKMOD_SHIFT);
1840
1841         return 0;
1842 }
1843 #endif /* STM32MP1_CLOCK_TREE_INIT */
1844
1845 static int pll_set_output_rate(struct udevice *dev,
1846                                int pll_id,
1847                                int div_id,
1848                                unsigned long clk_rate)
1849 {
1850         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1851         const struct stm32mp1_clk_pll *pll = priv->data->pll;
1852         u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1853         int div;
1854         ulong fvco;
1855
1856         if (div_id > _DIV_NB)
1857                 return -EINVAL;
1858
1859         fvco = pll_get_fvco(priv, pll_id);
1860
1861         if (fvco <= clk_rate)
1862                 div = 1;
1863         else
1864                 div = DIV_ROUND_UP(fvco, clk_rate);
1865
1866         if (div > 128)
1867                 div = 128;
1868
1869         /* stop the requested output */
1870         clrbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
1871         /* change divider */
1872         clrsetbits_le32(priv->base + pll[pll_id].pllxcfgr2,
1873                         RCC_PLLNCFGR2_DIVX_MASK << RCC_PLLNCFGR2_SHIFT(div_id),
1874                         (div - 1) << RCC_PLLNCFGR2_SHIFT(div_id));
1875         /* start the requested output */
1876         setbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
1877
1878         return 0;
1879 }
1880
1881 static ulong stm32mp1_clk_set_rate(struct clk *clk, unsigned long clk_rate)
1882 {
1883         struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1884         int p;
1885
1886         switch (clk->id) {
1887 #if defined(STM32MP1_CLOCK_TREE_INIT) && \
1888         defined(CONFIG_STM32MP1_DDR_INTERACTIVE)
1889         case DDRPHYC:
1890                 break;
1891 #endif
1892         case LTDC_PX:
1893         case DSI_PX:
1894                 break;
1895         default:
1896                 pr_err("not supported");
1897                 return -EINVAL;
1898         }
1899
1900         p = stm32mp1_clk_get_parent(priv, clk->id);
1901 #ifdef DEBUG
1902         debug("%s: parent = %d:%s\n", __func__, p, stm32mp1_clk_parent_name[p]);
1903 #endif
1904         if (p < 0)
1905                 return -EINVAL;
1906
1907         switch (p) {
1908 #if defined(STM32MP1_CLOCK_TREE_INIT) && \
1909         defined(CONFIG_STM32MP1_DDR_INTERACTIVE)
1910         case _PLL2_R: /* DDRPHYC */
1911         {
1912                 /* only for change DDR clock in interactive mode */
1913                 ulong result;
1914
1915                 set_clksrc(priv, CLK_AXI_HSI);
1916                 result = pll_set_rate(clk->dev,  _PLL2, _DIV_R, clk_rate);
1917                 set_clksrc(priv, CLK_AXI_PLL2P);
1918                 return result;
1919         }
1920 #endif
1921
1922         case _PLL4_Q:
1923                 /* for LTDC_PX and DSI_PX case */
1924                 return pll_set_output_rate(clk->dev, _PLL4, _DIV_Q, clk_rate);
1925         }
1926
1927         return -EINVAL;
1928 }
1929
1930 static void stm32mp1_osc_clk_init(const char *name,
1931                                   struct stm32mp1_clk_priv *priv,
1932                                   int index)
1933 {
1934         struct clk clk;
1935         struct udevice *dev = NULL;
1936
1937         priv->osc[index] = 0;
1938         clk.id = 0;
1939         if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) {
1940                 if (clk_request(dev, &clk))
1941                         pr_err("%s request", name);
1942                 else
1943                         priv->osc[index] = clk_get_rate(&clk);
1944         }
1945         priv->osc_dev[index] = dev;
1946 }
1947
1948 static void stm32mp1_osc_init(struct udevice *dev)
1949 {
1950         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1951         int i;
1952         const char *name[NB_OSC] = {
1953                 [_LSI] = "clk-lsi",
1954                 [_LSE] = "clk-lse",
1955                 [_HSI] = "clk-hsi",
1956                 [_HSE] = "clk-hse",
1957                 [_CSI] = "clk-csi",
1958                 [_I2S_CKIN] = "i2s_ckin",
1959         };
1960
1961         for (i = 0; i < NB_OSC; i++) {
1962                 stm32mp1_osc_clk_init(name[i], priv, i);
1963                 debug("%d: %s => %x\n", i, name[i], (u32)priv->osc[i]);
1964         }
1965 }
1966
1967 static void  __maybe_unused stm32mp1_clk_dump(struct stm32mp1_clk_priv *priv)
1968 {
1969         char buf[32];
1970         int i, s, p;
1971
1972         printf("Clocks:\n");
1973         for (i = 0; i < _PARENT_NB; i++) {
1974                 printf("- %s : %s MHz\n",
1975                        stm32mp1_clk_parent_name[i],
1976                        strmhz(buf, stm32mp1_clk_get(priv, i)));
1977         }
1978         printf("Source Clocks:\n");
1979         for (i = 0; i < _PARENT_SEL_NB; i++) {
1980                 p = (readl(priv->base + priv->data->sel[i].offset) >>
1981                      priv->data->sel[i].src) & priv->data->sel[i].msk;
1982                 if (p < priv->data->sel[i].nb_parent) {
1983                         s = priv->data->sel[i].parent[p];
1984                         printf("- %s(%d) => parent %s(%d)\n",
1985                                stm32mp1_clk_parent_sel_name[i], i,
1986                                stm32mp1_clk_parent_name[s], s);
1987                 } else {
1988                         printf("- %s(%d) => parent index %d is invalid\n",
1989                                stm32mp1_clk_parent_sel_name[i], i, p);
1990                 }
1991         }
1992 }
1993
1994 #ifdef CONFIG_CMD_CLK
1995 int soc_clk_dump(void)
1996 {
1997         struct udevice *dev;
1998         struct stm32mp1_clk_priv *priv;
1999         int ret;
2000
2001         ret = uclass_get_device_by_driver(UCLASS_CLK,
2002                                           DM_GET_DRIVER(stm32mp1_clock),
2003                                           &dev);
2004         if (ret)
2005                 return ret;
2006
2007         priv = dev_get_priv(dev);
2008
2009         stm32mp1_clk_dump(priv);
2010
2011         return 0;
2012 }
2013 #endif
2014
2015 static int stm32mp1_clk_probe(struct udevice *dev)
2016 {
2017         int result = 0;
2018         struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
2019
2020         priv->base = dev_read_addr(dev->parent);
2021         if (priv->base == FDT_ADDR_T_NONE)
2022                 return -EINVAL;
2023
2024         priv->data = (void *)&stm32mp1_data;
2025
2026         if (!priv->data->gate || !priv->data->sel ||
2027             !priv->data->pll)
2028                 return -EINVAL;
2029
2030         stm32mp1_osc_init(dev);
2031
2032 #ifdef STM32MP1_CLOCK_TREE_INIT
2033         /* clock tree init is done only one time, before relocation */
2034         if (!(gd->flags & GD_FLG_RELOC))
2035                 result = stm32mp1_clktree(dev);
2036 #endif
2037
2038 #ifndef CONFIG_SPL_BUILD
2039 #if defined(DEBUG)
2040         /* display debug information for probe after relocation */
2041         if (gd->flags & GD_FLG_RELOC)
2042                 stm32mp1_clk_dump(priv);
2043 #endif
2044
2045 #if defined(CONFIG_DISPLAY_CPUINFO)
2046         if (gd->flags & GD_FLG_RELOC) {
2047                 char buf[32];
2048
2049                 printf("Clocks:\n");
2050                 printf("- MPU : %s MHz\n",
2051                        strmhz(buf, stm32mp1_clk_get(priv, _CK_MPU)));
2052                 printf("- MCU : %s MHz\n",
2053                        strmhz(buf, stm32mp1_clk_get(priv, _CK_MCU)));
2054                 printf("- AXI : %s MHz\n",
2055                        strmhz(buf, stm32mp1_clk_get(priv, _ACLK)));
2056                 printf("- PER : %s MHz\n",
2057                        strmhz(buf, stm32mp1_clk_get(priv, _CK_PER)));
2058                 /* DDRPHYC father */
2059                 printf("- DDR : %s MHz\n",
2060                        strmhz(buf, stm32mp1_clk_get(priv, _PLL2_R)));
2061         }
2062 #endif /* CONFIG_DISPLAY_CPUINFO */
2063 #endif
2064
2065         return result;
2066 }
2067
2068 static const struct clk_ops stm32mp1_clk_ops = {
2069         .enable = stm32mp1_clk_enable,
2070         .disable = stm32mp1_clk_disable,
2071         .get_rate = stm32mp1_clk_get_rate,
2072         .set_rate = stm32mp1_clk_set_rate,
2073 };
2074
2075 U_BOOT_DRIVER(stm32mp1_clock) = {
2076         .name = "stm32mp1_clk",
2077         .id = UCLASS_CLK,
2078         .ops = &stm32mp1_clk_ops,
2079         .priv_auto_alloc_size = sizeof(struct stm32mp1_clk_priv),
2080         .probe = stm32mp1_clk_probe,
2081 };