1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
7 #include <clk-uclass.h>
14 #include <linux/iopoll.h>
15 #include <dt-bindings/clock/stm32mp1-clks.h>
16 #include <dt-bindings/clock/stm32mp1-clksrc.h>
18 #ifndef CONFIG_STM32MP1_TRUSTED
19 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
20 /* activate clock tree initialization in the driver */
21 #define STM32MP1_CLOCK_TREE_INIT
25 #define MAX_HSI_HZ 64000000
28 #define TIMEOUT_200MS 200000
29 #define TIMEOUT_1S 1000000
32 #define STGENC_CNTCR 0x00
33 #define STGENC_CNTSR 0x04
34 #define STGENC_CNTCVL 0x08
35 #define STGENC_CNTCVU 0x0C
36 #define STGENC_CNTFID0 0x20
38 #define STGENC_CNTCR_EN BIT(0)
41 #define RCC_OCENSETR 0x0C
42 #define RCC_OCENCLRR 0x10
43 #define RCC_HSICFGR 0x18
44 #define RCC_MPCKSELR 0x20
45 #define RCC_ASSCKSELR 0x24
46 #define RCC_RCK12SELR 0x28
47 #define RCC_MPCKDIVR 0x2C
48 #define RCC_AXIDIVR 0x30
49 #define RCC_APB4DIVR 0x3C
50 #define RCC_APB5DIVR 0x40
51 #define RCC_RTCDIVR 0x44
52 #define RCC_MSSCKSELR 0x48
53 #define RCC_PLL1CR 0x80
54 #define RCC_PLL1CFGR1 0x84
55 #define RCC_PLL1CFGR2 0x88
56 #define RCC_PLL1FRACR 0x8C
57 #define RCC_PLL1CSGR 0x90
58 #define RCC_PLL2CR 0x94
59 #define RCC_PLL2CFGR1 0x98
60 #define RCC_PLL2CFGR2 0x9C
61 #define RCC_PLL2FRACR 0xA0
62 #define RCC_PLL2CSGR 0xA4
63 #define RCC_I2C46CKSELR 0xC0
64 #define RCC_CPERCKSELR 0xD0
65 #define RCC_STGENCKSELR 0xD4
66 #define RCC_DDRITFCR 0xD8
67 #define RCC_BDCR 0x140
68 #define RCC_RDLSICR 0x144
69 #define RCC_MP_APB4ENSETR 0x200
70 #define RCC_MP_APB5ENSETR 0x208
71 #define RCC_MP_AHB5ENSETR 0x210
72 #define RCC_MP_AHB6ENSETR 0x218
73 #define RCC_OCRDYR 0x808
74 #define RCC_DBGCFGR 0x80C
75 #define RCC_RCK3SELR 0x820
76 #define RCC_RCK4SELR 0x824
77 #define RCC_MCUDIVR 0x830
78 #define RCC_APB1DIVR 0x834
79 #define RCC_APB2DIVR 0x838
80 #define RCC_APB3DIVR 0x83C
81 #define RCC_PLL3CR 0x880
82 #define RCC_PLL3CFGR1 0x884
83 #define RCC_PLL3CFGR2 0x888
84 #define RCC_PLL3FRACR 0x88C
85 #define RCC_PLL3CSGR 0x890
86 #define RCC_PLL4CR 0x894
87 #define RCC_PLL4CFGR1 0x898
88 #define RCC_PLL4CFGR2 0x89C
89 #define RCC_PLL4FRACR 0x8A0
90 #define RCC_PLL4CSGR 0x8A4
91 #define RCC_I2C12CKSELR 0x8C0
92 #define RCC_I2C35CKSELR 0x8C4
93 #define RCC_UART6CKSELR 0x8E4
94 #define RCC_UART24CKSELR 0x8E8
95 #define RCC_UART35CKSELR 0x8EC
96 #define RCC_UART78CKSELR 0x8F0
97 #define RCC_SDMMC12CKSELR 0x8F4
98 #define RCC_SDMMC3CKSELR 0x8F8
99 #define RCC_ETHCKSELR 0x8FC
100 #define RCC_QSPICKSELR 0x900
101 #define RCC_FMCCKSELR 0x904
102 #define RCC_USBCKSELR 0x91C
103 #define RCC_DSICKSELR 0x924
104 #define RCC_ADCCKSELR 0x928
105 #define RCC_MP_APB1ENSETR 0xA00
106 #define RCC_MP_APB2ENSETR 0XA08
107 #define RCC_MP_APB3ENSETR 0xA10
108 #define RCC_MP_AHB2ENSETR 0xA18
109 #define RCC_MP_AHB3ENSETR 0xA20
110 #define RCC_MP_AHB4ENSETR 0xA28
112 /* used for most of SELR register */
113 #define RCC_SELR_SRC_MASK GENMASK(2, 0)
114 #define RCC_SELR_SRCRDY BIT(31)
116 /* Values of RCC_MPCKSELR register */
117 #define RCC_MPCKSELR_HSI 0
118 #define RCC_MPCKSELR_HSE 1
119 #define RCC_MPCKSELR_PLL 2
120 #define RCC_MPCKSELR_PLL_MPUDIV 3
122 /* Values of RCC_ASSCKSELR register */
123 #define RCC_ASSCKSELR_HSI 0
124 #define RCC_ASSCKSELR_HSE 1
125 #define RCC_ASSCKSELR_PLL 2
127 /* Values of RCC_MSSCKSELR register */
128 #define RCC_MSSCKSELR_HSI 0
129 #define RCC_MSSCKSELR_HSE 1
130 #define RCC_MSSCKSELR_CSI 2
131 #define RCC_MSSCKSELR_PLL 3
133 /* Values of RCC_CPERCKSELR register */
134 #define RCC_CPERCKSELR_HSI 0
135 #define RCC_CPERCKSELR_CSI 1
136 #define RCC_CPERCKSELR_HSE 2
138 /* used for most of DIVR register : max div for RTC */
139 #define RCC_DIVR_DIV_MASK GENMASK(5, 0)
140 #define RCC_DIVR_DIVRDY BIT(31)
142 /* Masks for specific DIVR registers */
143 #define RCC_APBXDIV_MASK GENMASK(2, 0)
144 #define RCC_MPUDIV_MASK GENMASK(2, 0)
145 #define RCC_AXIDIV_MASK GENMASK(2, 0)
146 #define RCC_MCUDIV_MASK GENMASK(3, 0)
148 /* offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
149 #define RCC_MP_ENCLRR_OFFSET 4
151 /* Fields of RCC_BDCR register */
152 #define RCC_BDCR_LSEON BIT(0)
153 #define RCC_BDCR_LSEBYP BIT(1)
154 #define RCC_BDCR_LSERDY BIT(2)
155 #define RCC_BDCR_DIGBYP BIT(3)
156 #define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4)
157 #define RCC_BDCR_LSEDRV_SHIFT 4
158 #define RCC_BDCR_LSECSSON BIT(8)
159 #define RCC_BDCR_RTCCKEN BIT(20)
160 #define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16)
161 #define RCC_BDCR_RTCSRC_SHIFT 16
163 /* Fields of RCC_RDLSICR register */
164 #define RCC_RDLSICR_LSION BIT(0)
165 #define RCC_RDLSICR_LSIRDY BIT(1)
167 /* used for ALL PLLNCR registers */
168 #define RCC_PLLNCR_PLLON BIT(0)
169 #define RCC_PLLNCR_PLLRDY BIT(1)
170 #define RCC_PLLNCR_SSCG_CTRL BIT(2)
171 #define RCC_PLLNCR_DIVPEN BIT(4)
172 #define RCC_PLLNCR_DIVQEN BIT(5)
173 #define RCC_PLLNCR_DIVREN BIT(6)
174 #define RCC_PLLNCR_DIVEN_SHIFT 4
176 /* used for ALL PLLNCFGR1 registers */
177 #define RCC_PLLNCFGR1_DIVM_SHIFT 16
178 #define RCC_PLLNCFGR1_DIVM_MASK GENMASK(21, 16)
179 #define RCC_PLLNCFGR1_DIVN_SHIFT 0
180 #define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0)
181 /* only for PLL3 and PLL4 */
182 #define RCC_PLLNCFGR1_IFRGE_SHIFT 24
183 #define RCC_PLLNCFGR1_IFRGE_MASK GENMASK(25, 24)
185 /* used for ALL PLLNCFGR2 registers , using stm32mp1_div_id */
186 #define RCC_PLLNCFGR2_SHIFT(div_id) ((div_id) * 8)
187 #define RCC_PLLNCFGR2_DIVX_MASK GENMASK(6, 0)
188 #define RCC_PLLNCFGR2_DIVP_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_P)
189 #define RCC_PLLNCFGR2_DIVP_MASK GENMASK(6, 0)
190 #define RCC_PLLNCFGR2_DIVQ_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_Q)
191 #define RCC_PLLNCFGR2_DIVQ_MASK GENMASK(14, 8)
192 #define RCC_PLLNCFGR2_DIVR_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_R)
193 #define RCC_PLLNCFGR2_DIVR_MASK GENMASK(22, 16)
195 /* used for ALL PLLNFRACR registers */
196 #define RCC_PLLNFRACR_FRACV_SHIFT 3
197 #define RCC_PLLNFRACR_FRACV_MASK GENMASK(15, 3)
198 #define RCC_PLLNFRACR_FRACLE BIT(16)
200 /* used for ALL PLLNCSGR registers */
201 #define RCC_PLLNCSGR_INC_STEP_SHIFT 16
202 #define RCC_PLLNCSGR_INC_STEP_MASK GENMASK(30, 16)
203 #define RCC_PLLNCSGR_MOD_PER_SHIFT 0
204 #define RCC_PLLNCSGR_MOD_PER_MASK GENMASK(12, 0)
205 #define RCC_PLLNCSGR_SSCG_MODE_SHIFT 15
206 #define RCC_PLLNCSGR_SSCG_MODE_MASK BIT(15)
208 /* used for RCC_OCENSETR and RCC_OCENCLRR registers */
209 #define RCC_OCENR_HSION BIT(0)
210 #define RCC_OCENR_CSION BIT(4)
211 #define RCC_OCENR_DIGBYP BIT(7)
212 #define RCC_OCENR_HSEON BIT(8)
213 #define RCC_OCENR_HSEBYP BIT(10)
214 #define RCC_OCENR_HSECSSON BIT(11)
216 /* Fields of RCC_OCRDYR register */
217 #define RCC_OCRDYR_HSIRDY BIT(0)
218 #define RCC_OCRDYR_HSIDIVRDY BIT(2)
219 #define RCC_OCRDYR_CSIRDY BIT(4)
220 #define RCC_OCRDYR_HSERDY BIT(8)
222 /* Fields of DDRITFCR register */
223 #define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20)
224 #define RCC_DDRITFCR_DDRCKMOD_SHIFT 20
225 #define RCC_DDRITFCR_DDRCKMOD_SSR 0
227 /* Fields of RCC_HSICFGR register */
228 #define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0)
230 /* used for MCO related operations */
231 #define RCC_MCOCFG_MCOON BIT(12)
232 #define RCC_MCOCFG_MCODIV_MASK GENMASK(7, 4)
233 #define RCC_MCOCFG_MCODIV_SHIFT 4
234 #define RCC_MCOCFG_MCOSRC_MASK GENMASK(2, 0)
236 enum stm32mp1_parent_id {
238 * _HSI, _HSE, _CSI, _LSI, _LSE should not be moved
239 * they are used as index in osc[] as entry point
249 /* other parent source */
283 enum stm32mp1_parent_sel {
305 enum stm32mp1_pll_id {
313 enum stm32mp1_div_id {
320 enum stm32mp1_clksrc_id {
333 enum stm32mp1_clkdiv_id {
348 enum stm32mp1_pllcfg {
358 enum stm32mp1_pllcsg {
365 enum stm32mp1_plltype {
371 struct stm32mp1_pll {
377 struct stm32mp1_clk_gate {
386 struct stm32mp1_clk_sel {
394 #define REFCLK_SIZE 4
395 struct stm32mp1_clk_pll {
396 enum stm32mp1_plltype plltype;
403 u8 refclk[REFCLK_SIZE];
406 struct stm32mp1_clk_data {
407 const struct stm32mp1_clk_gate *gate;
408 const struct stm32mp1_clk_sel *sel;
409 const struct stm32mp1_clk_pll *pll;
413 struct stm32mp1_clk_priv {
415 const struct stm32mp1_clk_data *data;
417 struct udevice *osc_dev[NB_OSC];
420 #define STM32MP1_CLK(off, b, idx, s) \
427 .fixed = _UNKNOWN_ID, \
430 #define STM32MP1_CLK_F(off, b, idx, f) \
436 .sel = _UNKNOWN_SEL, \
440 #define STM32MP1_CLK_SET_CLR(off, b, idx, s) \
447 .fixed = _UNKNOWN_ID, \
450 #define STM32MP1_CLK_SET_CLR_F(off, b, idx, f) \
456 .sel = _UNKNOWN_SEL, \
460 #define STM32MP1_CLK_PARENT(idx, off, s, m, p) \
466 .nb_parent = ARRAY_SIZE((p)) \
469 #define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, off4, off5, off6,\
473 .rckxselr = (off1), \
474 .pllxcfgr1 = (off2), \
475 .pllxcfgr2 = (off3), \
476 .pllxfracr = (off4), \
478 .pllxcsgr = (off6), \
485 static const u8 stm32mp1_clks[][2] = {
495 {CK_HSE_DIV2, _HSE_KER_DIV2},
498 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
499 STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL),
500 STM32MP1_CLK(RCC_DDRITFCR, 1, DDRC1LP, _UNKNOWN_SEL),
501 STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL),
502 STM32MP1_CLK(RCC_DDRITFCR, 3, DDRC2LP, _UNKNOWN_SEL),
503 STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
504 STM32MP1_CLK(RCC_DDRITFCR, 5, DDRPHYCLP, _UNKNOWN_SEL),
505 STM32MP1_CLK(RCC_DDRITFCR, 6, DDRCAPB, _UNKNOWN_SEL),
506 STM32MP1_CLK(RCC_DDRITFCR, 7, DDRCAPBLP, _UNKNOWN_SEL),
507 STM32MP1_CLK(RCC_DDRITFCR, 8, AXIDCG, _UNKNOWN_SEL),
508 STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL),
509 STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL),
511 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
512 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
513 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
514 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL),
515 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL),
516 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL),
517 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL),
518 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL),
519 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL),
520 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
522 STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
524 STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3),
526 STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 0, LTDC_PX, _PLL4_Q),
527 STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 4, DSI_PX, _PLL4_Q),
528 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 4, DSI_K, _DSI_SEL),
529 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
530 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
531 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
533 STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
534 STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
536 STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB2ENSETR, 5, ADC12, _HCLK2),
537 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 5, ADC12_K, _ADC12_SEL),
538 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
539 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
541 STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 11, HSEM, _UNKNOWN_SEL),
542 STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 12, IPCC, _UNKNOWN_SEL),
544 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
545 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
546 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
547 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL),
548 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL),
549 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL),
550 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL),
551 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL),
552 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL),
553 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL),
554 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
556 STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
558 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK, _ETH_SEL),
559 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL),
560 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL),
561 STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK),
562 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
563 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
564 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL),
565 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL),
566 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL),
568 STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
571 static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
572 static const u8 i2c35_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
573 static const u8 i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER};
574 static const u8 uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
576 static const u8 uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
578 static const u8 uart35_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
580 static const u8 uart78_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
582 static const u8 sdmmc12_parents[] = {_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER};
583 static const u8 sdmmc3_parents[] = {_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER};
584 static const u8 eth_parents[] = {_PLL4_P, _PLL3_Q};
585 static const u8 qspi_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
586 static const u8 fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
587 static const u8 usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2};
588 static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48};
589 static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER};
590 static const u8 dsi_parents[] = {_DSI_PHY, _PLL4_P};
591 static const u8 adc_parents[] = {_PLL4_R, _CK_PER, _PLL3_Q};
593 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
594 STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents),
595 STM32MP1_CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents),
596 STM32MP1_CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents),
597 STM32MP1_CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents),
598 STM32MP1_CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7,
600 STM32MP1_CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7,
602 STM32MP1_CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7,
604 STM32MP1_CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7,
606 STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7,
608 STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents),
609 STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents),
610 STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents),
611 STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents),
612 STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
613 STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
614 STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents),
615 STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x1, adc_parents),
618 #ifdef STM32MP1_CLOCK_TREE_INIT
619 /* define characteristic of PLL according type */
621 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
633 #endif /* STM32MP1_CLOCK_TREE_INIT */
635 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = {
636 STM32MP1_CLK_PLL(_PLL1, PLL_1600,
637 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2,
638 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR,
639 _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
640 STM32MP1_CLK_PLL(_PLL2, PLL_1600,
641 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2,
642 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR,
643 _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
644 STM32MP1_CLK_PLL(_PLL3, PLL_800,
645 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2,
646 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR,
647 _HSI, _HSE, _CSI, _UNKNOWN_ID),
648 STM32MP1_CLK_PLL(_PLL4, PLL_800,
649 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2,
650 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR,
651 _HSI, _HSE, _CSI, _I2S_CKIN),
654 /* Prescaler table lookups for clock computation */
655 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */
656 static const u8 stm32mp1_mcu_div[16] = {
657 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9
660 /* div = /1 /2 /4 /8 /16 : same divider for pmu and apbx*/
661 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div
662 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div
663 static const u8 stm32mp1_mpu_apbx_div[8] = {
664 0, 1, 2, 3, 4, 4, 4, 4
667 /* div = /1 /2 /3 /4 */
668 static const u8 stm32mp1_axi_div[8] = {
669 1, 2, 3, 4, 4, 4, 4, 4
672 static const __maybe_unused
673 char * const stm32mp1_clk_parent_name[_PARENT_NB] = {
679 [_I2S_CKIN] = "I2S_CKIN",
680 [_HSI_KER] = "HSI_KER",
681 [_HSE_KER] = "HSE_KER",
682 [_HSE_KER_DIV2] = "HSE_KER_DIV2",
683 [_CSI_KER] = "CSI_KER",
684 [_PLL1_P] = "PLL1_P",
685 [_PLL1_Q] = "PLL1_Q",
686 [_PLL1_R] = "PLL1_R",
687 [_PLL2_P] = "PLL2_P",
688 [_PLL2_Q] = "PLL2_Q",
689 [_PLL2_R] = "PLL2_R",
690 [_PLL3_P] = "PLL3_P",
691 [_PLL3_Q] = "PLL3_Q",
692 [_PLL3_R] = "PLL3_R",
693 [_PLL4_P] = "PLL4_P",
694 [_PLL4_Q] = "PLL4_Q",
695 [_PLL4_R] = "PLL4_R",
704 [_CK_PER] = "CK_PER",
705 [_CK_MPU] = "CK_MPU",
706 [_CK_MCU] = "CK_MCU",
707 [_USB_PHY_48] = "USB_PHY_48",
708 [_DSI_PHY] = "DSI_PHY_PLL",
711 static const __maybe_unused
712 char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
713 [_I2C12_SEL] = "I2C12",
714 [_I2C35_SEL] = "I2C35",
715 [_I2C46_SEL] = "I2C46",
716 [_UART6_SEL] = "UART6",
717 [_UART24_SEL] = "UART24",
718 [_UART35_SEL] = "UART35",
719 [_UART78_SEL] = "UART78",
720 [_SDMMC12_SEL] = "SDMMC12",
721 [_SDMMC3_SEL] = "SDMMC3",
723 [_QSPI_SEL] = "QSPI",
725 [_USBPHY_SEL] = "USBPHY",
726 [_USBO_SEL] = "USBO",
727 [_STGEN_SEL] = "STGEN",
729 [_ADC12_SEL] = "ADC12",
732 static const struct stm32mp1_clk_data stm32mp1_data = {
733 .gate = stm32mp1_clk_gate,
734 .sel = stm32mp1_clk_sel,
735 .pll = stm32mp1_clk_pll,
736 .nb_gate = ARRAY_SIZE(stm32mp1_clk_gate),
739 static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx)
742 debug("%s: clk id %d not found\n", __func__, idx);
746 debug("%s: clk id %d = %x : %ld kHz\n", __func__, idx,
747 (u32)priv->osc[idx], priv->osc[idx] / 1000);
749 return priv->osc[idx];
752 static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id)
754 const struct stm32mp1_clk_gate *gate = priv->data->gate;
755 int i, nb_clks = priv->data->nb_gate;
757 for (i = 0; i < nb_clks; i++) {
758 if (gate[i].index == id)
763 printf("%s: clk id %d not found\n", __func__, (u32)id);
770 static int stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv,
773 const struct stm32mp1_clk_gate *gate = priv->data->gate;
775 if (gate[i].sel > _PARENT_SEL_NB) {
776 printf("%s: parents for clk id %d not found\n",
784 static int stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv *priv,
787 const struct stm32mp1_clk_gate *gate = priv->data->gate;
789 if (gate[i].fixed == _UNKNOWN_ID)
792 return gate[i].fixed;
795 static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv,
798 const struct stm32mp1_clk_sel *sel = priv->data->sel;
802 for (i = 0; i < ARRAY_SIZE(stm32mp1_clks); i++)
803 if (stm32mp1_clks[i][0] == id)
804 return stm32mp1_clks[i][1];
806 i = stm32mp1_clk_get_id(priv, id);
810 p = stm32mp1_clk_get_fixed_parent(priv, i);
811 if (p >= 0 && p < _PARENT_NB)
814 s = stm32mp1_clk_get_sel(priv, i);
818 p = (readl(priv->base + sel[s].offset) >> sel[s].src) & sel[s].msk;
820 if (p < sel[s].nb_parent) {
822 debug("%s: %s clock is the parent %s of clk id %d\n", __func__,
823 stm32mp1_clk_parent_name[sel[s].parent[p]],
824 stm32mp1_clk_parent_sel_name[s],
827 return sel[s].parent[p];
830 pr_err("%s: no parents defined for clk id %d\n",
836 static ulong pll_get_fref_ck(struct stm32mp1_clk_priv *priv,
839 const struct stm32mp1_clk_pll *pll = priv->data->pll;
844 /* Get current refclk */
845 selr = readl(priv->base + pll[pll_id].rckxselr);
846 src = selr & RCC_SELR_SRC_MASK;
848 refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]);
849 debug("PLL%d : selr=%x refclk = %d kHz\n",
850 pll_id, selr, (u32)(refclk / 1000));
856 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL
857 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1)
858 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1)
859 * => in all the case Fpll_y_ck = pll_get_fvco() / (DIVy + 1)
861 static ulong pll_get_fvco(struct stm32mp1_clk_priv *priv,
864 const struct stm32mp1_clk_pll *pll = priv->data->pll;
869 cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1);
870 fracr = readl(priv->base + pll[pll_id].pllxfracr);
872 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
873 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
875 debug("PLL%d : cfgr1=%x fracr=%x DIVN=%d DIVM=%d\n",
876 pll_id, cfgr1, fracr, divn, divm);
878 refclk = pll_get_fref_ck(priv, pll_id);
881 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1)
883 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1)
885 if (fracr & RCC_PLLNFRACR_FRACLE) {
886 u32 fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK)
887 >> RCC_PLLNFRACR_FRACV_SHIFT;
888 fvco = (ulong)lldiv((unsigned long long)refclk *
889 (((divn + 1) << 13) + fracv),
890 ((unsigned long long)(divm + 1)) << 13);
892 fvco = (ulong)(refclk * (divn + 1) / (divm + 1));
894 debug("PLL%d : %s = %ld\n", pll_id, __func__, fvco);
899 static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
900 int pll_id, int div_id)
902 const struct stm32mp1_clk_pll *pll = priv->data->pll;
907 debug("%s(%d, %d)\n", __func__, pll_id, div_id);
908 if (div_id >= _DIV_NB)
911 cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2);
912 divy = (cfgr2 >> RCC_PLLNCFGR2_SHIFT(div_id)) & RCC_PLLNCFGR2_DIVX_MASK;
914 debug("PLL%d : cfgr2=%x DIVY=%d\n", pll_id, cfgr2, divy);
916 dfout = pll_get_fvco(priv, pll_id) / (divy + 1);
917 debug(" => dfout = %d kHz\n", (u32)(dfout / 1000));
922 static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
930 reg = readl(priv->base + RCC_MPCKSELR);
931 switch (reg & RCC_SELR_SRC_MASK) {
932 case RCC_MPCKSELR_HSI:
933 clock = stm32mp1_clk_get_fixed(priv, _HSI);
935 case RCC_MPCKSELR_HSE:
936 clock = stm32mp1_clk_get_fixed(priv, _HSE);
938 case RCC_MPCKSELR_PLL:
939 case RCC_MPCKSELR_PLL_MPUDIV:
940 clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P);
941 if (p == RCC_MPCKSELR_PLL_MPUDIV) {
942 reg = readl(priv->base + RCC_MPCKDIVR);
943 clock /= stm32mp1_mpu_div[reg &
955 reg = readl(priv->base + RCC_ASSCKSELR);
956 switch (reg & RCC_SELR_SRC_MASK) {
957 case RCC_ASSCKSELR_HSI:
958 clock = stm32mp1_clk_get_fixed(priv, _HSI);
960 case RCC_ASSCKSELR_HSE:
961 clock = stm32mp1_clk_get_fixed(priv, _HSE);
963 case RCC_ASSCKSELR_PLL:
964 clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P);
968 /* System clock divider */
969 reg = readl(priv->base + RCC_AXIDIVR);
970 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK];
974 reg = readl(priv->base + RCC_APB4DIVR);
975 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
978 reg = readl(priv->base + RCC_APB5DIVR);
979 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
990 reg = readl(priv->base + RCC_MSSCKSELR);
991 switch (reg & RCC_SELR_SRC_MASK) {
992 case RCC_MSSCKSELR_HSI:
993 clock = stm32mp1_clk_get_fixed(priv, _HSI);
995 case RCC_MSSCKSELR_HSE:
996 clock = stm32mp1_clk_get_fixed(priv, _HSE);
998 case RCC_MSSCKSELR_CSI:
999 clock = stm32mp1_clk_get_fixed(priv, _CSI);
1001 case RCC_MSSCKSELR_PLL:
1002 clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_P);
1006 /* MCU clock divider */
1007 reg = readl(priv->base + RCC_MCUDIVR);
1008 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK];
1012 reg = readl(priv->base + RCC_APB1DIVR);
1013 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1016 reg = readl(priv->base + RCC_APB2DIVR);
1017 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1020 reg = readl(priv->base + RCC_APB3DIVR);
1021 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1029 reg = readl(priv->base + RCC_CPERCKSELR);
1030 switch (reg & RCC_SELR_SRC_MASK) {
1031 case RCC_CPERCKSELR_HSI:
1032 clock = stm32mp1_clk_get_fixed(priv, _HSI);
1034 case RCC_CPERCKSELR_HSE:
1035 clock = stm32mp1_clk_get_fixed(priv, _HSE);
1037 case RCC_CPERCKSELR_CSI:
1038 clock = stm32mp1_clk_get_fixed(priv, _CSI);
1044 clock = stm32mp1_clk_get_fixed(priv, _HSI);
1048 clock = stm32mp1_clk_get_fixed(priv, _CSI);
1053 clock = stm32mp1_clk_get_fixed(priv, _HSE);
1054 if (p == _HSE_KER_DIV2)
1058 clock = stm32mp1_clk_get_fixed(priv, _LSI);
1061 clock = stm32mp1_clk_get_fixed(priv, _LSE);
1067 clock = stm32mp1_read_pll_freq(priv, _PLL1, p - _PLL1_P);
1072 clock = stm32mp1_read_pll_freq(priv, _PLL2, p - _PLL2_P);
1077 clock = stm32mp1_read_pll_freq(priv, _PLL3, p - _PLL3_P);
1082 clock = stm32mp1_read_pll_freq(priv, _PLL4, p - _PLL4_P);
1091 struct udevice *dev = NULL;
1093 if (!uclass_get_device_by_name(UCLASS_CLK, "ck_dsi_phy",
1095 if (clk_request(dev, &clk)) {
1096 pr_err("ck_dsi_phy request");
1099 clock = clk_get_rate(&clk);
1108 debug("%s(%d) clock = %lx : %ld kHz\n",
1109 __func__, p, clock, clock / 1000);
1114 static int stm32mp1_clk_enable(struct clk *clk)
1116 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1117 const struct stm32mp1_clk_gate *gate = priv->data->gate;
1118 int i = stm32mp1_clk_get_id(priv, clk->id);
1123 if (gate[i].set_clr)
1124 writel(BIT(gate[i].bit), priv->base + gate[i].offset);
1126 setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1128 debug("%s: id clock %d has been enabled\n", __func__, (u32)clk->id);
1133 static int stm32mp1_clk_disable(struct clk *clk)
1135 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1136 const struct stm32mp1_clk_gate *gate = priv->data->gate;
1137 int i = stm32mp1_clk_get_id(priv, clk->id);
1142 if (gate[i].set_clr)
1143 writel(BIT(gate[i].bit),
1144 priv->base + gate[i].offset
1145 + RCC_MP_ENCLRR_OFFSET);
1147 clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1149 debug("%s: id clock %d has been disabled\n", __func__, (u32)clk->id);
1154 static ulong stm32mp1_clk_get_rate(struct clk *clk)
1156 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1157 int p = stm32mp1_clk_get_parent(priv, clk->id);
1163 rate = stm32mp1_clk_get(priv, p);
1166 debug("%s: computed rate for id clock %d is %d (parent is %s)\n",
1167 __func__, (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]);
1172 #ifdef STM32MP1_CLOCK_TREE_INIT
1173 static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset,
1176 u32 address = rcc + offset;
1179 setbits_le32(address, mask_on);
1181 clrbits_le32(address, mask_on);
1184 static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on)
1186 writel(mask_on, rcc + (enable ? RCC_OCENSETR : RCC_OCENCLRR));
1189 static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset,
1193 u32 address = rcc + offset;
1198 mask_test = mask_rdy;
1200 ret = readl_poll_timeout(address, val,
1201 (val & mask_rdy) == mask_test,
1205 pr_err("OSC %x @ %x timeout for enable=%d : 0x%x\n",
1206 mask_rdy, address, enable, readl(address));
1211 static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int digbyp,
1217 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_DIGBYP);
1219 if (bypass || digbyp)
1220 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP);
1223 * warning: not recommended to switch directly from "high drive"
1224 * to "medium low drive", and vice-versa.
1226 value = (readl(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK)
1227 >> RCC_BDCR_LSEDRV_SHIFT;
1229 while (value != lsedrv) {
1235 clrsetbits_le32(rcc + RCC_BDCR,
1236 RCC_BDCR_LSEDRV_MASK,
1237 value << RCC_BDCR_LSEDRV_SHIFT);
1240 stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON);
1243 static void stm32mp1_lse_wait(fdt_addr_t rcc)
1245 stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY);
1248 static void stm32mp1_lsi_set(fdt_addr_t rcc, int enable)
1250 stm32mp1_ls_osc_set(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSION);
1251 stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY);
1254 static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int digbyp, int css)
1257 writel(RCC_OCENR_DIGBYP, rcc + RCC_OCENSETR);
1258 if (bypass || digbyp)
1259 writel(RCC_OCENR_HSEBYP, rcc + RCC_OCENSETR);
1261 stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON);
1262 stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY);
1265 writel(RCC_OCENR_HSECSSON, rcc + RCC_OCENSETR);
1268 static void stm32mp1_csi_set(fdt_addr_t rcc, int enable)
1270 stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_CSION);
1271 stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY);
1274 static void stm32mp1_hsi_set(fdt_addr_t rcc, int enable)
1276 stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_HSION);
1277 stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_HSIRDY);
1280 static int stm32mp1_set_hsidiv(fdt_addr_t rcc, u8 hsidiv)
1282 u32 address = rcc + RCC_OCRDYR;
1286 clrsetbits_le32(rcc + RCC_HSICFGR,
1287 RCC_HSICFGR_HSIDIV_MASK,
1288 RCC_HSICFGR_HSIDIV_MASK & hsidiv);
1290 ret = readl_poll_timeout(address, val,
1291 val & RCC_OCRDYR_HSIDIVRDY,
1294 pr_err("HSIDIV failed @ 0x%x: 0x%x\n",
1295 address, readl(address));
1300 static int stm32mp1_hsidiv(fdt_addr_t rcc, ulong hsifreq)
1303 u32 hsidivfreq = MAX_HSI_HZ;
1305 for (hsidiv = 0; hsidiv < 4; hsidiv++,
1306 hsidivfreq = hsidivfreq / 2)
1307 if (hsidivfreq == hsifreq)
1311 pr_err("clk-hsi frequency invalid");
1316 return stm32mp1_set_hsidiv(rcc, hsidiv);
1321 static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id)
1323 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1325 clrsetbits_le32(priv->base + pll[pll_id].pllxcr,
1326 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN |
1331 static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output)
1333 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1334 u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1338 ret = readl_poll_timeout(pllxcr, val, val & RCC_PLLNCR_PLLRDY,
1342 pr_err("PLL%d start failed @ 0x%x: 0x%x\n",
1343 pll_id, pllxcr, readl(pllxcr));
1347 /* start the requested output */
1348 setbits_le32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT);
1353 static int pll_stop(struct stm32mp1_clk_priv *priv, int pll_id)
1355 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1356 u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1359 /* stop all output */
1360 clrbits_le32(pllxcr,
1361 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN);
1364 clrbits_le32(pllxcr, RCC_PLLNCR_PLLON);
1366 /* wait PLL stopped */
1367 return readl_poll_timeout(pllxcr, val, (val & RCC_PLLNCR_PLLRDY) == 0,
1371 static void pll_config_output(struct stm32mp1_clk_priv *priv,
1372 int pll_id, u32 *pllcfg)
1374 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1375 fdt_addr_t rcc = priv->base;
1378 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT)
1379 & RCC_PLLNCFGR2_DIVP_MASK;
1380 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT)
1381 & RCC_PLLNCFGR2_DIVQ_MASK;
1382 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT)
1383 & RCC_PLLNCFGR2_DIVR_MASK;
1384 writel(value, rcc + pll[pll_id].pllxcfgr2);
1387 static int pll_config(struct stm32mp1_clk_priv *priv, int pll_id,
1388 u32 *pllcfg, u32 fracv)
1390 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1391 fdt_addr_t rcc = priv->base;
1392 enum stm32mp1_plltype type = pll[pll_id].plltype;
1398 src = readl(priv->base + pll[pll_id].rckxselr) & RCC_SELR_SRC_MASK;
1400 refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]) /
1401 (pllcfg[PLLCFG_M] + 1);
1403 if (refclk < (stm32mp1_pll[type].refclk_min * 1000000) ||
1404 refclk > (stm32mp1_pll[type].refclk_max * 1000000)) {
1405 debug("invalid refclk = %x\n", (u32)refclk);
1408 if (type == PLL_800 && refclk >= 8000000)
1411 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT)
1412 & RCC_PLLNCFGR1_DIVN_MASK;
1413 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT)
1414 & RCC_PLLNCFGR1_DIVM_MASK;
1415 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT)
1416 & RCC_PLLNCFGR1_IFRGE_MASK;
1417 writel(value, rcc + pll[pll_id].pllxcfgr1);
1419 /* fractional configuration: load sigma-delta modulator (SDM) */
1421 /* Write into FRACV the new fractional value , and FRACLE to 0 */
1422 writel(fracv << RCC_PLLNFRACR_FRACV_SHIFT,
1423 rcc + pll[pll_id].pllxfracr);
1425 /* Write FRACLE to 1 : FRACV value is loaded into the SDM */
1426 setbits_le32(rcc + pll[pll_id].pllxfracr,
1427 RCC_PLLNFRACR_FRACLE);
1429 pll_config_output(priv, pll_id, pllcfg);
1434 static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg)
1436 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1439 pllxcsg = ((csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) &
1440 RCC_PLLNCSGR_MOD_PER_MASK) |
1441 ((csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) &
1442 RCC_PLLNCSGR_INC_STEP_MASK) |
1443 ((csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) &
1444 RCC_PLLNCSGR_SSCG_MODE_MASK);
1446 writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr);
1448 setbits_le32(priv->base + pll[pll_id].pllxcr, RCC_PLLNCR_SSCG_CTRL);
1451 static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc)
1453 u32 address = priv->base + (clksrc >> 4);
1457 clrsetbits_le32(address, RCC_SELR_SRC_MASK, clksrc & RCC_SELR_SRC_MASK);
1458 ret = readl_poll_timeout(address, val, val & RCC_SELR_SRCRDY,
1461 pr_err("CLKSRC %x start failed @ 0x%x: 0x%x\n",
1462 clksrc, address, readl(address));
1467 static void stgen_config(struct stm32mp1_clk_priv *priv)
1470 u32 stgenc, cntfid0;
1473 stgenc = (u32)syscon_get_first_range(STM32MP_SYSCON_STGEN);
1475 cntfid0 = readl(stgenc + STGENC_CNTFID0);
1476 p = stm32mp1_clk_get_parent(priv, STGEN_K);
1477 rate = stm32mp1_clk_get(priv, p);
1479 if (cntfid0 != rate) {
1482 pr_debug("System Generic Counter (STGEN) update\n");
1483 clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1484 counter = (u64)readl(stgenc + STGENC_CNTCVL);
1485 counter |= ((u64)(readl(stgenc + STGENC_CNTCVU))) << 32;
1486 counter = lldiv(counter * (u64)rate, cntfid0);
1487 writel((u32)counter, stgenc + STGENC_CNTCVL);
1488 writel((u32)(counter >> 32), stgenc + STGENC_CNTCVU);
1489 writel(rate, stgenc + STGENC_CNTFID0);
1490 setbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1492 __asm__ volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (rate));
1494 /* need to update gd->arch.timer_rate_hz with new frequency */
1496 pr_debug("gd->arch.timer_rate_hz = %x\n",
1497 (u32)gd->arch.timer_rate_hz);
1498 pr_debug("Tick = %x\n", (u32)(get_ticks()));
1502 static int set_clkdiv(unsigned int clkdiv, u32 address)
1507 clrsetbits_le32(address, RCC_DIVR_DIV_MASK, clkdiv & RCC_DIVR_DIV_MASK);
1508 ret = readl_poll_timeout(address, val, val & RCC_DIVR_DIVRDY,
1511 pr_err("CLKDIV %x start failed @ 0x%x: 0x%x\n",
1512 clkdiv, address, readl(address));
1517 static void stm32mp1_mco_csg(struct stm32mp1_clk_priv *priv,
1518 u32 clksrc, u32 clkdiv)
1520 u32 address = priv->base + (clksrc >> 4);
1523 * binding clksrc : bit15-4 offset
1525 * bit2-0: MCOSEL[2:0]
1528 clrbits_le32(address, RCC_MCOCFG_MCOON);
1530 clrsetbits_le32(address,
1531 RCC_MCOCFG_MCOSRC_MASK,
1532 clksrc & RCC_MCOCFG_MCOSRC_MASK);
1533 clrsetbits_le32(address,
1534 RCC_MCOCFG_MCODIV_MASK,
1535 clkdiv << RCC_MCOCFG_MCODIV_SHIFT);
1536 setbits_le32(address, RCC_MCOCFG_MCOON);
1540 static void set_rtcsrc(struct stm32mp1_clk_priv *priv,
1541 unsigned int clksrc,
1544 u32 address = priv->base + RCC_BDCR;
1546 if (readl(address) & RCC_BDCR_RTCCKEN)
1549 if (clksrc == CLK_RTC_DISABLED)
1552 clrsetbits_le32(address,
1553 RCC_BDCR_RTCSRC_MASK,
1554 clksrc << RCC_BDCR_RTCSRC_SHIFT);
1556 setbits_le32(address, RCC_BDCR_RTCCKEN);
1560 setbits_le32(address, RCC_BDCR_LSECSSON);
1563 static void pkcs_config(struct stm32mp1_clk_priv *priv, u32 pkcs)
1565 u32 address = priv->base + ((pkcs >> 4) & 0xFFF);
1566 u32 value = pkcs & 0xF;
1569 if (pkcs & BIT(31)) {
1573 clrsetbits_le32(address, mask, value);
1576 static int stm32mp1_clktree(struct udevice *dev)
1578 struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1579 fdt_addr_t rcc = priv->base;
1580 unsigned int clksrc[CLKSRC_NB];
1581 unsigned int clkdiv[CLKDIV_NB];
1582 unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
1583 ofnode plloff[_PLL_NB];
1587 const u32 *pkcs_cell;
1589 /* check mandatory field */
1590 ret = dev_read_u32_array(dev, "st,clksrc", clksrc, CLKSRC_NB);
1592 debug("field st,clksrc invalid: error %d\n", ret);
1593 return -FDT_ERR_NOTFOUND;
1596 ret = dev_read_u32_array(dev, "st,clkdiv", clkdiv, CLKDIV_NB);
1598 debug("field st,clkdiv invalid: error %d\n", ret);
1599 return -FDT_ERR_NOTFOUND;
1602 /* check mandatory field in each pll */
1603 for (i = 0; i < _PLL_NB; i++) {
1606 sprintf(name, "st,pll@%d", i);
1607 plloff[i] = dev_read_subnode(dev, name);
1608 if (!ofnode_valid(plloff[i]))
1610 ret = ofnode_read_u32_array(plloff[i], "cfg",
1611 pllcfg[i], PLLCFG_NB);
1613 debug("field cfg invalid: error %d\n", ret);
1614 return -FDT_ERR_NOTFOUND;
1618 debug("configuration MCO\n");
1619 stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]);
1620 stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]);
1622 debug("switch ON osillator\n");
1624 * switch ON oscillator found in device-tree,
1625 * HSI already ON after bootrom
1627 if (priv->osc[_LSI])
1628 stm32mp1_lsi_set(rcc, 1);
1630 if (priv->osc[_LSE]) {
1631 int bypass, digbyp, lsedrv;
1632 struct udevice *dev = priv->osc_dev[_LSE];
1634 bypass = dev_read_bool(dev, "st,bypass");
1635 digbyp = dev_read_bool(dev, "st,digbypass");
1636 lse_css = dev_read_bool(dev, "st,css");
1637 lsedrv = dev_read_u32_default(dev, "st,drive",
1638 LSEDRV_MEDIUM_HIGH);
1640 stm32mp1_lse_enable(rcc, bypass, digbyp, lsedrv);
1643 if (priv->osc[_HSE]) {
1644 int bypass, digbyp, css;
1645 struct udevice *dev = priv->osc_dev[_HSE];
1647 bypass = dev_read_bool(dev, "st,bypass");
1648 digbyp = dev_read_bool(dev, "st,digbypass");
1649 css = dev_read_bool(dev, "st,css");
1651 stm32mp1_hse_enable(rcc, bypass, digbyp, css);
1653 /* CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR)
1654 * => switch on CSI even if node is not present in device tree
1656 stm32mp1_csi_set(rcc, 1);
1658 /* come back to HSI */
1659 debug("come back to HSI\n");
1660 set_clksrc(priv, CLK_MPU_HSI);
1661 set_clksrc(priv, CLK_AXI_HSI);
1662 set_clksrc(priv, CLK_MCU_HSI);
1664 debug("pll stop\n");
1665 for (i = 0; i < _PLL_NB; i++)
1668 /* configure HSIDIV */
1669 debug("configure HSIDIV\n");
1670 if (priv->osc[_HSI]) {
1671 stm32mp1_hsidiv(rcc, priv->osc[_HSI]);
1676 debug("select DIV\n");
1677 /* no ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */
1678 writel(clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK, rcc + RCC_MPCKDIVR);
1679 set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR);
1680 set_clkdiv(clkdiv[CLKDIV_APB4], rcc + RCC_APB4DIVR);
1681 set_clkdiv(clkdiv[CLKDIV_APB5], rcc + RCC_APB5DIVR);
1682 set_clkdiv(clkdiv[CLKDIV_MCU], rcc + RCC_MCUDIVR);
1683 set_clkdiv(clkdiv[CLKDIV_APB1], rcc + RCC_APB1DIVR);
1684 set_clkdiv(clkdiv[CLKDIV_APB2], rcc + RCC_APB2DIVR);
1685 set_clkdiv(clkdiv[CLKDIV_APB3], rcc + RCC_APB3DIVR);
1687 /* no ready bit for RTC */
1688 writel(clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK, rcc + RCC_RTCDIVR);
1690 /* configure PLLs source */
1691 debug("configure PLLs source\n");
1692 set_clksrc(priv, clksrc[CLKSRC_PLL12]);
1693 set_clksrc(priv, clksrc[CLKSRC_PLL3]);
1694 set_clksrc(priv, clksrc[CLKSRC_PLL4]);
1696 /* configure and start PLLs */
1697 debug("configure PLLs\n");
1698 for (i = 0; i < _PLL_NB; i++) {
1702 debug("configure PLL %d @ %d\n", i,
1703 ofnode_to_offset(plloff[i]));
1704 if (!ofnode_valid(plloff[i]))
1707 fracv = ofnode_read_u32_default(plloff[i], "frac", 0);
1708 pll_config(priv, i, pllcfg[i], fracv);
1709 ret = ofnode_read_u32_array(plloff[i], "csg", csg, PLLCSG_NB);
1711 pll_csg(priv, i, csg);
1712 } else if (ret != -FDT_ERR_NOTFOUND) {
1713 debug("invalid csg node for pll@%d res=%d\n", i, ret);
1719 /* wait and start PLLs ouptut when ready */
1720 for (i = 0; i < _PLL_NB; i++) {
1721 if (!ofnode_valid(plloff[i]))
1723 debug("output PLL %d\n", i);
1724 pll_output(priv, i, pllcfg[i][PLLCFG_O]);
1727 /* wait LSE ready before to use it */
1728 if (priv->osc[_LSE])
1729 stm32mp1_lse_wait(rcc);
1731 /* configure with expected clock source */
1733 set_clksrc(priv, clksrc[CLKSRC_MPU]);
1734 set_clksrc(priv, clksrc[CLKSRC_AXI]);
1735 set_clksrc(priv, clksrc[CLKSRC_MCU]);
1736 set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css);
1738 /* configure PKCK */
1740 pkcs_cell = dev_read_prop(dev, "st,pkcs", &len);
1742 bool ckper_disabled = false;
1744 for (i = 0; i < len / sizeof(u32); i++) {
1745 u32 pkcs = (u32)fdt32_to_cpu(pkcs_cell[i]);
1747 if (pkcs == CLK_CKPER_DISABLED) {
1748 ckper_disabled = true;
1751 pkcs_config(priv, pkcs);
1753 /* CKPER is source for some peripheral clock
1754 * (FMC-NAND / QPSI-NOR) and switching source is allowed
1755 * only if previous clock is still ON
1756 * => deactivated CKPER only after switching clock
1759 pkcs_config(priv, CLK_CKPER_DISABLED);
1762 /* STGEN clock source can change with CLK_STGEN_XXX */
1765 debug("oscillator off\n");
1766 /* switch OFF HSI if not found in device-tree */
1767 if (!priv->osc[_HSI])
1768 stm32mp1_hsi_set(rcc, 0);
1770 /* Software Self-Refresh mode (SSR) during DDR initilialization */
1771 clrsetbits_le32(priv->base + RCC_DDRITFCR,
1772 RCC_DDRITFCR_DDRCKMOD_MASK,
1773 RCC_DDRITFCR_DDRCKMOD_SSR <<
1774 RCC_DDRITFCR_DDRCKMOD_SHIFT);
1778 #endif /* STM32MP1_CLOCK_TREE_INIT */
1780 static int pll_set_output_rate(struct udevice *dev,
1783 unsigned long clk_rate)
1785 struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1786 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1787 u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1791 if (div_id > _DIV_NB)
1794 fvco = pll_get_fvco(priv, pll_id);
1796 if (fvco <= clk_rate)
1799 div = DIV_ROUND_UP(fvco, clk_rate);
1804 debug("fvco = %ld, clk_rate = %ld, div=%d\n", fvco, clk_rate, div);
1805 /* stop the requested output */
1806 clrbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
1807 /* change divider */
1808 clrsetbits_le32(priv->base + pll[pll_id].pllxcfgr2,
1809 RCC_PLLNCFGR2_DIVX_MASK << RCC_PLLNCFGR2_SHIFT(div_id),
1810 (div - 1) << RCC_PLLNCFGR2_SHIFT(div_id));
1811 /* start the requested output */
1812 setbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
1817 static ulong stm32mp1_clk_set_rate(struct clk *clk, unsigned long clk_rate)
1819 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1827 pr_err("not supported");
1831 p = stm32mp1_clk_get_parent(priv, clk->id);
1837 /* for LTDC_PX and DSI_PX case */
1838 return pll_set_output_rate(clk->dev, _PLL4, _DIV_Q, clk_rate);
1844 static void stm32mp1_osc_clk_init(const char *name,
1845 struct stm32mp1_clk_priv *priv,
1849 struct udevice *dev = NULL;
1851 priv->osc[index] = 0;
1853 if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) {
1854 if (clk_request(dev, &clk))
1855 pr_err("%s request", name);
1857 priv->osc[index] = clk_get_rate(&clk);
1859 priv->osc_dev[index] = dev;
1862 static void stm32mp1_osc_init(struct udevice *dev)
1864 struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1866 const char *name[NB_OSC] = {
1872 [_I2S_CKIN] = "i2s_ckin",
1875 for (i = 0; i < NB_OSC; i++) {
1876 stm32mp1_osc_clk_init(name[i], priv, i);
1877 debug("%d: %s => %x\n", i, name[i], (u32)priv->osc[i]);
1881 static void __maybe_unused stm32mp1_clk_dump(struct stm32mp1_clk_priv *priv)
1886 printf("Clocks:\n");
1887 for (i = 0; i < _PARENT_NB; i++) {
1888 printf("- %s : %s MHz\n",
1889 stm32mp1_clk_parent_name[i],
1890 strmhz(buf, stm32mp1_clk_get(priv, i)));
1892 printf("Source Clocks:\n");
1893 for (i = 0; i < _PARENT_SEL_NB; i++) {
1894 p = (readl(priv->base + priv->data->sel[i].offset) >>
1895 priv->data->sel[i].src) & priv->data->sel[i].msk;
1896 if (p < priv->data->sel[i].nb_parent) {
1897 s = priv->data->sel[i].parent[p];
1898 printf("- %s(%d) => parent %s(%d)\n",
1899 stm32mp1_clk_parent_sel_name[i], i,
1900 stm32mp1_clk_parent_name[s], s);
1902 printf("- %s(%d) => parent index %d is invalid\n",
1903 stm32mp1_clk_parent_sel_name[i], i, p);
1908 #ifdef CONFIG_CMD_CLK
1909 int soc_clk_dump(void)
1911 struct udevice *dev;
1912 struct stm32mp1_clk_priv *priv;
1915 ret = uclass_get_device_by_driver(UCLASS_CLK,
1916 DM_GET_DRIVER(stm32mp1_clock),
1921 priv = dev_get_priv(dev);
1923 stm32mp1_clk_dump(priv);
1929 static int stm32mp1_clk_probe(struct udevice *dev)
1932 struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1934 priv->base = dev_read_addr(dev->parent);
1935 if (priv->base == FDT_ADDR_T_NONE)
1938 priv->data = (void *)&stm32mp1_data;
1940 if (!priv->data->gate || !priv->data->sel ||
1944 stm32mp1_osc_init(dev);
1946 #ifdef STM32MP1_CLOCK_TREE_INIT
1947 /* clock tree init is done only one time, before relocation */
1948 if (!(gd->flags & GD_FLG_RELOC))
1949 result = stm32mp1_clktree(dev);
1952 #ifndef CONFIG_SPL_BUILD
1954 /* display debug information for probe after relocation */
1955 if (gd->flags & GD_FLG_RELOC)
1956 stm32mp1_clk_dump(priv);
1959 #if defined(CONFIG_DISPLAY_CPUINFO)
1960 if (gd->flags & GD_FLG_RELOC) {
1963 printf("Clocks:\n");
1964 printf("- MPU : %s MHz\n",
1965 strmhz(buf, stm32mp1_clk_get(priv, _CK_MPU)));
1966 printf("- MCU : %s MHz\n",
1967 strmhz(buf, stm32mp1_clk_get(priv, _CK_MCU)));
1968 printf("- AXI : %s MHz\n",
1969 strmhz(buf, stm32mp1_clk_get(priv, _ACLK)));
1970 printf("- PER : %s MHz\n",
1971 strmhz(buf, stm32mp1_clk_get(priv, _CK_PER)));
1972 /* DDRPHYC father */
1973 printf("- DDR : %s MHz\n",
1974 strmhz(buf, stm32mp1_clk_get(priv, _PLL2_R)));
1976 #endif /* CONFIG_DISPLAY_CPUINFO */
1982 static const struct clk_ops stm32mp1_clk_ops = {
1983 .enable = stm32mp1_clk_enable,
1984 .disable = stm32mp1_clk_disable,
1985 .get_rate = stm32mp1_clk_get_rate,
1986 .set_rate = stm32mp1_clk_set_rate,
1989 U_BOOT_DRIVER(stm32mp1_clock) = {
1990 .name = "stm32mp1_clk",
1992 .ops = &stm32mp1_clk_ops,
1993 .priv_auto_alloc_size = sizeof(struct stm32mp1_clk_priv),
1994 .probe = stm32mp1_clk_probe,