drivers/clk/clk_stm32f7.c

   1 /*
   2  * (C) Copyright 2017
   3  * Vikas Manocha, <vikas.manocha@st.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7 #include <common.h>
   8 #include <clk-uclass.h>
   9 #include <dm.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/rcc.h>
  12 #include <asm/arch/stm32.h>
  13 #include <asm/arch/stm32_periph.h>
  14
  15 #define RCC_CR_HSION                    BIT(0)
  16 #define RCC_CR_HSEON                    BIT(16)
  17 #define RCC_CR_HSERDY                   BIT(17)
  18 #define RCC_CR_HSEBYP                   BIT(18)
  19 #define RCC_CR_CSSON                    BIT(19)
  20 #define RCC_CR_PLLON                    BIT(24)
  21 #define RCC_CR_PLLRDY                   BIT(25)
  22
  23 #define RCC_PLLCFGR_PLLM_MASK           GENMASK(5, 0)
  24 #define RCC_PLLCFGR_PLLN_MASK           GENMASK(14, 6)
  25 #define RCC_PLLCFGR_PLLP_MASK           GENMASK(17, 16)
  26 #define RCC_PLLCFGR_PLLQ_MASK           GENMASK(27, 24)
  27 #define RCC_PLLCFGR_PLLSRC              BIT(22)
  28 #define RCC_PLLCFGR_PLLM_SHIFT          0
  29 #define RCC_PLLCFGR_PLLN_SHIFT          6
  30 #define RCC_PLLCFGR_PLLP_SHIFT          16
  31 #define RCC_PLLCFGR_PLLQ_SHIFT          24
  32
  33 #define RCC_CFGR_AHB_PSC_MASK           GENMASK(7, 4)
  34 #define RCC_CFGR_APB1_PSC_MASK          GENMASK(12, 10)
  35 #define RCC_CFGR_APB2_PSC_MASK          GENMASK(15, 13)
  36 #define RCC_CFGR_SW0                    BIT(0)
  37 #define RCC_CFGR_SW1                    BIT(1)
  38 #define RCC_CFGR_SW_MASK                GENMASK(1, 0)
  39 #define RCC_CFGR_SW_HSI                 0
  40 #define RCC_CFGR_SW_HSE                 RCC_CFGR_SW0
  41 #define RCC_CFGR_SW_PLL                 RCC_CFGR_SW1
  42 #define RCC_CFGR_SWS0                   BIT(2)
  43 #define RCC_CFGR_SWS1                   BIT(3)
  44 #define RCC_CFGR_SWS_MASK               GENMASK(3, 2)
  45 #define RCC_CFGR_SWS_HSI                0
  46 #define RCC_CFGR_SWS_HSE                RCC_CFGR_SWS0
  47 #define RCC_CFGR_SWS_PLL                RCC_CFGR_SWS1
  48 #define RCC_CFGR_HPRE_SHIFT             4
  49 #define RCC_CFGR_PPRE1_SHIFT            10
  50 #define RCC_CFGR_PPRE2_SHIFT            13
  51
  52 /*
  53  * Offsets of some PWR registers
  54  */
  55 #define PWR_CR1_ODEN                    BIT(16)
  56 #define PWR_CR1_ODSWEN                  BIT(17)
  57 #define PWR_CSR1_ODRDY                  BIT(16)
  58 #define PWR_CSR1_ODSWRDY                BIT(17)
  59
  60 struct pll_psc {
  61         u8      pll_m;
  62         u16     pll_n;
  63         u8      pll_p;
  64         u8      pll_q;
  65         u8      ahb_psc;
  66         u8      apb1_psc;
  67         u8      apb2_psc;
  68 };
  69
  70 #define AHB_PSC_1                       0
  71 #define AHB_PSC_2                       0x8
  72 #define AHB_PSC_4                       0x9
  73 #define AHB_PSC_8                       0xA
  74 #define AHB_PSC_16                      0xB
  75 #define AHB_PSC_64                      0xC
  76 #define AHB_PSC_128                     0xD
  77 #define AHB_PSC_256                     0xE
  78 #define AHB_PSC_512                     0xF
  79
  80 #define APB_PSC_1                       0
  81 #define APB_PSC_2                       0x4
  82 #define APB_PSC_4                       0x5
  83 #define APB_PSC_8                       0x6
  84 #define APB_PSC_16                      0x7
  85
  86 struct stm32_clk {
  87         struct stm32_rcc_regs *base;
  88 };
  89
  90 #if !defined(CONFIG_STM32_HSE_HZ)
  91 #error "CONFIG_STM32_HSE_HZ not defined!"
  92 #else
  93 #if (CONFIG_STM32_HSE_HZ == 25000000)
  94 #if (CONFIG_SYS_CLK_FREQ == 200000000)
  95 /* 200 MHz */
  96 struct pll_psc sys_pll_psc = {
  97         .pll_m = 25,
  98         .pll_n = 400,
  99         .pll_p = 2,
 100         .pll_q = 8,
 101         .ahb_psc = AHB_PSC_1,
 102         .apb1_psc = APB_PSC_4,
 103         .apb2_psc = APB_PSC_2
 104 };
 105 #endif
 106 #else
 107 #error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists"
 108 #endif
 109 #endif
 110
 111 static int configure_clocks(struct udevice *dev)
 112 {
 113         struct stm32_clk *priv = dev_get_priv(dev);
 114         struct stm32_rcc_regs *regs = priv->base;
 115
 116         /* Reset RCC configuration */
 117         setbits_le32(&regs->cr, RCC_CR_HSION);
 118         writel(0, &regs->cfgr); /* Reset CFGR */
 119         clrbits_le32(&regs->cr, (RCC_CR_HSEON | RCC_CR_CSSON
 120                 | RCC_CR_PLLON));
 121         writel(0x24003010, &regs->pllcfgr); /* Reset value from RM */
 122         clrbits_le32(&regs->cr, RCC_CR_HSEBYP);
 123         writel(0, &regs->cir); /* Disable all interrupts */
 124
 125         /* Configure for HSE+PLL operation */
 126         setbits_le32(&regs->cr, RCC_CR_HSEON);
 127         while (!(readl(&regs->cr) & RCC_CR_HSERDY))
 128                 ;
 129
 130         setbits_le32(&regs->cfgr, ((
 131                 sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT)
 132                 | (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT)
 133                 | (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
 134
 135         /* Configure the main PLL */
 136         uint32_t pllcfgr = 0;
 137         pllcfgr = RCC_PLLCFGR_PLLSRC; /* pll source HSE */
 138         pllcfgr |= sys_pll_psc.pll_m << RCC_PLLCFGR_PLLM_SHIFT;
 139         pllcfgr |= sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT;
 140         pllcfgr |= ((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT;
 141         pllcfgr |= sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT;
 142         writel(pllcfgr, &regs->pllcfgr);
 143
 144         /* Enable the main PLL */
 145         setbits_le32(&regs->cr, RCC_CR_PLLON);
 146         while (!(readl(&regs->cr) & RCC_CR_PLLRDY))
 147                 ;
 148
 149         /* Enable high performance mode, System frequency up to 200 MHz */
 150         setbits_le32(&regs->apb1enr, RCC_APB1ENR_PWREN);
 151         setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODEN);
 152         /* Infinite wait! */
 153         while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODRDY))
 154                 ;
 155         /* Enable the Over-drive switch */
 156         setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODSWEN);
 157         /* Infinite wait! */
 158         while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODSWRDY))
 159                 ;
 160
 161         stm32_flash_latency_cfg(5);
 162         clrbits_le32(&regs->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
 163         setbits_le32(&regs->cfgr, RCC_CFGR_SW_PLL);
 164
 165         while ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) !=
 166                         RCC_CFGR_SWS_PLL)
 167                 ;
 168
 169         return 0;
 170 }
 171
 172 unsigned long clock_get(enum clock clck)
 173 {
 174         u32 sysclk = 0;
 175         u32 shift = 0;
 176         /* Prescaler table lookups for clock computation */
 177         u8 ahb_psc_table[16] = {
 178                 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
 179         };
 180         u8 apb_psc_table[8] = {
 181                 0, 0, 0, 0, 1, 2, 3, 4
 182         };
 183
 184         if ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) ==
 185                         RCC_CFGR_SWS_PLL) {
 186                 u16 pllm, plln, pllp;
 187                 pllm = (readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
 188                 plln = ((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
 189                         >> RCC_PLLCFGR_PLLN_SHIFT);
 190                 pllp = ((((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
 191                         >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
 192                 sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp;
 193         }
 194
 195         switch (clck) {
 196         case CLOCK_CORE:
 197                 return sysclk;
 198                 break;
 199         case CLOCK_AHB:
 200                 shift = ahb_psc_table[(
 201                         (readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK)
 202                         >> RCC_CFGR_HPRE_SHIFT)];
 203                 return sysclk >>= shift;
 204                 break;
 205         case CLOCK_APB1:
 206                 shift = apb_psc_table[(
 207                         (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB1_PSC_MASK)
 208                         >> RCC_CFGR_PPRE1_SHIFT)];
 209                 return sysclk >>= shift;
 210                 break;
 211         case CLOCK_APB2:
 212                 shift = apb_psc_table[(
 213                         (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB2_PSC_MASK)
 214                         >> RCC_CFGR_PPRE2_SHIFT)];
 215                 return sysclk >>= shift;
 216                 break;
 217         default:
 218                 return 0;
 219                 break;
 220         }
 221 }
 222
 223 static int stm32_clk_enable(struct clk *clk)
 224 {
 225         struct stm32_clk *priv = dev_get_priv(clk->dev);
 226         struct stm32_rcc_regs *regs = priv->base;
 227         u32 offset = clk->id / 32;
 228         u32 bit_index = clk->id % 32;
 229
 230         debug("%s: clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n",
 231               __func__, clk->id, offset, bit_index);
 232         setbits_le32(&regs->ahb1enr + offset, BIT(bit_index));
 233
 234         return 0;
 235 }
 236
 237 void clock_setup(int peripheral)
 238 {
 239         switch (peripheral) {
 240         case SYSCFG_CLOCK_CFG:
 241                 setbits_le32(&STM32_RCC->apb2enr, RCC_APB2ENR_SYSCFGEN);
 242                 break;
 243         case TIMER2_CLOCK_CFG:
 244                 setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN);
 245                 break;
 246         case STMMAC_CLOCK_CFG:
 247                 setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_EN);
 248                 setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_RX_EN);
 249                 setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_TX_EN);
 250                 break;
 251         default:
 252                 break;
 253         }
 254 }
 255
 256 static int stm32_clk_probe(struct udevice *dev)
 257 {
 258         debug("%s: stm32_clk_probe\n", __func__);
 259
 260         struct stm32_clk *priv = dev_get_priv(dev);
 261         fdt_addr_t addr;
 262
 263         addr = devfdt_get_addr(dev);
 264         if (addr == FDT_ADDR_T_NONE)
 265                 return -EINVAL;
 266
 267         priv->base = (struct stm32_rcc_regs *)addr;
 268
 269         configure_clocks(dev);
 270
 271         return 0;
 272 }
 273
 274 static int stm32_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
 275 {
 276         debug("%s(clk=%p)\n", __func__, clk);
 277
 278         if (args->args_count != 2) {
 279                 debug("Invaild args_count: %d\n", args->args_count);
 280                 return -EINVAL;
 281         }
 282
 283         if (args->args_count)
 284                 clk->id = args->args[1];
 285         else
 286                 clk->id = 0;
 287
 288         return 0;
 289 }
 290
 291 static struct clk_ops stm32_clk_ops = {
 292         .of_xlate       = stm32_clk_of_xlate,
 293         .enable         = stm32_clk_enable,
 294 };
 295
 296 static const struct udevice_id stm32_clk_ids[] = {
 297         { .compatible = "st,stm32f42xx-rcc"},
 298         {}
 299 };
 300
 301 U_BOOT_DRIVER(stm32f7_clk) = {
 302         .name           = "stm32f7_clk",
 303         .id             = UCLASS_CLK,
 304         .of_match       = stm32_clk_ids,
 305         .ops            = &stm32_clk_ops,
 306         .probe          = stm32_clk_probe,
 307         .flags          = DM_FLAG_PRE_RELOC,
 308 };