2 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
3 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <clk-uclass.h>
11 #include <stm32_rcc.h>
14 #include <asm/arch/stm32.h>
15 #include <asm/arch/stm32_pwr.h>
17 #include <dt-bindings/mfd/stm32f7-rcc.h>
19 #define RCC_CR_HSION BIT(0)
20 #define RCC_CR_HSEON BIT(16)
21 #define RCC_CR_HSERDY BIT(17)
22 #define RCC_CR_HSEBYP BIT(18)
23 #define RCC_CR_CSSON BIT(19)
24 #define RCC_CR_PLLON BIT(24)
25 #define RCC_CR_PLLRDY BIT(25)
26 #define RCC_CR_PLLSAION BIT(28)
27 #define RCC_CR_PLLSAIRDY BIT(29)
29 #define RCC_PLLCFGR_PLLM_MASK GENMASK(5, 0)
30 #define RCC_PLLCFGR_PLLN_MASK GENMASK(14, 6)
31 #define RCC_PLLCFGR_PLLP_MASK GENMASK(17, 16)
32 #define RCC_PLLCFGR_PLLQ_MASK GENMASK(27, 24)
33 #define RCC_PLLCFGR_PLLSRC BIT(22)
34 #define RCC_PLLCFGR_PLLM_SHIFT 0
35 #define RCC_PLLCFGR_PLLN_SHIFT 6
36 #define RCC_PLLCFGR_PLLP_SHIFT 16
37 #define RCC_PLLCFGR_PLLQ_SHIFT 24
39 #define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4)
40 #define RCC_CFGR_APB1_PSC_MASK GENMASK(12, 10)
41 #define RCC_CFGR_APB2_PSC_MASK GENMASK(15, 13)
42 #define RCC_CFGR_SW0 BIT(0)
43 #define RCC_CFGR_SW1 BIT(1)
44 #define RCC_CFGR_SW_MASK GENMASK(1, 0)
45 #define RCC_CFGR_SW_HSI 0
46 #define RCC_CFGR_SW_HSE RCC_CFGR_SW0
47 #define RCC_CFGR_SW_PLL RCC_CFGR_SW1
48 #define RCC_CFGR_SWS0 BIT(2)
49 #define RCC_CFGR_SWS1 BIT(3)
50 #define RCC_CFGR_SWS_MASK GENMASK(3, 2)
51 #define RCC_CFGR_SWS_HSI 0
52 #define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0
53 #define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1
54 #define RCC_CFGR_HPRE_SHIFT 4
55 #define RCC_CFGR_PPRE1_SHIFT 10
56 #define RCC_CFGR_PPRE2_SHIFT 13
58 #define RCC_PLLSAICFGR_PLLSAIN_MASK GENMASK(14, 6)
59 #define RCC_PLLSAICFGR_PLLSAIP_MASK GENMASK(17, 16)
60 #define RCC_PLLSAICFGR_PLLSAIQ_MASK GENMASK(27, 24)
61 #define RCC_PLLSAICFGR_PLLSAIR_MASK GENMASK(30, 28)
62 #define RCC_PLLSAICFGR_PLLSAIN_SHIFT 6
63 #define RCC_PLLSAICFGR_PLLSAIP_SHIFT 16
64 #define RCC_PLLSAICFGR_PLLSAIQ_SHIFT 24
65 #define RCC_PLLSAICFGR_PLLSAIR_SHIFT 28
66 #define RCC_PLLSAICFGR_PLLSAIP_4 BIT(16)
67 #define RCC_PLLSAICFGR_PLLSAIQ_4 BIT(26)
68 #define RCC_PLLSAICFGR_PLLSAIR_2 BIT(29)
70 #define RCC_DCKCFGRX_TIMPRE BIT(24)
71 #define RCC_DCKCFGRX_CK48MSEL BIT(27)
72 #define RCC_DCKCFGRX_SDMMC1SEL BIT(28)
73 #define RCC_DCKCFGR2_SDMMC2SEL BIT(29)
76 * RCC AHB1ENR specific definitions
78 #define RCC_AHB1ENR_ETHMAC_EN BIT(25)
79 #define RCC_AHB1ENR_ETHMAC_TX_EN BIT(26)
80 #define RCC_AHB1ENR_ETHMAC_RX_EN BIT(27)
83 * RCC APB1ENR specific definitions
85 #define RCC_APB1ENR_TIM2EN BIT(0)
86 #define RCC_APB1ENR_PWREN BIT(28)
89 * RCC APB2ENR specific definitions
91 #define RCC_APB2ENR_SYSCFGEN BIT(14)
92 #define RCC_APB2ENR_SAI1EN BIT(22)
100 static const struct stm32_clk_info stm32f4_clk_info = {
106 .ahb_psc = AHB_PSC_1,
107 .apb1_psc = APB_PSC_4,
108 .apb2_psc = APB_PSC_2,
110 .has_overdrive = false,
114 static const struct stm32_clk_info stm32f7_clk_info = {
120 .ahb_psc = AHB_PSC_1,
121 .apb1_psc = APB_PSC_4,
122 .apb2_psc = APB_PSC_2,
124 .has_overdrive = true,
129 struct stm32_rcc_regs *base;
130 struct stm32_pwr_regs *pwr_regs;
131 struct stm32_clk_info info;
132 unsigned long hse_rate;
135 static int configure_clocks(struct udevice *dev)
137 struct stm32_clk *priv = dev_get_priv(dev);
138 struct stm32_rcc_regs *regs = priv->base;
139 struct stm32_pwr_regs *pwr = priv->pwr_regs;
140 struct pll_psc *sys_pll_psc = &priv->info.sys_pll_psc;
142 /* Reset RCC configuration */
143 setbits_le32(®s->cr, RCC_CR_HSION);
144 writel(0, ®s->cfgr); /* Reset CFGR */
145 clrbits_le32(®s->cr, (RCC_CR_HSEON | RCC_CR_CSSON
146 | RCC_CR_PLLON | RCC_CR_PLLSAION));
147 writel(0x24003010, ®s->pllcfgr); /* Reset value from RM */
148 clrbits_le32(®s->cr, RCC_CR_HSEBYP);
149 writel(0, ®s->cir); /* Disable all interrupts */
151 /* Configure for HSE+PLL operation */
152 setbits_le32(®s->cr, RCC_CR_HSEON);
153 while (!(readl(®s->cr) & RCC_CR_HSERDY))
156 setbits_le32(®s->cfgr, ((
157 sys_pll_psc->ahb_psc << RCC_CFGR_HPRE_SHIFT)
158 | (sys_pll_psc->apb1_psc << RCC_CFGR_PPRE1_SHIFT)
159 | (sys_pll_psc->apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
161 /* Configure the main PLL */
162 setbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLSRC); /* pll source HSE */
163 clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLM_MASK,
164 sys_pll_psc->pll_m << RCC_PLLCFGR_PLLM_SHIFT);
165 clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLN_MASK,
166 sys_pll_psc->pll_n << RCC_PLLCFGR_PLLN_SHIFT);
167 clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLP_MASK,
168 ((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT);
169 clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLQ_MASK,
170 sys_pll_psc->pll_q << RCC_PLLCFGR_PLLQ_SHIFT);
172 /* configure SDMMC clock */
173 if (priv->info.v2) { /*stm32f7 case */
174 /* select PLLQ as 48MHz clock source */
175 clrbits_le32(®s->dckcfgr2, RCC_DCKCFGRX_CK48MSEL);
177 /* select 48MHz as SDMMC1 clock source */
178 clrbits_le32(®s->dckcfgr2, RCC_DCKCFGRX_SDMMC1SEL);
180 /* select 48MHz as SDMMC2 clock source */
181 clrbits_le32(®s->dckcfgr2, RCC_DCKCFGR2_SDMMC2SEL);
182 } else { /* stm32f4 case */
183 /* select PLLQ as 48MHz clock source */
184 clrbits_le32(®s->dckcfgr, RCC_DCKCFGRX_CK48MSEL);
186 /* select 48MHz as SDMMC1 clock source */
187 clrbits_le32(®s->dckcfgr, RCC_DCKCFGRX_SDMMC1SEL);
190 /* Enable the main PLL */
191 setbits_le32(®s->cr, RCC_CR_PLLON);
192 while (!(readl(®s->cr) & RCC_CR_PLLRDY))
195 setbits_le32(®s->apb1enr, RCC_APB1ENR_PWREN);
197 if (priv->info.has_overdrive) {
199 * Enable high performance mode
200 * System frequency up to 200 MHz
202 setbits_le32(&pwr->cr1, PWR_CR1_ODEN);
204 while (!(readl(&pwr->csr1) & PWR_CSR1_ODRDY))
206 /* Enable the Over-drive switch */
207 setbits_le32(&pwr->cr1, PWR_CR1_ODSWEN);
209 while (!(readl(&pwr->csr1) & PWR_CSR1_ODSWRDY))
213 stm32_flash_latency_cfg(5);
214 clrbits_le32(®s->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
215 setbits_le32(®s->cfgr, RCC_CFGR_SW_PLL);
217 while ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) !=
221 #ifdef CONFIG_ETH_DESIGNWARE
222 /* gate the SYSCFG clock, needed to set RMII ethernet interface */
223 setbits_le32(®s->apb2enr, RCC_APB2ENR_SYSCFGEN);
229 static bool stm32_clk_get_ck48msel(struct stm32_clk *priv)
231 struct stm32_rcc_regs *regs = priv->base;
233 if (priv->info.v2) /*stm32f7 case */
234 return readl(®s->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL;
237 return readl(®s->dckcfgr) & RCC_DCKCFGRX_CK48MSEL;
240 static unsigned long stm32_clk_get_pllsai_vco_rate(struct stm32_clk *priv)
242 struct stm32_rcc_regs *regs = priv->base;
245 pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
246 pllsain = ((readl(®s->pllsaicfgr) & RCC_PLLSAICFGR_PLLSAIN_MASK)
247 >> RCC_PLLSAICFGR_PLLSAIN_SHIFT);
249 return ((priv->hse_rate / pllm) * pllsain);
252 static unsigned long stm32_clk_get_pllsai_rate(struct stm32_clk *priv,
253 enum pllsai_div output)
255 struct stm32_rcc_regs *regs = priv->base;
260 pll_div_output = ((((readl(®s->pllsaicfgr)
261 & RCC_PLLSAICFGR_PLLSAIP_MASK)
262 >> RCC_PLLSAICFGR_PLLSAIP_SHIFT) + 1) << 1);
265 pll_div_output = (readl(®s->pllsaicfgr)
266 & RCC_PLLSAICFGR_PLLSAIQ_MASK)
267 >> RCC_PLLSAICFGR_PLLSAIQ_SHIFT;
270 pll_div_output = (readl(®s->pllsaicfgr)
271 & RCC_PLLSAICFGR_PLLSAIR_MASK)
272 >> RCC_PLLSAICFGR_PLLSAIR_SHIFT;
275 pr_err("incorrect PLLSAI output %d\n", output);
279 return (stm32_clk_get_pllsai_vco_rate(priv) / pll_div_output);
282 static bool stm32_get_timpre(struct stm32_clk *priv)
284 struct stm32_rcc_regs *regs = priv->base;
287 if (priv->info.v2) /*stm32f7 case */
288 val = readl(®s->dckcfgr2);
290 val = readl(®s->dckcfgr);
291 /* get timer prescaler */
292 return !!(val & RCC_DCKCFGRX_TIMPRE);
295 static u32 stm32_get_hclk_rate(struct stm32_rcc_regs *regs, u32 sysclk)
298 /* Prescaler table lookups for clock computation */
299 u8 ahb_psc_table[16] = {
300 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
303 shift = ahb_psc_table[(
304 (readl(®s->cfgr) & RCC_CFGR_AHB_PSC_MASK)
305 >> RCC_CFGR_HPRE_SHIFT)];
307 return sysclk >> shift;
310 static u8 stm32_get_apb_shift(struct stm32_rcc_regs *regs, enum apb apb)
312 /* Prescaler table lookups for clock computation */
313 u8 apb_psc_table[8] = {
314 0, 0, 0, 0, 1, 2, 3, 4
318 return apb_psc_table[(
319 (readl(®s->cfgr) & RCC_CFGR_APB1_PSC_MASK)
320 >> RCC_CFGR_PPRE1_SHIFT)];
322 return apb_psc_table[(
323 (readl(®s->cfgr) & RCC_CFGR_APB2_PSC_MASK)
324 >> RCC_CFGR_PPRE2_SHIFT)];
327 static u32 stm32_get_timer_rate(struct stm32_clk *priv, u32 sysclk,
330 struct stm32_rcc_regs *regs = priv->base;
331 u8 shift = stm32_get_apb_shift(regs, apb);
333 if (stm32_get_timpre(priv))
335 * if APB prescaler is configured to a
336 * division factor of 1, 2 or 4
342 return stm32_get_hclk_rate(regs, sysclk);
344 return (sysclk >> shift) * 4;
348 * if APB prescaler is configured to a
349 * division factor of 1
354 return (sysclk >> shift) * 2;
357 static ulong stm32_clk_get_rate(struct clk *clk)
359 struct stm32_clk *priv = dev_get_priv(clk->dev);
360 struct stm32_rcc_regs *regs = priv->base;
364 u16 pllm, plln, pllp, pllq;
366 if ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) ==
368 pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
369 plln = ((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
370 >> RCC_PLLCFGR_PLLN_SHIFT);
371 pllp = ((((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
372 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
373 pllq = ((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLQ_MASK)
374 >> RCC_PLLCFGR_PLLQ_SHIFT);
375 vco = (priv->hse_rate / pllm) * plln;
383 * AHB CLOCK: 3 x 32 bits consecutive registers are used :
384 * AHB1, AHB2 and AHB3
386 case STM32F7_AHB1_CLOCK(GPIOA) ... STM32F7_AHB3_CLOCK(QSPI):
387 return stm32_get_hclk_rate(regs, sysclk);
389 case STM32F7_APB1_CLOCK(TIM2) ... STM32F7_APB1_CLOCK(UART8):
390 /* For timer clock, an additionnal prescaler is used*/
392 case STM32F7_APB1_CLOCK(TIM2):
393 case STM32F7_APB1_CLOCK(TIM3):
394 case STM32F7_APB1_CLOCK(TIM4):
395 case STM32F7_APB1_CLOCK(TIM5):
396 case STM32F7_APB1_CLOCK(TIM6):
397 case STM32F7_APB1_CLOCK(TIM7):
398 case STM32F7_APB1_CLOCK(TIM12):
399 case STM32F7_APB1_CLOCK(TIM13):
400 case STM32F7_APB1_CLOCK(TIM14):
401 return stm32_get_timer_rate(priv, sysclk, APB1);
403 return (sysclk >> stm32_get_apb_shift(regs, APB1));
406 case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(LTDC):
409 * particular case for SDMMC1 and SDMMC2 :
410 * 48Mhz source clock can be from main PLL or from
413 case STM32F7_APB2_CLOCK(SDMMC1):
414 case STM32F7_APB2_CLOCK(SDMMC2):
415 if (clk->id == STM32F7_APB2_CLOCK(SDMMC1))
416 sdmmcxsel_bit = RCC_DCKCFGRX_SDMMC1SEL;
418 sdmmcxsel_bit = RCC_DCKCFGR2_SDMMC2SEL;
420 if (readl(®s->dckcfgr2) & sdmmcxsel_bit)
421 /* System clock is selected as SDMMC1 clock */
424 * 48 MHz can be generated by either PLLSAIP
425 * or by PLLQ depending of CK48MSEL bit of RCC_DCKCFGR
427 if (stm32_clk_get_ck48msel(priv))
428 return stm32_clk_get_pllsai_rate(priv, PLLSAIP);
433 /* For timer clock, an additionnal prescaler is used*/
434 case STM32F7_APB2_CLOCK(TIM1):
435 case STM32F7_APB2_CLOCK(TIM8):
436 case STM32F7_APB2_CLOCK(TIM9):
437 case STM32F7_APB2_CLOCK(TIM10):
438 case STM32F7_APB2_CLOCK(TIM11):
439 return stm32_get_timer_rate(priv, sysclk, APB2);
442 return (sysclk >> stm32_get_apb_shift(regs, APB2));
445 pr_err("clock index %ld out of range\n", clk->id);
450 static ulong stm32_set_rate(struct clk *clk, ulong rate)
455 static int stm32_clk_enable(struct clk *clk)
457 struct stm32_clk *priv = dev_get_priv(clk->dev);
458 struct stm32_rcc_regs *regs = priv->base;
459 u32 offset = clk->id / 32;
460 u32 bit_index = clk->id % 32;
462 debug("%s: clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n",
463 __func__, clk->id, offset, bit_index);
464 setbits_le32(®s->ahb1enr + offset, BIT(bit_index));
469 static int stm32_clk_probe(struct udevice *dev)
471 struct ofnode_phandle_args args;
472 struct udevice *fixed_clock_dev = NULL;
476 debug("%s\n", __func__);
478 struct stm32_clk *priv = dev_get_priv(dev);
481 addr = dev_read_addr(dev);
482 if (addr == FDT_ADDR_T_NONE)
485 priv->base = (struct stm32_rcc_regs *)addr;
487 switch (dev_get_driver_data(dev)) {
489 memcpy(&priv->info, &stm32f4_clk_info,
490 sizeof(struct stm32_clk_info));
493 memcpy(&priv->info, &stm32f7_clk_info,
494 sizeof(struct stm32_clk_info));
500 /* retrieve HSE frequency (external oscillator) */
501 err = uclass_get_device_by_name(UCLASS_CLK, "clk-hse",
505 pr_err("Can't find fixed clock (%d)", err);
509 err = clk_request(fixed_clock_dev, &clk);
511 pr_err("Can't request %s clk (%d)", fixed_clock_dev->name,
517 * set pllm factor accordingly to the external oscillator
518 * frequency (HSE). For STM32F4 and STM32F7, we want VCO
520 * if input PLL frequency is 25Mhz, divide it by 25
523 priv->hse_rate = clk_get_rate(&clk);
525 if (priv->hse_rate < 1000000) {
526 pr_err("%s: unexpected HSE clock rate = %ld \"n", __func__,
531 priv->info.sys_pll_psc.pll_m = priv->hse_rate / 1000000;
533 if (priv->info.has_overdrive) {
534 err = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
537 debug("%s: can't find syscon device (%d)\n", __func__,
542 priv->pwr_regs = (struct stm32_pwr_regs *)ofnode_get_addr(args.node);
545 configure_clocks(dev);
550 static int stm32_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
552 debug("%s(clk=%p)\n", __func__, clk);
554 if (args->args_count != 2) {
555 debug("Invaild args_count: %d\n", args->args_count);
559 if (args->args_count)
560 clk->id = args->args[1];
567 static struct clk_ops stm32_clk_ops = {
568 .of_xlate = stm32_clk_of_xlate,
569 .enable = stm32_clk_enable,
570 .get_rate = stm32_clk_get_rate,
571 .set_rate = stm32_set_rate,
574 U_BOOT_DRIVER(stm32fx_clk) = {
575 .name = "stm32fx_rcc_clock",
577 .ops = &stm32_clk_ops,
578 .probe = stm32_clk_probe,
579 .priv_auto_alloc_size = sizeof(struct stm32_clk),
580 .flags = DM_FLAG_PRE_RELOC,