drivers/clk/clk_stm32f.c

   1 /*
   2  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
   3  * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <clk-uclass.h>
  10 #include <dm.h>
  11 #include <stm32_rcc.h>
  12
  13 #include <asm/io.h>
  14 #include <asm/arch/stm32.h>
  15 #include <asm/arch/stm32_periph.h>
  16 #include <asm/arch/stm32_pwr.h>
  17
  18 #include <dt-bindings/mfd/stm32f7-rcc.h>
  19
  20 #define RCC_CR_HSION                    BIT(0)
  21 #define RCC_CR_HSEON                    BIT(16)
  22 #define RCC_CR_HSERDY                   BIT(17)
  23 #define RCC_CR_HSEBYP                   BIT(18)
  24 #define RCC_CR_CSSON                    BIT(19)
  25 #define RCC_CR_PLLON                    BIT(24)
  26 #define RCC_CR_PLLRDY                   BIT(25)
  27
  28 #define RCC_PLLCFGR_PLLM_MASK           GENMASK(5, 0)
  29 #define RCC_PLLCFGR_PLLN_MASK           GENMASK(14, 6)
  30 #define RCC_PLLCFGR_PLLP_MASK           GENMASK(17, 16)
  31 #define RCC_PLLCFGR_PLLQ_MASK           GENMASK(27, 24)
  32 #define RCC_PLLCFGR_PLLSRC              BIT(22)
  33 #define RCC_PLLCFGR_PLLM_SHIFT          0
  34 #define RCC_PLLCFGR_PLLN_SHIFT          6
  35 #define RCC_PLLCFGR_PLLP_SHIFT          16
  36 #define RCC_PLLCFGR_PLLQ_SHIFT          24
  37
  38 #define RCC_CFGR_AHB_PSC_MASK           GENMASK(7, 4)
  39 #define RCC_CFGR_APB1_PSC_MASK          GENMASK(12, 10)
  40 #define RCC_CFGR_APB2_PSC_MASK          GENMASK(15, 13)
  41 #define RCC_CFGR_SW0                    BIT(0)
  42 #define RCC_CFGR_SW1                    BIT(1)
  43 #define RCC_CFGR_SW_MASK                GENMASK(1, 0)
  44 #define RCC_CFGR_SW_HSI                 0
  45 #define RCC_CFGR_SW_HSE                 RCC_CFGR_SW0
  46 #define RCC_CFGR_SW_PLL                 RCC_CFGR_SW1
  47 #define RCC_CFGR_SWS0                   BIT(2)
  48 #define RCC_CFGR_SWS1                   BIT(3)
  49 #define RCC_CFGR_SWS_MASK               GENMASK(3, 2)
  50 #define RCC_CFGR_SWS_HSI                0
  51 #define RCC_CFGR_SWS_HSE                RCC_CFGR_SWS0
  52 #define RCC_CFGR_SWS_PLL                RCC_CFGR_SWS1
  53 #define RCC_CFGR_HPRE_SHIFT             4
  54 #define RCC_CFGR_PPRE1_SHIFT            10
  55 #define RCC_CFGR_PPRE2_SHIFT            13
  56
  57 /*
  58  * RCC AHB1ENR specific definitions
  59  */
  60 #define RCC_AHB1ENR_ETHMAC_EN           BIT(25)
  61 #define RCC_AHB1ENR_ETHMAC_TX_EN        BIT(26)
  62 #define RCC_AHB1ENR_ETHMAC_RX_EN        BIT(27)
  63
  64 /*
  65  * RCC APB1ENR specific definitions
  66  */
  67 #define RCC_APB1ENR_TIM2EN              BIT(0)
  68 #define RCC_APB1ENR_PWREN               BIT(28)
  69
  70 /*
  71  * RCC APB2ENR specific definitions
  72  */
  73 #define RCC_APB2ENR_SYSCFGEN            BIT(14)
  74
  75 struct stm32_clk_info stm32f4_clk_info = {
  76         /* 180 MHz */
  77         .sys_pll_psc = {
  78                 .pll_m = 8,
  79                 .pll_n = 360,
  80                 .pll_p = 2,
  81                 .pll_q = 8,
  82                 .ahb_psc = AHB_PSC_1,
  83                 .apb1_psc = APB_PSC_4,
  84                 .apb2_psc = APB_PSC_2,
  85         },
  86         .has_overdrive = false,
  87 };
  88
  89 struct stm32_clk_info stm32f7_clk_info = {
  90         /* 200 MHz */
  91         .sys_pll_psc = {
  92                 .pll_m = 25,
  93                 .pll_n = 400,
  94                 .pll_p = 2,
  95                 .pll_q = 8,
  96                 .ahb_psc = AHB_PSC_1,
  97                 .apb1_psc = APB_PSC_4,
  98                 .apb2_psc = APB_PSC_2,
  99         },
 100         .has_overdrive = true,
 101 };
 102
 103 struct stm32_clk {
 104         struct stm32_rcc_regs *base;
 105         struct stm32_pwr_regs *pwr_regs;
 106         struct stm32_clk_info *info;
 107 };
 108
 109 static int configure_clocks(struct udevice *dev)
 110 {
 111         struct stm32_clk *priv = dev_get_priv(dev);
 112         struct stm32_rcc_regs *regs = priv->base;
 113         struct stm32_pwr_regs *pwr = priv->pwr_regs;
 114         struct pll_psc sys_pll_psc = priv->info->sys_pll_psc;
 115
 116         /* Reset RCC configuration */
 117         setbits_le32(&regs->cr, RCC_CR_HSION);
 118         writel(0, &regs->cfgr); /* Reset CFGR */
 119         clrbits_le32(&regs->cr, (RCC_CR_HSEON | RCC_CR_CSSON
 120                 | RCC_CR_PLLON));
 121         writel(0x24003010, &regs->pllcfgr); /* Reset value from RM */
 122         clrbits_le32(&regs->cr, RCC_CR_HSEBYP);
 123         writel(0, &regs->cir); /* Disable all interrupts */
 124
 125         /* Configure for HSE+PLL operation */
 126         setbits_le32(&regs->cr, RCC_CR_HSEON);
 127         while (!(readl(&regs->cr) & RCC_CR_HSERDY))
 128                 ;
 129
 130         setbits_le32(&regs->cfgr, ((
 131                 sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT)
 132                 | (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT)
 133                 | (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
 134
 135         /* Configure the main PLL */
 136         setbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLSRC); /* pll source HSE */
 137         clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLM_MASK,
 138                         sys_pll_psc.pll_m << RCC_PLLCFGR_PLLM_SHIFT);
 139         clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLN_MASK,
 140                         sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT);
 141         clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLP_MASK,
 142                         ((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT);
 143         clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLQ_MASK,
 144                         sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT);
 145
 146         /* Enable the main PLL */
 147         setbits_le32(&regs->cr, RCC_CR_PLLON);
 148         while (!(readl(&regs->cr) & RCC_CR_PLLRDY))
 149                 ;
 150
 151         setbits_le32(&regs->apb1enr, RCC_APB1ENR_PWREN);
 152
 153         if (priv->info->has_overdrive) {
 154                 /*
 155                  * Enable high performance mode
 156                  * System frequency up to 200 MHz
 157                  */
 158                 setbits_le32(&pwr->cr1, PWR_CR1_ODEN);
 159                 /* Infinite wait! */
 160                 while (!(readl(&pwr->csr1) & PWR_CSR1_ODRDY))
 161                         ;
 162                 /* Enable the Over-drive switch */
 163                 setbits_le32(&pwr->cr1, PWR_CR1_ODSWEN);
 164                 /* Infinite wait! */
 165                 while (!(readl(&pwr->csr1) & PWR_CSR1_ODSWRDY))
 166                         ;
 167         }
 168
 169         stm32_flash_latency_cfg(5);
 170         clrbits_le32(&regs->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
 171         setbits_le32(&regs->cfgr, RCC_CFGR_SW_PLL);
 172
 173         while ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) !=
 174                         RCC_CFGR_SWS_PLL)
 175                 ;
 176
 177         return 0;
 178 }
 179
 180 static unsigned long stm32_clk_get_rate(struct clk *clk)
 181 {
 182         struct stm32_clk *priv = dev_get_priv(clk->dev);
 183         struct stm32_rcc_regs *regs = priv->base;
 184         u32 sysclk = 0;
 185         u32 shift = 0;
 186         u16 pllm, plln, pllp;
 187         /* Prescaler table lookups for clock computation */
 188         u8 ahb_psc_table[16] = {
 189                 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
 190         };
 191         u8 apb_psc_table[8] = {
 192                 0, 0, 0, 0, 1, 2, 3, 4
 193         };
 194
 195         if ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) ==
 196                         RCC_CFGR_SWS_PLL) {
 197                 pllm = (readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
 198                 plln = ((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
 199                         >> RCC_PLLCFGR_PLLN_SHIFT);
 200                 pllp = ((((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
 201                         >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
 202                 sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp;
 203         } else {
 204                 return -EINVAL;
 205         }
 206
 207         switch (clk->id) {
 208         /*
 209          * AHB CLOCK: 3 x 32 bits consecutive registers are used :
 210          * AHB1, AHB2 and AHB3
 211          */
 212         case STM32F7_AHB1_CLOCK(GPIOA) ... STM32F7_AHB3_CLOCK(QSPI):
 213                 shift = ahb_psc_table[(
 214                         (readl(&regs->cfgr) & RCC_CFGR_AHB_PSC_MASK)
 215                         >> RCC_CFGR_HPRE_SHIFT)];
 216                 return sysclk >>= shift;
 217         /* APB1 CLOCK */
 218         case STM32F7_APB1_CLOCK(TIM2) ... STM32F7_APB1_CLOCK(UART8):
 219                 shift = apb_psc_table[(
 220                         (readl(&regs->cfgr) & RCC_CFGR_APB1_PSC_MASK)
 221                         >> RCC_CFGR_PPRE1_SHIFT)];
 222                 return sysclk >>= shift;
 223         /* APB2 CLOCK */
 224         case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(LTDC):
 225                 shift = apb_psc_table[(
 226                         (readl(&regs->cfgr) & RCC_CFGR_APB2_PSC_MASK)
 227                         >> RCC_CFGR_PPRE2_SHIFT)];
 228                 return sysclk >>= shift;
 229         default:
 230                 pr_err("clock index %ld out of range\n", clk->id);
 231                 return -EINVAL;
 232         }
 233 }
 234
 235 static int stm32_clk_enable(struct clk *clk)
 236 {
 237         struct stm32_clk *priv = dev_get_priv(clk->dev);
 238         struct stm32_rcc_regs *regs = priv->base;
 239         u32 offset = clk->id / 32;
 240         u32 bit_index = clk->id % 32;
 241
 242         debug("%s: clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n",
 243               __func__, clk->id, offset, bit_index);
 244         setbits_le32(&regs->ahb1enr + offset, BIT(bit_index));
 245
 246         return 0;
 247 }
 248
 249 void clock_setup(int peripheral)
 250 {
 251         switch (peripheral) {
 252         case SYSCFG_CLOCK_CFG:
 253                 setbits_le32(&STM32_RCC->apb2enr, RCC_APB2ENR_SYSCFGEN);
 254                 break;
 255         case TIMER2_CLOCK_CFG:
 256                 setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN);
 257                 break;
 258         case STMMAC_CLOCK_CFG:
 259                 setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_EN);
 260                 setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_RX_EN);
 261                 setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_TX_EN);
 262                 break;
 263         default:
 264                 break;
 265         }
 266 }
 267
 268 static int stm32_clk_probe(struct udevice *dev)
 269 {
 270         struct ofnode_phandle_args args;
 271         int err;
 272
 273         debug("%s\n", __func__);
 274
 275         struct stm32_clk *priv = dev_get_priv(dev);
 276         fdt_addr_t addr;
 277
 278         addr = dev_read_addr(dev);
 279         if (addr == FDT_ADDR_T_NONE)
 280                 return -EINVAL;
 281
 282         priv->base = (struct stm32_rcc_regs *)addr;
 283
 284         switch (dev_get_driver_data(dev)) {
 285         case STM32F4:
 286                 priv->info = &stm32f4_clk_info;
 287                 break;
 288         case STM32F7:
 289                 priv->info = &stm32f7_clk_info;
 290                 break;
 291         default:
 292                 return -EINVAL;
 293         }
 294
 295         if (priv->info->has_overdrive) {
 296                 err = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
 297                                                  &args);
 298                 if (err) {
 299                         debug("%s: can't find syscon device (%d)\n", __func__,
 300                               err);
 301                         return err;
 302                 }
 303
 304                 priv->pwr_regs = (struct stm32_pwr_regs *)ofnode_get_addr(args.node);
 305         }
 306
 307         configure_clocks(dev);
 308
 309         return 0;
 310 }
 311
 312 static int stm32_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
 313 {
 314         debug("%s(clk=%p)\n", __func__, clk);
 315
 316         if (args->args_count != 2) {
 317                 debug("Invaild args_count: %d\n", args->args_count);
 318                 return -EINVAL;
 319         }
 320
 321         if (args->args_count)
 322                 clk->id = args->args[1];
 323         else
 324                 clk->id = 0;
 325
 326         return 0;
 327 }
 328
 329 static struct clk_ops stm32_clk_ops = {
 330         .of_xlate       = stm32_clk_of_xlate,
 331         .enable         = stm32_clk_enable,
 332         .get_rate       = stm32_clk_get_rate,
 333 };
 334
 335 U_BOOT_DRIVER(stm32fx_clk) = {
 336         .name                   = "stm32fx_rcc_clock",
 337         .id                     = UCLASS_CLK,
 338         .ops                    = &stm32_clk_ops,
 339         .probe                  = stm32_clk_probe,
 340         .priv_auto_alloc_size   = sizeof(struct stm32_clk),
 341         .flags                  = DM_FLAG_PRE_RELOC,
 342 };