drivers/clk/clk_sandbox_ccf.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2019
   4  * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
   5  *
   6  * Common Clock Framework [CCF] driver for Sandbox
   7  */
   8
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <clk.h>
  12 #include <asm/clk.h>
  13 #include <clk-uclass.h>
  14 #include <linux/clk-provider.h>
  15 #include <sandbox-clk.h>
  16
  17 /*
  18  * Sandbox implementation of CCF primitives necessary for clk-uclass testing
  19  *
  20  * --- Sandbox PLLv3 ---
  21  */
  22 struct clk_pllv3 {
  23         struct clk      clk;
  24         u32             div_mask;
  25         u32             div_shift;
  26 };
  27
  28 static ulong clk_pllv3_get_rate(struct clk *clk)
  29 {
  30         unsigned long parent_rate = clk_get_parent_rate(clk);
  31
  32         return parent_rate * 24;
  33 }
  34
  35 static const struct clk_ops clk_pllv3_generic_ops = {
  36         .get_rate       = clk_pllv3_get_rate,
  37 };
  38
  39 struct clk *sandbox_clk_pllv3(enum sandbox_pllv3_type type, const char *name,
  40                               const char *parent_name, void __iomem *base,
  41                               u32 div_mask)
  42 {
  43         struct clk_pllv3 *pll;
  44         struct clk *clk;
  45         char *drv_name = "sandbox_clk_pllv3";
  46         int ret;
  47
  48         pll = kzalloc(sizeof(*pll), GFP_KERNEL);
  49         if (!pll)
  50                 return ERR_PTR(-ENOMEM);
  51
  52         pll->div_mask = div_mask;
  53         clk = &pll->clk;
  54
  55         ret = clk_register(clk, drv_name, name, parent_name);
  56         if (ret) {
  57                 kfree(pll);
  58                 return ERR_PTR(ret);
  59         }
  60
  61         return clk;
  62 }
  63
  64 U_BOOT_DRIVER(sandbox_clk_pll_generic) = {
  65         .name   = "sandbox_clk_pllv3",
  66         .id     = UCLASS_CLK,
  67         .ops    = &clk_pllv3_generic_ops,
  68 };
  69
  70 /* --- Sandbox PLLv3 --- */
  71 /* --- Sandbox Gate  --- */
  72 struct clk_gate2 {
  73         struct clk clk;
  74         bool    state;
  75 };
  76
  77 #define to_clk_gate2(_clk) container_of(_clk, struct clk_gate2, clk)
  78
  79 static int clk_gate2_enable(struct clk *clk)
  80 {
  81         struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev));
  82
  83         gate->state = 1;
  84         return 0;
  85 }
  86
  87 static int clk_gate2_disable(struct clk *clk)
  88 {
  89         struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev));
  90
  91         gate->state = 0;
  92         return 0;
  93 }
  94
  95 static const struct clk_ops clk_gate2_ops = {
  96         .enable = clk_gate2_enable,
  97         .disable = clk_gate2_disable,
  98         .get_rate = clk_generic_get_rate,
  99 };
 100
 101 struct clk *sandbox_clk_register_gate2(struct device *dev, const char *name,
 102                                        const char *parent_name,
 103                                        unsigned long flags, void __iomem *reg,
 104                                        u8 bit_idx, u8 cgr_val,
 105                                        u8 clk_gate2_flags)
 106 {
 107         struct clk_gate2 *gate;
 108         struct clk *clk;
 109         int ret;
 110
 111         gate = kzalloc(sizeof(*gate), GFP_KERNEL);
 112         if (!gate)
 113                 return ERR_PTR(-ENOMEM);
 114
 115         gate->state = 0;
 116         clk = &gate->clk;
 117
 118         ret = clk_register(clk, "sandbox_clk_gate2", name, parent_name);
 119         if (ret) {
 120                 kfree(gate);
 121                 return ERR_PTR(ret);
 122         }
 123
 124         return clk;
 125 }
 126
 127 U_BOOT_DRIVER(sandbox_clk_gate2) = {
 128         .name   = "sandbox_clk_gate2",
 129         .id     = UCLASS_CLK,
 130         .ops    = &clk_gate2_ops,
 131 };
 132
 133 /* --- Sandbox Gate --- */
 134 /* The CCF core driver itself */
 135 static const struct udevice_id sandbox_clk_ccf_test_ids[] = {
 136         { .compatible = "sandbox,clk-ccf" },
 137         { }
 138 };
 139
 140 static const char *const usdhc_sels[] = { "pll3_60m", "pll3_80m", };
 141
 142 static int sandbox_clk_ccf_probe(struct udevice *dev)
 143 {
 144         void *base = NULL;
 145         u32 reg;
 146
 147         clk_dm(SANDBOX_CLK_PLL3,
 148                sandbox_clk_pllv3(SANDBOX_PLLV3_USB, "pll3_usb_otg", "osc",
 149                                  base + 0x10, 0x3));
 150
 151         clk_dm(SANDBOX_CLK_PLL3_60M,
 152                sandbox_clk_fixed_factor("pll3_60m",  "pll3_usb_otg",   1, 8));
 153
 154         clk_dm(SANDBOX_CLK_PLL3_80M,
 155                sandbox_clk_fixed_factor("pll3_80m",  "pll3_usb_otg",   1, 6));
 156
 157         /* The HW adds +1 to the divider value (2+1) is the divider */
 158         reg = (2 << 19);
 159         clk_dm(SANDBOX_CLK_ECSPI_ROOT,
 160                sandbox_clk_divider("ecspi_root", "pll3_60m", &reg, 19, 6));
 161
 162         clk_dm(SANDBOX_CLK_ECSPI1,
 163                sandbox_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0));
 164
 165         /* Select 'pll3_60m' */
 166         reg = 0;
 167         clk_dm(SANDBOX_CLK_USDHC1_SEL,
 168                sandbox_clk_mux("usdhc1_sel", &reg, 16, 1, usdhc_sels,
 169                                ARRAY_SIZE(usdhc_sels)));
 170
 171         /* Select 'pll3_80m' */
 172         reg = BIT(17);
 173         clk_dm(SANDBOX_CLK_USDHC2_SEL,
 174                sandbox_clk_mux("usdhc2_sel", &reg, 17, 1, usdhc_sels,
 175                                ARRAY_SIZE(usdhc_sels)));
 176
 177         return 0;
 178 }
 179
 180 U_BOOT_DRIVER(sandbox_clk_ccf) = {
 181         .name = "sandbox_clk_ccf",
 182         .id = UCLASS_CLK,
 183         .probe = sandbox_clk_ccf_probe,
 184         .of_match = sandbox_clk_ccf_test_ids,
 185 };