drivers/clk/clk_sandbox_ccf.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2019
   4  * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
   5  *
   6  * Common Clock Framework [CCF] driver for Sandbox
   7  */
   8
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <clk.h>
  12 #include <asm/clk.h>
  13 #include <clk-uclass.h>
  14 #include <dm/devres.h>
  15 #include <linux/clk-provider.h>
  16 #include <sandbox-clk.h>
  17 #include <linux/err.h>
  18
  19 /*
  20  * Sandbox implementation of CCF primitives necessary for clk-uclass testing
  21  *
  22  * --- Sandbox PLLv3 ---
  23  */
  24 struct clk_pllv3 {
  25         struct clk      clk;
  26         u32             div_mask;
  27         u32             div_shift;
  28 };
  29
  30 int sandbox_clk_enable_count(struct clk *clk)
  31 {
  32         struct clk *clkp = NULL;
  33         int ret;
  34
  35         ret = clk_get_by_id(clk->id, &clkp);
  36         if (ret)
  37                 return 0;
  38
  39         return clkp->enable_count;
  40 }
  41
  42 static ulong clk_pllv3_get_rate(struct clk *clk)
  43 {
  44         unsigned long parent_rate = clk_get_parent_rate(clk);
  45
  46         return parent_rate * 24;
  47 }
  48
  49 static const struct clk_ops clk_pllv3_generic_ops = {
  50         .get_rate       = clk_pllv3_get_rate,
  51 };
  52
  53 struct clk *sandbox_clk_pllv3(enum sandbox_pllv3_type type, const char *name,
  54                               const char *parent_name, void __iomem *base,
  55                               u32 div_mask)
  56 {
  57         struct clk_pllv3 *pll;
  58         struct clk *clk;
  59         char *drv_name = "sandbox_clk_pllv3";
  60         int ret;
  61
  62         pll = kzalloc(sizeof(*pll), GFP_KERNEL);
  63         if (!pll)
  64                 return ERR_PTR(-ENOMEM);
  65
  66         pll->div_mask = div_mask;
  67         clk = &pll->clk;
  68
  69         ret = clk_register(clk, drv_name, name, parent_name);
  70         if (ret) {
  71                 kfree(pll);
  72                 return ERR_PTR(ret);
  73         }
  74
  75         return clk;
  76 }
  77
  78 U_BOOT_DRIVER(sandbox_clk_pll_generic) = {
  79         .name   = "sandbox_clk_pllv3",
  80         .id     = UCLASS_CLK,
  81         .ops    = &clk_pllv3_generic_ops,
  82 };
  83
  84 /* --- Sandbox PLLv3 --- */
  85 /* --- Sandbox Gate  --- */
  86 struct clk_gate2 {
  87         struct clk clk;
  88         bool    state;
  89 };
  90
  91 #define to_clk_gate2(_clk) container_of(_clk, struct clk_gate2, clk)
  92
  93 static int clk_gate2_enable(struct clk *clk)
  94 {
  95         struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev));
  96
  97         gate->state = 1;
  98         return 0;
  99 }
 100
 101 static int clk_gate2_disable(struct clk *clk)
 102 {
 103         struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev));
 104
 105         gate->state = 0;
 106         return 0;
 107 }
 108
 109 static const struct clk_ops clk_gate2_ops = {
 110         .enable = clk_gate2_enable,
 111         .disable = clk_gate2_disable,
 112         .get_rate = clk_generic_get_rate,
 113 };
 114
 115 struct clk *sandbox_clk_register_gate2(struct device *dev, const char *name,
 116                                        const char *parent_name,
 117                                        unsigned long flags, void __iomem *reg,
 118                                        u8 bit_idx, u8 cgr_val,
 119                                        u8 clk_gate2_flags)
 120 {
 121         struct clk_gate2 *gate;
 122         struct clk *clk;
 123         int ret;
 124
 125         gate = kzalloc(sizeof(*gate), GFP_KERNEL);
 126         if (!gate)
 127                 return ERR_PTR(-ENOMEM);
 128
 129         gate->state = 0;
 130         clk = &gate->clk;
 131
 132         ret = clk_register(clk, "sandbox_clk_gate2", name, parent_name);
 133         if (ret) {
 134                 kfree(gate);
 135                 return ERR_PTR(ret);
 136         }
 137
 138         return clk;
 139 }
 140
 141 U_BOOT_DRIVER(sandbox_clk_gate2) = {
 142         .name   = "sandbox_clk_gate2",
 143         .id     = UCLASS_CLK,
 144         .ops    = &clk_gate2_ops,
 145 };
 146
 147 static unsigned long sandbox_clk_composite_divider_recalc_rate(struct clk *clk)
 148 {
 149         struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk);
 150         struct clk_composite *composite = (struct clk_composite *)clk->data;
 151         ulong parent_rate = clk_get_parent_rate(&composite->clk);
 152         unsigned int val;
 153
 154         val = divider->io_divider_val;
 155         val >>= divider->shift;
 156         val &= clk_div_mask(divider->width);
 157
 158         return divider_recalc_rate(clk, parent_rate, val, divider->table,
 159                                    divider->flags, divider->width);
 160 }
 161
 162 static const struct clk_ops sandbox_clk_composite_divider_ops = {
 163         .get_rate = sandbox_clk_composite_divider_recalc_rate,
 164 };
 165
 166 struct clk *sandbox_clk_composite(const char *name,
 167                                   const char * const *parent_names,
 168                                   int num_parents, void __iomem *reg,
 169                                   unsigned long flags)
 170 {
 171         struct clk *clk = ERR_PTR(-ENOMEM);
 172         struct clk_divider *div = NULL;
 173         struct clk_gate *gate = NULL;
 174         struct clk_mux *mux = NULL;
 175
 176         mux = kzalloc(sizeof(*mux), GFP_KERNEL);
 177         if (!mux)
 178                 goto fail;
 179
 180         mux->reg = reg;
 181         mux->shift = 24;
 182         mux->mask = 0x7;
 183         mux->num_parents = num_parents;
 184         mux->flags = flags;
 185         mux->parent_names = parent_names;
 186
 187         div = kzalloc(sizeof(*div), GFP_KERNEL);
 188         if (!div)
 189                 goto fail;
 190
 191         div->reg = reg;
 192         div->shift = 16;
 193         div->width = 3;
 194         div->flags = CLK_DIVIDER_ROUND_CLOSEST | flags;
 195
 196         gate = kzalloc(sizeof(*gate), GFP_KERNEL);
 197         if (!gate)
 198                 goto fail;
 199
 200         gate->reg = reg;
 201         gate->bit_idx = 28;
 202         gate->flags = flags;
 203
 204         clk = clk_register_composite(NULL, name,
 205                                      parent_names, num_parents,
 206                                      &mux->clk, &clk_mux_ops, &div->clk,
 207                                      &sandbox_clk_composite_divider_ops,
 208                                      &gate->clk, &clk_gate_ops, flags);
 209         if (IS_ERR(clk))
 210                 goto fail;
 211
 212         return clk;
 213
 214 fail:
 215         kfree(gate);
 216         kfree(div);
 217         kfree(mux);
 218         return ERR_CAST(clk);
 219 }
 220
 221 /* --- Sandbox Gate --- */
 222 /* The CCF core driver itself */
 223 static const struct udevice_id sandbox_clk_ccf_test_ids[] = {
 224         { .compatible = "sandbox,clk-ccf" },
 225         { }
 226 };
 227
 228 static const char *const usdhc_sels[] = { "pll3_60m", "pll3_80m", };
 229 static const char *const i2c_sels[] = { "pll3_60m", "pll3_80m", };
 230
 231 static int sandbox_clk_ccf_probe(struct udevice *dev)
 232 {
 233         void *base = NULL;
 234         u32 reg;
 235
 236         clk_dm(SANDBOX_CLK_PLL3,
 237                sandbox_clk_pllv3(SANDBOX_PLLV3_USB, "pll3_usb_otg", "osc",
 238                                  base + 0x10, 0x3));
 239
 240         clk_dm(SANDBOX_CLK_PLL3_60M,
 241                sandbox_clk_fixed_factor("pll3_60m",  "pll3_usb_otg",   1, 8));
 242
 243         clk_dm(SANDBOX_CLK_PLL3_80M,
 244                sandbox_clk_fixed_factor("pll3_80m",  "pll3_usb_otg",   1, 6));
 245
 246         /* The HW adds +1 to the divider value (2+1) is the divider */
 247         reg = (2 << 19);
 248         clk_dm(SANDBOX_CLK_ECSPI_ROOT,
 249                sandbox_clk_divider("ecspi_root", "pll3_60m", &reg, 19, 6));
 250
 251         clk_dm(SANDBOX_CLK_ECSPI1,
 252                sandbox_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0));
 253
 254         /* Select 'pll3_60m' */
 255         reg = 0;
 256         clk_dm(SANDBOX_CLK_USDHC1_SEL,
 257                sandbox_clk_mux("usdhc1_sel", &reg, 16, 1, usdhc_sels,
 258                                ARRAY_SIZE(usdhc_sels)));
 259
 260         /* Select 'pll3_80m' */
 261         reg = BIT(17);
 262         clk_dm(SANDBOX_CLK_USDHC2_SEL,
 263                sandbox_clk_mux("usdhc2_sel", &reg, 17, 1, usdhc_sels,
 264                                ARRAY_SIZE(usdhc_sels)));
 265
 266         reg = BIT(28) | BIT(24) | BIT(16);
 267         clk_dm(SANDBOX_CLK_I2C,
 268                sandbox_clk_composite("i2c", i2c_sels, ARRAY_SIZE(i2c_sels),
 269                                      &reg, 0));
 270
 271         clk_dm(SANDBOX_CLK_I2C_ROOT,
 272                sandbox_clk_gate2("i2c_root", "i2c", base + 0x7c, 0));
 273
 274         return 0;
 275 }
 276
 277 U_BOOT_DRIVER(sandbox_clk_ccf) = {
 278         .name = "sandbox_clk_ccf",
 279         .id = UCLASS_CLK,
 280         .probe = sandbox_clk_ccf_probe,
 281         .of_match = sandbox_clk_ccf_test_ids,
 282 };