drivers/clk/clk_sandbox_ccf.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2019
   4  * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
   5  *
   6  * Common Clock Framework [CCF] driver for Sandbox
   7  */
   8
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <clk.h>
  12 #include <malloc.h>
  13 #include <asm/clk.h>
  14 #include <clk-uclass.h>
  15 #include <dm/devres.h>
  16 #include <linux/clk-provider.h>
  17 #include <sandbox-clk.h>
  18 #include <linux/err.h>
  19
  20 /*
  21  * Sandbox implementation of CCF primitives necessary for clk-uclass testing
  22  *
  23  * --- Sandbox PLLv3 ---
  24  */
  25 struct clk_pllv3 {
  26         struct clk      clk;
  27         u32             div_mask;
  28         u32             div_shift;
  29 };
  30
  31 int sandbox_clk_enable_count(struct clk *clk)
  32 {
  33         struct clk *clkp = NULL;
  34         int ret;
  35
  36         ret = clk_get_by_id(clk->id, &clkp);
  37         if (ret)
  38                 return 0;
  39
  40         return clkp->enable_count;
  41 }
  42
  43 static ulong clk_pllv3_get_rate(struct clk *clk)
  44 {
  45         unsigned long parent_rate = clk_get_parent_rate(clk);
  46
  47         return parent_rate * 24;
  48 }
  49
  50 static const struct clk_ops clk_pllv3_generic_ops = {
  51         .get_rate       = clk_pllv3_get_rate,
  52 };
  53
  54 struct clk *sandbox_clk_pllv3(enum sandbox_pllv3_type type, const char *name,
  55                               const char *parent_name, void __iomem *base,
  56                               u32 div_mask)
  57 {
  58         struct clk_pllv3 *pll;
  59         struct clk *clk;
  60         char *drv_name = "sandbox_clk_pllv3";
  61         int ret;
  62
  63         pll = kzalloc(sizeof(*pll), GFP_KERNEL);
  64         if (!pll)
  65                 return ERR_PTR(-ENOMEM);
  66
  67         pll->div_mask = div_mask;
  68         clk = &pll->clk;
  69
  70         ret = clk_register(clk, drv_name, name, parent_name);
  71         if (ret) {
  72                 kfree(pll);
  73                 return ERR_PTR(ret);
  74         }
  75
  76         return clk;
  77 }
  78
  79 U_BOOT_DRIVER(sandbox_clk_pll_generic) = {
  80         .name   = "sandbox_clk_pllv3",
  81         .id     = UCLASS_CLK,
  82         .ops    = &clk_pllv3_generic_ops,
  83 };
  84
  85 /* --- Sandbox PLLv3 --- */
  86 /* --- Sandbox Gate  --- */
  87 struct clk_gate2 {
  88         struct clk clk;
  89         bool    state;
  90 };
  91
  92 #define to_clk_gate2(_clk) container_of(_clk, struct clk_gate2, clk)
  93
  94 static int clk_gate2_enable(struct clk *clk)
  95 {
  96         struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev));
  97
  98         gate->state = 1;
  99         return 0;
 100 }
 101
 102 static int clk_gate2_disable(struct clk *clk)
 103 {
 104         struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev));
 105
 106         gate->state = 0;
 107         return 0;
 108 }
 109
 110 static const struct clk_ops clk_gate2_ops = {
 111         .enable = clk_gate2_enable,
 112         .disable = clk_gate2_disable,
 113         .get_rate = clk_generic_get_rate,
 114 };
 115
 116 struct clk *sandbox_clk_register_gate2(struct device *dev, const char *name,
 117                                        const char *parent_name,
 118                                        unsigned long flags, void __iomem *reg,
 119                                        u8 bit_idx, u8 cgr_val,
 120                                        u8 clk_gate2_flags)
 121 {
 122         struct clk_gate2 *gate;
 123         struct clk *clk;
 124         int ret;
 125
 126         gate = kzalloc(sizeof(*gate), GFP_KERNEL);
 127         if (!gate)
 128                 return ERR_PTR(-ENOMEM);
 129
 130         gate->state = 0;
 131         clk = &gate->clk;
 132
 133         ret = clk_register(clk, "sandbox_clk_gate2", name, parent_name);
 134         if (ret) {
 135                 kfree(gate);
 136                 return ERR_PTR(ret);
 137         }
 138
 139         return clk;
 140 }
 141
 142 U_BOOT_DRIVER(sandbox_clk_gate2) = {
 143         .name   = "sandbox_clk_gate2",
 144         .id     = UCLASS_CLK,
 145         .ops    = &clk_gate2_ops,
 146 };
 147
 148 static unsigned long sandbox_clk_composite_divider_recalc_rate(struct clk *clk)
 149 {
 150         struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk);
 151         struct clk_composite *composite = (struct clk_composite *)clk->data;
 152         ulong parent_rate = clk_get_parent_rate(&composite->clk);
 153         unsigned int val;
 154
 155         val = divider->io_divider_val;
 156         val >>= divider->shift;
 157         val &= clk_div_mask(divider->width);
 158
 159         return divider_recalc_rate(clk, parent_rate, val, divider->table,
 160                                    divider->flags, divider->width);
 161 }
 162
 163 static const struct clk_ops sandbox_clk_composite_divider_ops = {
 164         .get_rate = sandbox_clk_composite_divider_recalc_rate,
 165 };
 166
 167 struct clk *sandbox_clk_composite(const char *name,
 168                                   const char * const *parent_names,
 169                                   int num_parents, void __iomem *reg,
 170                                   unsigned long flags)
 171 {
 172         struct clk *clk = ERR_PTR(-ENOMEM);
 173         struct clk_divider *div = NULL;
 174         struct clk_gate *gate = NULL;
 175         struct clk_mux *mux = NULL;
 176
 177         mux = kzalloc(sizeof(*mux), GFP_KERNEL);
 178         if (!mux)
 179                 goto fail;
 180
 181         mux->reg = reg;
 182         mux->shift = 24;
 183         mux->mask = 0x7;
 184         mux->num_parents = num_parents;
 185         mux->flags = flags;
 186         mux->parent_names = parent_names;
 187
 188         div = kzalloc(sizeof(*div), GFP_KERNEL);
 189         if (!div)
 190                 goto fail;
 191
 192         div->reg = reg;
 193         div->shift = 16;
 194         div->width = 3;
 195         div->flags = CLK_DIVIDER_ROUND_CLOSEST | flags;
 196
 197         gate = kzalloc(sizeof(*gate), GFP_KERNEL);
 198         if (!gate)
 199                 goto fail;
 200
 201         gate->reg = reg;
 202         gate->bit_idx = 28;
 203         gate->flags = flags;
 204
 205         clk = clk_register_composite(NULL, name,
 206                                      parent_names, num_parents,
 207                                      &mux->clk, &clk_mux_ops, &div->clk,
 208                                      &sandbox_clk_composite_divider_ops,
 209                                      &gate->clk, &clk_gate_ops, flags);
 210         if (IS_ERR(clk))
 211                 goto fail;
 212
 213         return clk;
 214
 215 fail:
 216         kfree(gate);
 217         kfree(div);
 218         kfree(mux);
 219         return ERR_CAST(clk);
 220 }
 221
 222 /* --- Sandbox Gate --- */
 223 /* The CCF core driver itself */
 224 static const struct udevice_id sandbox_clk_ccf_test_ids[] = {
 225         { .compatible = "sandbox,clk-ccf" },
 226         { }
 227 };
 228
 229 static const char *const usdhc_sels[] = { "pll3_60m", "pll3_80m", };
 230 static const char *const i2c_sels[] = { "pll3_60m", "pll3_80m", };
 231
 232 static int sandbox_clk_ccf_probe(struct udevice *dev)
 233 {
 234         void *base = NULL;
 235         u32 reg;
 236
 237         clk_dm(SANDBOX_CLK_PLL3,
 238                sandbox_clk_pllv3(SANDBOX_PLLV3_USB, "pll3_usb_otg", "osc",
 239                                  base + 0x10, 0x3));
 240
 241         clk_dm(SANDBOX_CLK_PLL3_60M,
 242                sandbox_clk_fixed_factor("pll3_60m",  "pll3_usb_otg",   1, 8));
 243
 244         clk_dm(SANDBOX_CLK_PLL3_80M,
 245                sandbox_clk_fixed_factor("pll3_80m",  "pll3_usb_otg",   1, 6));
 246
 247         /* The HW adds +1 to the divider value (2+1) is the divider */
 248         reg = (2 << 19);
 249         clk_dm(SANDBOX_CLK_ECSPI_ROOT,
 250                sandbox_clk_divider("ecspi_root", "pll3_60m", &reg, 19, 6));
 251
 252         clk_dm(SANDBOX_CLK_ECSPI1,
 253                sandbox_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0));
 254
 255         /* Select 'pll3_60m' */
 256         reg = 0;
 257         clk_dm(SANDBOX_CLK_USDHC1_SEL,
 258                sandbox_clk_mux("usdhc1_sel", &reg, 16, 1, usdhc_sels,
 259                                ARRAY_SIZE(usdhc_sels)));
 260
 261         /* Select 'pll3_80m' */
 262         reg = BIT(17);
 263         clk_dm(SANDBOX_CLK_USDHC2_SEL,
 264                sandbox_clk_mux("usdhc2_sel", &reg, 17, 1, usdhc_sels,
 265                                ARRAY_SIZE(usdhc_sels)));
 266
 267         reg = BIT(28) | BIT(24) | BIT(16);
 268         clk_dm(SANDBOX_CLK_I2C,
 269                sandbox_clk_composite("i2c", i2c_sels, ARRAY_SIZE(i2c_sels),
 270                                      &reg, 0));
 271
 272         clk_dm(SANDBOX_CLK_I2C_ROOT,
 273                sandbox_clk_gate2("i2c_root", "i2c", base + 0x7c, 0));
 274
 275         return 0;
 276 }
 277
 278 U_BOOT_DRIVER(sandbox_clk_ccf) = {
 279         .name = "sandbox_clk_ccf",
 280         .id = UCLASS_CLK,
 281         .probe = sandbox_clk_ccf_probe,
 282         .of_match = sandbox_clk_ccf_test_ids,
 283 };